| 1 |
121 |
davidgb |
#
|
| 2 |
|
|
# Project automation script for system09
|
| 3 |
|
|
#
|
| 4 |
|
|
# Created for ISE version 11.1
|
| 5 |
|
|
#
|
| 6 |
|
|
# This file contains several Tcl procedures (procs) that you can use to automate
|
| 7 |
|
|
# your project by running from xtclsh or the Project Navigator Tcl console.
|
| 8 |
|
|
# If you load this file (using the Tcl command: source system09.tcl), then you can
|
| 9 |
|
|
# run any of the procs included here.
|
| 10 |
|
|
#
|
| 11 |
|
|
# This script is generated assuming your project has HDL sources.
|
| 12 |
|
|
# Several of the defined procs won't apply to an EDIF or NGC based project.
|
| 13 |
|
|
# If that is the case, simply remove them from this script.
|
| 14 |
|
|
#
|
| 15 |
|
|
# You may also edit any of these procs to customize them. See comments in each
|
| 16 |
|
|
# proc for more instructions.
|
| 17 |
|
|
#
|
| 18 |
|
|
# This file contains the following procedures:
|
| 19 |
|
|
#
|
| 20 |
|
|
# Top Level procs (meant to be called directly by the user):
|
| 21 |
|
|
# run_process: you can use this top-level procedure to run any processes
|
| 22 |
|
|
# that you choose to by adding and removing comments, or by
|
| 23 |
|
|
# adding new entries.
|
| 24 |
|
|
# rebuild_project: you can alternatively use this top-level procedure
|
| 25 |
|
|
# to recreate your entire project, and the run selected processes.
|
| 26 |
|
|
#
|
| 27 |
|
|
# Lower Level (helper) procs (called under in various cases by the top level procs):
|
| 28 |
|
|
# show_help: print some basic information describing how this script works
|
| 29 |
|
|
# add_source_files: adds the listed source files to your project.
|
| 30 |
|
|
# set_project_props: sets the project properties that were in effect when this
|
| 31 |
|
|
# script was generated.
|
| 32 |
|
|
# create_libraries: creates and adds file to VHDL libraries that were defined when
|
| 33 |
|
|
# this script was generated.
|
| 34 |
|
|
# create_partitions: adds any partitions that were defined when this script was generated.
|
| 35 |
|
|
# set_process_props: set the process properties as they were set for your project
|
| 36 |
|
|
# when this script was generated.
|
| 37 |
|
|
#
|
| 38 |
|
|
|
| 39 |
|
|
set myProject "system09"
|
| 40 |
|
|
set myScript "system09.tcl"
|
| 41 |
|
|
|
| 42 |
|
|
#
|
| 43 |
|
|
# Main (top-level) routines
|
| 44 |
|
|
#
|
| 45 |
|
|
|
| 46 |
|
|
#
|
| 47 |
|
|
# run_process
|
| 48 |
|
|
# This procedure is used to run processes on an existing project. You may comment or
|
| 49 |
|
|
# uncomment lines to control which processes are run. This routine is set up to run
|
| 50 |
|
|
# the Implement Design and Generate Programming File processes by default. This proc
|
| 51 |
|
|
# also sets process properties as specified in the "set_process_props" proc. Only
|
| 52 |
|
|
# those properties which have values different from their current settings in the project
|
| 53 |
|
|
# file will be modified in the project.
|
| 54 |
|
|
#
|
| 55 |
|
|
proc run_process {} {
|
| 56 |
|
|
|
| 57 |
|
|
global myScript
|
| 58 |
|
|
global myProject
|
| 59 |
|
|
|
| 60 |
|
|
## put out a 'heartbeat' - so we know something's happening.
|
| 61 |
|
|
puts "\n$myScript: running ($myProject)...\n"
|
| 62 |
|
|
|
| 63 |
|
|
if { ! [ open_project ] } {
|
| 64 |
|
|
return false
|
| 65 |
|
|
}
|
| 66 |
|
|
|
| 67 |
|
|
set_process_props
|
| 68 |
|
|
#
|
| 69 |
|
|
# Remove the comment characters (#'s) to enable the following commands
|
| 70 |
|
|
# process run "Synthesize"
|
| 71 |
|
|
# process run "Translate"
|
| 72 |
|
|
# process run "Map"
|
| 73 |
|
|
# process run "Place & Route"
|
| 74 |
|
|
#
|
| 75 |
|
|
puts "Running 'Implement Design'"
|
| 76 |
|
|
if { ! [ process run "Implement Design" ] } {
|
| 77 |
|
|
puts "$myScript: Implementation run failed, check run output for details."
|
| 78 |
|
|
project close
|
| 79 |
|
|
return
|
| 80 |
|
|
}
|
| 81 |
|
|
puts "Running 'Generate Programming File'"
|
| 82 |
|
|
if { ! [ process run "Generate Programming File" ] } {
|
| 83 |
|
|
puts "$myScript: Generate Programming File run failed, check run output for details."
|
| 84 |
|
|
project close
|
| 85 |
|
|
return
|
| 86 |
|
|
}
|
| 87 |
|
|
|
| 88 |
|
|
puts "Run completed."
|
| 89 |
|
|
project close
|
| 90 |
|
|
|
| 91 |
|
|
}
|
| 92 |
|
|
|
| 93 |
|
|
#
|
| 94 |
|
|
# rebuild_project
|
| 95 |
|
|
#
|
| 96 |
|
|
# This procedure renames the project file (if it exists) and recreates the project.
|
| 97 |
|
|
# It then sets project properties and adds project sources as specified by the
|
| 98 |
|
|
# set_project_props and add_source_files support procs. It recreates VHDL libraries
|
| 99 |
|
|
# and partitions as they existed at the time this script was generated.
|
| 100 |
|
|
#
|
| 101 |
|
|
# It then calls run_process to set process properties and run selected processes.
|
| 102 |
|
|
#
|
| 103 |
|
|
proc rebuild_project {} {
|
| 104 |
|
|
|
| 105 |
|
|
global myScript
|
| 106 |
|
|
global myProject
|
| 107 |
|
|
|
| 108 |
|
|
project close
|
| 109 |
|
|
## put out a 'heartbeat' - so we know something's happening.
|
| 110 |
|
|
puts "\n$myScript: Rebuilding ($myProject)...\n"
|
| 111 |
|
|
|
| 112 |
|
|
set proj_exts [ list ise xise gise ]
|
| 113 |
|
|
foreach ext $proj_exts {
|
| 114 |
|
|
set proj_name "${myProject}.$ext"
|
| 115 |
|
|
if { [ file exists $proj_name ] } {
|
| 116 |
|
|
file delete $proj_name
|
| 117 |
|
|
}
|
| 118 |
|
|
}
|
| 119 |
|
|
|
| 120 |
|
|
project new $myProject
|
| 121 |
|
|
set_project_props
|
| 122 |
|
|
add_source_files
|
| 123 |
|
|
create_libraries
|
| 124 |
|
|
create_partitions
|
| 125 |
|
|
puts "$myScript: project rebuild completed."
|
| 126 |
|
|
|
| 127 |
|
|
run_process
|
| 128 |
|
|
|
| 129 |
|
|
}
|
| 130 |
|
|
|
| 131 |
|
|
#
|
| 132 |
|
|
# Support Routines
|
| 133 |
|
|
#
|
| 134 |
|
|
|
| 135 |
|
|
#
|
| 136 |
|
|
# show_help: print information to help users understand the options available when
|
| 137 |
|
|
# running this script.
|
| 138 |
|
|
#
|
| 139 |
|
|
proc show_help {} {
|
| 140 |
|
|
|
| 141 |
|
|
global myScript
|
| 142 |
|
|
|
| 143 |
|
|
puts ""
|
| 144 |
|
|
puts "usage: xtclsh $myScript <options>"
|
| 145 |
|
|
puts " or you can run xtclsh and then enter 'source $myScript'."
|
| 146 |
|
|
puts ""
|
| 147 |
|
|
puts "options:"
|
| 148 |
|
|
puts " run_process - set properties and run processes."
|
| 149 |
|
|
puts " rebuild_project - rebuild the project from scratch and run processes."
|
| 150 |
|
|
puts " set_project_props - set project properties (device, speed, etc.)"
|
| 151 |
|
|
puts " add_source_files - add source files"
|
| 152 |
|
|
puts " create_libraries - create vhdl libraries"
|
| 153 |
|
|
puts " create_partitions - create partitions"
|
| 154 |
|
|
puts " set_process_props - set process property values"
|
| 155 |
|
|
puts " show_help - print this message"
|
| 156 |
|
|
puts ""
|
| 157 |
|
|
}
|
| 158 |
|
|
|
| 159 |
|
|
proc open_project {} {
|
| 160 |
|
|
|
| 161 |
|
|
global myScript
|
| 162 |
|
|
global myProject
|
| 163 |
|
|
|
| 164 |
|
|
if { ! [ file exists ${myProject}.xise ] } {
|
| 165 |
|
|
## project file isn't there, rebuild it.
|
| 166 |
|
|
puts "Project $myProject not found. Use project_rebuild to recreate it."
|
| 167 |
|
|
return false
|
| 168 |
|
|
}
|
| 169 |
|
|
|
| 170 |
|
|
project open $myProject
|
| 171 |
|
|
|
| 172 |
|
|
return true
|
| 173 |
|
|
|
| 174 |
|
|
}
|
| 175 |
|
|
#
|
| 176 |
|
|
# set_project_props
|
| 177 |
|
|
#
|
| 178 |
|
|
# This procedure sets the project properties as they were set in the project
|
| 179 |
|
|
# at the time this script was generated.
|
| 180 |
|
|
#
|
| 181 |
|
|
proc set_project_props {} {
|
| 182 |
|
|
|
| 183 |
|
|
global myScript
|
| 184 |
|
|
|
| 185 |
|
|
if { ! [ open_project ] } {
|
| 186 |
|
|
return false
|
| 187 |
|
|
}
|
| 188 |
|
|
|
| 189 |
|
|
puts "$myScript: Setting project properties..."
|
| 190 |
|
|
|
| 191 |
|
|
project set family "Virtex5"
|
| 192 |
|
|
project set device "xc5vsx50t"
|
| 193 |
|
|
project set package "ff1136"
|
| 194 |
|
|
project set speed "-3"
|
| 195 |
|
|
project set top_level_module_type "HDL"
|
| 196 |
|
|
project set synthesis_tool "XST (VHDL/Verilog)"
|
| 197 |
|
|
project set simulator "Modelsim-SE Mixed"
|
| 198 |
|
|
project set "Preferred Language" "VHDL"
|
| 199 |
|
|
project set "Enable Message Filtering" "false"
|
| 200 |
|
|
project set "Display Incremental Messages" "false"
|
| 201 |
|
|
|
| 202 |
|
|
}
|
| 203 |
|
|
|
| 204 |
|
|
|
| 205 |
|
|
#
|
| 206 |
|
|
# add_source_files
|
| 207 |
|
|
#
|
| 208 |
|
|
# This procedure add the source files that were known to the project at the
|
| 209 |
|
|
# time this script was generated.
|
| 210 |
|
|
#
|
| 211 |
|
|
proc add_source_files {} {
|
| 212 |
|
|
|
| 213 |
|
|
global myScript
|
| 214 |
|
|
|
| 215 |
|
|
if { ! [ open_project ] } {
|
| 216 |
|
|
return false
|
| 217 |
|
|
}
|
| 218 |
|
|
|
| 219 |
|
|
puts "$myScript: Adding sources to project..."
|
| 220 |
|
|
|
| 221 |
|
|
xfile add "../../src/sys09bug/sys09s3s.vhd"
|
| 222 |
|
|
xfile add "../VHDL/ACIA_Clock.vhd"
|
| 223 |
|
|
xfile add "../VHDL/acia6850.vhd"
|
| 224 |
|
|
xfile add "../VHDL/bit_funcs.vhd"
|
| 225 |
|
|
xfile add "../VHDL/cpu09.vhd"
|
| 226 |
|
|
xfile add "../VHDL/datram.vhd"
|
| 227 |
|
|
xfile add "../VHDL/timer.vhd"
|
| 228 |
|
|
xfile add "../VHDL/trap.vhd"
|
| 229 |
|
|
xfile add "System09_Xilinx_ML506.vhd"
|
| 230 |
|
|
xfile add "ml506.ucf"
|
| 231 |
|
|
|
| 232 |
|
|
# Set the Top Module as well...
|
| 233 |
|
|
project set top "rtl" "system09"
|
| 234 |
|
|
|
| 235 |
|
|
puts "$myScript: project sources reloaded."
|
| 236 |
|
|
|
| 237 |
|
|
} ; # end add_source_files
|
| 238 |
|
|
|
| 239 |
|
|
#
|
| 240 |
|
|
# create_libraries
|
| 241 |
|
|
#
|
| 242 |
|
|
# This procedure defines VHDL libraries and associates files with those libraries.
|
| 243 |
|
|
# It is expected to be used when recreating the project. Any libraries defined
|
| 244 |
|
|
# when this script was generated are recreated by this procedure.
|
| 245 |
|
|
#
|
| 246 |
|
|
proc create_libraries {} {
|
| 247 |
|
|
|
| 248 |
|
|
global myScript
|
| 249 |
|
|
|
| 250 |
|
|
if { ! [ open_project ] } {
|
| 251 |
|
|
return false
|
| 252 |
|
|
}
|
| 253 |
|
|
|
| 254 |
|
|
puts "$myScript: Creating libraries..."
|
| 255 |
|
|
|
| 256 |
|
|
|
| 257 |
|
|
# must close the project or library definitions aren't saved.
|
| 258 |
|
|
project save
|
| 259 |
|
|
|
| 260 |
|
|
} ; # end create_libraries
|
| 261 |
|
|
|
| 262 |
|
|
#
|
| 263 |
|
|
# create_partitions
|
| 264 |
|
|
#
|
| 265 |
|
|
# This procedure creates partitions on instances in your project.
|
| 266 |
|
|
# It is expected to be used when recreating the project. Any partitions
|
| 267 |
|
|
# defined when this script was generated are recreated by this procedure.
|
| 268 |
|
|
#
|
| 269 |
|
|
proc create_partitions {} {
|
| 270 |
|
|
|
| 271 |
|
|
global myScript
|
| 272 |
|
|
|
| 273 |
|
|
if { ! [ open_project ] } {
|
| 274 |
|
|
return false
|
| 275 |
|
|
}
|
| 276 |
|
|
|
| 277 |
|
|
puts "$myScript: Creating Partitions..."
|
| 278 |
|
|
|
| 279 |
|
|
|
| 280 |
|
|
# must close the project or partition definitions aren't saved.
|
| 281 |
|
|
project save
|
| 282 |
|
|
|
| 283 |
|
|
} ; # end create_partitions
|
| 284 |
|
|
|
| 285 |
|
|
#
|
| 286 |
|
|
# set_process_props
|
| 287 |
|
|
#
|
| 288 |
|
|
# This procedure sets properties as requested during script generation (either
|
| 289 |
|
|
# all of the properties, or only those modified from their defaults).
|
| 290 |
|
|
#
|
| 291 |
|
|
proc set_process_props {} {
|
| 292 |
|
|
|
| 293 |
|
|
global myScript
|
| 294 |
|
|
|
| 295 |
|
|
if { ! [ open_project ] } {
|
| 296 |
|
|
return false
|
| 297 |
|
|
}
|
| 298 |
|
|
|
| 299 |
|
|
puts "$myScript: setting process properties..."
|
| 300 |
|
|
|
| 301 |
|
|
project set "Compiled Library Directory" "\$XILINX/<language>/<simulator>"
|
| 302 |
|
|
project set "Global Optimization" "Off" -process "Map"
|
| 303 |
|
|
project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
|
| 304 |
|
|
project set "Place And Route Mode" "Route Only" -process "Place & Route"
|
| 305 |
|
|
project set "Number of Clock Buffers" "32" -process "Synthesize - XST"
|
| 306 |
|
|
project set "Max Fanout" "100000" -process "Synthesize - XST"
|
| 307 |
|
|
project set "Use Clock Enable" "Auto" -process "Synthesize - XST"
|
| 308 |
|
|
project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST"
|
| 309 |
|
|
project set "Use Synchronous Set" "Auto" -process "Synthesize - XST"
|
| 310 |
|
|
project set "Placer Effort Level" "Standard" -process "Map"
|
| 311 |
|
|
project set "LUT Combining" "Off" -process "Map"
|
| 312 |
|
|
project set "Combinatorial Logic Optimization" "false" -process "Map"
|
| 313 |
|
|
project set "Starting Placer Cost Table (1-100)" "1" -process "Map"
|
| 314 |
|
|
project set "Power Reduction" "false" -process "Map"
|
| 315 |
|
|
project set "Register Duplication" "Off" -process "Map"
|
| 316 |
|
|
project set "Reduce Control Sets" "No" -process "Synthesize - XST"
|
| 317 |
|
|
project set "Case Implementation Style" "None" -process "Synthesize - XST"
|
| 318 |
|
|
project set "Decoder Extraction" "true" -process "Synthesize - XST"
|
| 319 |
|
|
project set "Priority Encoder Extraction" "Yes" -process "Synthesize - XST"
|
| 320 |
|
|
project set "Mux Extraction" "Yes" -process "Synthesize - XST"
|
| 321 |
|
|
project set "RAM Extraction" "true" -process "Synthesize - XST"
|
| 322 |
|
|
project set "ROM Extraction" "true" -process "Synthesize - XST"
|
| 323 |
|
|
project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
|
| 324 |
|
|
project set "Logical Shifter Extraction" "true" -process "Synthesize - XST"
|
| 325 |
|
|
project set "Optimization Goal" "Speed" -process "Synthesize - XST"
|
| 326 |
|
|
project set "Optimization Effort" "Normal" -process "Synthesize - XST"
|
| 327 |
|
|
project set "Resource Sharing" "true" -process "Synthesize - XST"
|
| 328 |
|
|
project set "Shift Register Extraction" "true" -process "Synthesize - XST"
|
| 329 |
|
|
project set "XOR Collapsing" "true" -process "Synthesize - XST"
|
| 330 |
|
|
project set "Other Bitgen Command Line Options" "" -process "Generate Programming File"
|
| 331 |
|
|
project set "Generate Detailed Package Parasitics" "false" -process "Generate IBIS Model"
|
| 332 |
|
|
project set "Show All Models" "false" -process "Generate IBIS Model"
|
| 333 |
|
|
project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
|
| 334 |
|
|
project set "Ignore User Timing Constraints" "false" -process "Map"
|
| 335 |
|
|
project set "Use RLOC Constraints" "Yes" -process "Map"
|
| 336 |
|
|
project set "Other Map Command Line Options" "" -process "Map"
|
| 337 |
|
|
project set "Use LOC Constraints" "true" -process "Translate"
|
| 338 |
|
|
project set "Other Ngdbuild Command Line Options" "" -process "Translate"
|
| 339 |
|
|
project set "Ignore User Timing Constraints" "false" -process "Place & Route"
|
| 340 |
|
|
project set "Other Place & Route Command Line Options" "" -process "Place & Route"
|
| 341 |
|
|
project set "Use DSP Block" "Auto" -process "Synthesize - XST"
|
| 342 |
|
|
project set "BPI Reads Per Page" "1" -process "Generate Programming File"
|
| 343 |
|
|
project set "Configuration Pin Busy" "Pull Up" -process "Generate Programming File"
|
| 344 |
|
|
project set "Configuration Clk (Configuration Pins)" "Pull Up" -process "Generate Programming File"
|
| 345 |
|
|
project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
|
| 346 |
|
|
project set "Configuration Pin CS" "Pull Up" -process "Generate Programming File"
|
| 347 |
|
|
project set "DCI Update Mode" "As Required" -process "Generate Programming File"
|
| 348 |
|
|
project set "Configuration Pin DIn" "Pull Up" -process "Generate Programming File"
|
| 349 |
|
|
project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
|
| 350 |
|
|
project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
|
| 351 |
|
|
project set "Create Binary Configuration File" "false" -process "Generate Programming File"
|
| 352 |
|
|
project set "Create Bit File" "true" -process "Generate Programming File"
|
| 353 |
|
|
project set "Enable BitStream Compression" "false" -process "Generate Programming File"
|
| 354 |
|
|
project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
|
| 355 |
|
|
project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
|
| 356 |
|
|
project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
|
| 357 |
|
|
project set "Create ReadBack Data Files" "false" -process "Generate Programming File"
|
| 358 |
|
|
project set "Configuration Pin Init" "Pull Up" -process "Generate Programming File"
|
| 359 |
|
|
project set "Configuration Pin M0" "Pull Up" -process "Generate Programming File"
|
| 360 |
|
|
project set "Configuration Pin M1" "Pull Up" -process "Generate Programming File"
|
| 361 |
|
|
project set "Configuration Pin M2" "Pull Up" -process "Generate Programming File"
|
| 362 |
|
|
project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
|
| 363 |
|
|
project set "Power Down Device if Over Safe Temperature" "false" -process "Generate Programming File"
|
| 364 |
|
|
project set "Configuration Rate" "2" -process "Generate Programming File"
|
| 365 |
|
|
project set "Configuration Pin RdWr" "Pull Up" -process "Generate Programming File"
|
| 366 |
|
|
project set "Retain Configuration Status Register Values after Reconfiguration" "true" -process "Generate Programming File"
|
| 367 |
|
|
project set "SelectMAP Abort Sequence" "Enable" -process "Generate Programming File"
|
| 368 |
|
|
project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
|
| 369 |
|
|
project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
|
| 370 |
|
|
project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
|
| 371 |
|
|
project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
|
| 372 |
|
|
project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
|
| 373 |
|
|
project set "Watchdog Timer Mode" "Off" -process "Generate Programming File"
|
| 374 |
|
|
project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
|
| 375 |
|
|
project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
|
| 376 |
|
|
project set "Drive Done Pin High" "false" -process "Generate Programming File"
|
| 377 |
|
|
project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
|
| 378 |
|
|
project set "Wait for DCI Match (Output Events)" "Auto" -process "Generate Programming File"
|
| 379 |
|
|
project set "Wait for DLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File"
|
| 380 |
|
|
project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
|
| 381 |
|
|
project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
|
| 382 |
|
|
project set "Enable Internal Done Pipe" "false" -process "Generate Programming File"
|
| 383 |
|
|
project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map"
|
| 384 |
|
|
project set "Optimization Strategy (Cover Mode)" "Area" -process "Map"
|
| 385 |
|
|
project set "Maximum Compression" "false" -process "Map"
|
| 386 |
|
|
project set "Generate Detailed MAP Report" "false" -process "Map"
|
| 387 |
|
|
project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
|
| 388 |
|
|
project set "Trim Unconnected Signals" "true" -process "Map"
|
| 389 |
|
|
project set "Create I/O Pads from Ports" "false" -process "Translate"
|
| 390 |
|
|
project set "Macro Search Path" "" -process "Translate"
|
| 391 |
|
|
project set "Netlist Translation Type" "Timestamp" -process "Translate"
|
| 392 |
|
|
project set "User Rules File for Netlister Launcher" "" -process "Translate"
|
| 393 |
|
|
project set "Allow Unexpanded Blocks" "false" -process "Translate"
|
| 394 |
|
|
project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
|
| 395 |
|
|
project set "Use Bonded I/Os" "false" -process "Place & Route"
|
| 396 |
|
|
project set "Add I/O Buffers" "true" -process "Synthesize - XST"
|
| 397 |
|
|
project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
|
| 398 |
|
|
project set "Keep Hierarchy" "No" -process "Synthesize - XST"
|
| 399 |
|
|
project set "Register Balancing" "No" -process "Synthesize - XST"
|
| 400 |
|
|
project set "Register Duplication" "true" -process "Synthesize - XST"
|
| 401 |
|
|
project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
|
| 402 |
|
|
project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
|
| 403 |
|
|
project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
|
| 404 |
|
|
project set "Bus Delimiter" "<>" -process "Synthesize - XST"
|
| 405 |
|
|
project set "Case" "Maintain" -process "Synthesize - XST"
|
| 406 |
|
|
project set "Cores Search Directories" "" -process "Synthesize - XST"
|
| 407 |
|
|
project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
|
| 408 |
|
|
project set "DSP Utilization Ratio" "100" -process "Synthesize - XST"
|
| 409 |
|
|
project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
|
| 410 |
|
|
project set "FSM Style" "LUT" -process "Synthesize - XST"
|
| 411 |
|
|
project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
|
| 412 |
|
|
project set "Generics, Parameters" "" -process "Synthesize - XST"
|
| 413 |
|
|
project set "Hierarchy Separator" "/" -process "Synthesize - XST"
|
| 414 |
|
|
project set "HDL INI File" "" -process "Synthesize - XST"
|
| 415 |
|
|
project set "LUT Combining" "No" -process "Synthesize - XST"
|
| 416 |
|
|
project set "Library Search Order" "" -process "Synthesize - XST"
|
| 417 |
|
|
project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
|
| 418 |
|
|
project set "Optimize Instantiated Primitives" "false" -process "Synthesize - XST"
|
| 419 |
|
|
project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
|
| 420 |
|
|
project set "Power Reduction" "false" -process "Synthesize - XST"
|
| 421 |
|
|
project set "Read Cores" "true" -process "Synthesize - XST"
|
| 422 |
|
|
project set "Slice Packing" "true" -process "Synthesize - XST"
|
| 423 |
|
|
project set "LUT-FF Pairs Utilization Ratio" "100" -process "Synthesize - XST"
|
| 424 |
|
|
project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
|
| 425 |
|
|
project set "Verilog Include Directories" "" -process "Synthesize - XST"
|
| 426 |
|
|
project set "Verilog 2001" "true" -process "Synthesize - XST"
|
| 427 |
|
|
project set "Verilog Macros" "" -process "Synthesize - XST"
|
| 428 |
|
|
project set "Work Directory" "C:/Users/dgb/Desktop/FPGA/System09/rtl/System09_Xilinx_ML506/xst" -process "Synthesize - XST"
|
| 429 |
|
|
project set "Write Timing Constraints" "false" -process "Synthesize - XST"
|
| 430 |
|
|
project set "Other XST Command Line Options" "" -process "Synthesize - XST"
|
| 431 |
|
|
project set "Timing Mode" "Performance Evaluation" -process "Map"
|
| 432 |
|
|
project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
|
| 433 |
|
|
project set "Generate Clock Region Report" "false" -process "Place & Route"
|
| 434 |
|
|
project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route"
|
| 435 |
|
|
project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
|
| 436 |
|
|
project set "Power Reduction" "false" -process "Place & Route"
|
| 437 |
|
|
project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route"
|
| 438 |
|
|
project set "Equivalent Register Removal" "true" -process "Map"
|
| 439 |
|
|
project set "Placer Extra Effort" "None" -process "Map"
|
| 440 |
|
|
project set "Power Activity File" "" -process "Map"
|
| 441 |
|
|
project set "Retiming" "false" -process "Map"
|
| 442 |
|
|
project set "Synthesis Constraints File" "" -process "Synthesize - XST"
|
| 443 |
|
|
project set "Mux Style" "Auto" -process "Synthesize - XST"
|
| 444 |
|
|
project set "RAM Style" "Auto" -process "Synthesize - XST"
|
| 445 |
|
|
project set "Encrypt Bitstream" "false" -process "Generate Programming File"
|
| 446 |
|
|
project set "Output File Name" "system09" -process "Generate IBIS Model"
|
| 447 |
|
|
project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
|
| 448 |
|
|
project set "Cycles for First BPI Page Read" "1" -process "Generate Programming File"
|
| 449 |
|
|
project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
|
| 450 |
|
|
project set "Create Logic Allocation File" "false" -process "Generate Programming File"
|
| 451 |
|
|
project set "Create Mask File" "false" -process "Generate Programming File"
|
| 452 |
|
|
project set "Watchdog Timer Value" "0x000000" -process "Generate Programming File"
|
| 453 |
|
|
project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File"
|
| 454 |
|
|
project set "Enable Multi-Threading" "false" -process "Map"
|
| 455 |
|
|
project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
|
| 456 |
|
|
project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
|
| 457 |
|
|
project set "ROM Style" "Auto" -process "Synthesize - XST"
|
| 458 |
|
|
project set "Safe Implementation" "No" -process "Synthesize - XST"
|
| 459 |
|
|
project set "Power Activity File" "" -process "Place & Route"
|
| 460 |
|
|
project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
|
| 461 |
|
|
project set "AES Initial Vector" "" -process "Generate Programming File"
|
| 462 |
|
|
project set "Key 0 (Hex String)" "" -process "Generate Programming File"
|
| 463 |
|
|
project set "Input Encryption Key File" "" -process "Generate Programming File"
|
| 464 |
|
|
project set "Fallback Reconfiguration" "Enable" -process "Generate Programming File"
|
| 465 |
|
|
|
| 466 |
|
|
puts "$myScript: project property values set."
|
| 467 |
|
|
|
| 468 |
|
|
} ; # end set_process_props
|
| 469 |
|
|
|
| 470 |
|
|
proc main {} {
|
| 471 |
|
|
|
| 472 |
|
|
if { [llength $::argv] == 0 } {
|
| 473 |
|
|
show_help
|
| 474 |
|
|
return true
|
| 475 |
|
|
}
|
| 476 |
|
|
|
| 477 |
|
|
foreach option $::argv {
|
| 478 |
|
|
switch $option {
|
| 479 |
|
|
"show_help" { show_help }
|
| 480 |
|
|
"run_process" { run_process }
|
| 481 |
|
|
"rebuild_project" { rebuild_project }
|
| 482 |
|
|
"set_project_props" { set_project_props }
|
| 483 |
|
|
"add_source_files" { add_source_files }
|
| 484 |
|
|
"create_libraries" { create_libraries }
|
| 485 |
|
|
"create_partitions" { create_partitions }
|
| 486 |
|
|
"set_process_props" { set_process_props }
|
| 487 |
|
|
default { puts "unrecognized option: $option"; show_help }
|
| 488 |
|
|
}
|
| 489 |
|
|
}
|
| 490 |
|
|
}
|
| 491 |
|
|
|
| 492 |
|
|
if { $tcl_interactive } {
|
| 493 |
|
|
show_help
|
| 494 |
|
|
} else {
|
| 495 |
|
|
if {[catch {main} result]} {
|
| 496 |
|
|
puts "$myScript failed: $result."
|
| 497 |
|
|
}
|
| 498 |
|
|
}
|
| 499 |
|
|
|
