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[/] [System09/] [trunk/] [rtl/] [System09_base/] [xsasdramcntl.vhd] - Blame information for rev 76

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1 59 davidgb
--------------------------------------------------------------------
2
-- Company       : XESS Corp.
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-- Engineer      : Dave Vanden Bout
4
-- Creation Date : 05/17/2005
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-- Copyright     : 2005, XESS Corp
6
-- Tool Versions : WebPACK 6.3.03i
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--
8
-- Description:
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--    Customizes the generic SDRAM controller module for the XSA Board.
10
--
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-- Revision:
12
--    1.1.0
13
--
14
-- Additional Comments:
15
--    1.1.0:
16
--        Added CLK_DIV generic parameter to allow stepping-down the clock frequency.
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--        Added MULTIPLE_ACTIVE_ROWS generic parameter to enable/disable keeping an active row in each bank.
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--    1.0.0:
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--        Initial release.
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--
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-- License:
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--    This code can be freely distributed and modified as long as
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--    this header is not removed.
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--------------------------------------------------------------------
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27
 
28
library IEEE, UNISIM;
29
use IEEE.std_logic_1164.all;
30
use IEEE.numeric_std.all;
31
use UNISIM.VComponents.all;
32
use WORK.common.all;
33
use WORK.sdram.all;
34
 
35
 
36
package XSASDRAM is
37
 
38
  component XSASDRAMCntl
39
    generic(
40
      FREQ                 :     natural := 100_000;  -- operating frequency in KHz
41
      CLK_DIV              :     real    := 2.0;  -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
42
      PIPE_EN              :     boolean := false;  -- if true, enable pipelined read operations
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      MAX_NOP              :     natural := 10000;  -- number of NOPs before entering self-refresh
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      MULTIPLE_ACTIVE_ROWS :     boolean := false;  -- if true, allow an active row in each bank
45
      DATA_WIDTH           :     natural := 16;  -- host & SDRAM data width
46
      NROWS                :     natural := 8096;  -- number of rows in SDRAM array
47
      NCOLS                :     natural := 512;  -- number of columns in SDRAM array
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      HADDR_WIDTH          :     natural := 24;  -- host-side address width
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      SADDR_WIDTH          :     natural := 13  -- SDRAM-side address width
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      );
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    port(
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      -- host side
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      clk                  : in  std_logic;  -- master clock
54
      bufclk               : out std_logic;  -- buffered master clock
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      clk1x                : out std_logic;  -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
56
      clk2x                : out std_logic;  -- double-speed host clock
57
      lock                 : out std_logic;  -- true when host clock is locked to master clock
58
      rst                  : in  std_logic;  -- reset
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      rd                   : in  std_logic;  -- initiate read operation
60
      wr                   : in  std_logic;  -- initiate write operation
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      earlyOpBegun         : out std_logic;  -- read/write/self-refresh op begun     (async)
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      opBegun              : out std_logic;  -- read/write/self-refresh op begun (clocked)
63
      rdPending            : out std_logic;  -- read operation(s) are still in the pipeline
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      done                 : out std_logic;  -- read or write operation is done
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      rdDone               : out std_logic;  -- read done and data is available
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      hAddr                : in  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address from host
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      hDIn                 : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from host
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      hDOut                : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to host
69
      status               : out std_logic_vector(3 downto 0);  -- diagnostic status of the FSM         
70
 
71
      -- SDRAM side
72
      sclkfb : in    std_logic;         -- clock from SDRAM after PCB delays
73
      sclk   : out   std_logic;         -- SDRAM clock sync'ed to master clock
74
      cke    : out   std_logic;         -- clock-enable to SDRAM
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      cs_n   : out   std_logic;         -- chip-select to SDRAM
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      ras_n  : out   std_logic;         -- SDRAM row address strobe
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      cas_n  : out   std_logic;         -- SDRAM column address strobe
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      we_n   : out   std_logic;         -- SDRAM write enable
79
      ba     : out   std_logic_vector(1 downto 0);  -- SDRAM bank address bits
80
      sAddr  : out   std_logic_vector(SADDR_WIDTH-1 downto 0);  -- SDRAM row/column address
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      sData  : inout std_logic_vector(DATA_WIDTH-1 downto 0);  -- SDRAM in/out databus
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      dqmh   : out   std_logic;         -- high databits I/O mask
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      dqml   : out   std_logic          -- low databits I/O mask
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      );
85
  end component;
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87
end package XSASDRAM;
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91
library IEEE, UNISIM;
92
use IEEE.std_logic_1164.all;
93
use IEEE.numeric_std.all;
94
use UNISIM.VComponents.all;
95
use WORK.common.all;
96
use WORK.sdram.all;
97
 
98
entity XSASDRAMCntl is
99
  generic(
100
    FREQ                 :     natural := 100_000; -- operating frequency in KHz
101
    CLK_DIV              :     real    := 2.0;     -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
102
    PIPE_EN              :     boolean := false;   -- if true, enable pipelined read operations
103
    MAX_NOP              :     natural := 10000;   -- number of NOPs before entering self-refresh
104
    MULTIPLE_ACTIVE_ROWS :     boolean := false;   -- if true, allow an active row in each bank
105
    DATA_WIDTH           :     natural := 16;      -- host & SDRAM data width
106
    NROWS                :     natural := 8192;    -- number of rows in SDRAM array
107
    NCOLS                :     natural := 512;     -- number of columns in SDRAM array
108
    HADDR_WIDTH          :     natural := 24;      -- host-side address width
109
    SADDR_WIDTH          :     natural := 13       -- SDRAM-side address width
110
    );
111
  port(
112
    -- host side
113
    clk                  : in  std_logic;  -- master clock
114
    bufclk               : out std_logic;  -- buffered master clock
115
    clk1x                : out std_logic;  -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
116
    clk2x                : out std_logic;  -- double-speed host clock
117
    lock                 : out std_logic;  -- true when host clock is locked to master clock
118
    rst                  : in  std_logic;  -- reset
119
    rd                   : in  std_logic;  -- initiate read operation
120
    wr                   : in  std_logic;  -- initiate write operation
121
    earlyOpBegun         : out std_logic;  -- read/write/self-refresh op begun     (async)
122
    opBegun              : out std_logic;  -- read/write/self-refresh op begun (clocked)
123
    rdPending            : out std_logic;  -- read operation(s) are still in the pipeline
124
    done                 : out std_logic;  -- read or write operation is done
125
    rdDone               : out std_logic;  -- read done and data is available
126
    hAddr                : in  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address from host
127
    hDIn                 : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from host
128
    hDOut                : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to host
129
    status               : out std_logic_vector(3 downto 0);  -- diagnostic status of the FSM         
130
 
131
    -- SDRAM side
132
    sclkfb : in    std_logic;           -- clock from SDRAM after PCB delays
133
    sclk   : out   std_logic;           -- SDRAM clock sync'ed to master clock
134
    cke    : out   std_logic;           -- clock-enable to SDRAM
135
    cs_n   : out   std_logic;           -- chip-select to SDRAM
136
    ras_n  : out   std_logic;           -- SDRAM row address strobe
137
    cas_n  : out   std_logic;           -- SDRAM column address strobe
138
    we_n   : out   std_logic;           -- SDRAM write enable
139
    ba     : out   std_logic_vector(1 downto 0);  -- SDRAM bank address bits
140
    sAddr  : out   std_logic_vector(SADDR_WIDTH-1 downto 0);  -- SDRAM row/column address
141
    sData  : inout std_logic_vector(DATA_WIDTH-1 downto 0);  -- SDRAM in/out databus
142
    dqmh   : out   std_logic;           -- high databits I/O mask
143
    dqml   : out   std_logic            -- low databits I/O mask
144
    );
145
end XSASDRAMCntl;
146
 
147
 
148
 
149
architecture arch of XSASDRAMCntl is
150
 
151
  -- The SDRAM controller and external SDRAM chip will clock on the same edge
152
  -- if the frequency and divided frequency are both greater than the minimum DLL lock frequency.
153
  -- Otherwise the DLLs cannot be used so the SDRAM controller and external SDRAM clock on opposite edges
154
  -- to try and mitigate the clock skew between the internal FPGA logic and the external SDRAM.
155
  constant MIN_LOCK_FREQ : real    := 25_000.0;
156
  constant IN_PHASE      : boolean := real(FREQ)/CLK_DIV >= MIN_LOCK_FREQ;
157
  -- Calculate the frequency of the clock for the SDRAM.
158
  constant SDRAM_FREQ    : natural := int_select(IN_PHASE, (FREQ*integer(2.0*CLK_DIV))/2, FREQ);
159
  -- Compute the CLKDV_DIVIDE generic paramter for the DLL modules.  It defaults to 2 when CLK_DIV=1
160
  -- because the DLL does not support a divisor of 1 on the CLKDV output.  We use the CLK0 output
161
  -- when CLK_DIV=1 so we don't care what is output on thr CLK_DIV output of the DLL.
162
  constant CLKDV_DIVIDE  : real    := real_select(CLK_DIV = 1.0, 2.0, CLK_DIV);
163
 
164
  signal int_clkin,                     -- signals for internal logic clock DLL
165
    int_clk1x, int_clk1x_b,
166
    int_clk2x, int_clk2x_b,
167
    int_clkdv, int_clkdv_b              : std_logic;
168
  signal ext_clkin, sclkfb_b, ext_clk1x : std_logic;  -- signals for external logic clock DLL
169
  signal dllext_rst, dllext_rst_n       : std_logic;  -- external DLL reset signal
170
  signal clk_i                          : std_logic;  -- clock for SDRAM controller logic
171
  signal int_lock, ext_lock, lock_i     : std_logic;  -- DLL lock signals
172
 
173
  -- bus for holding output data from SDRAM
174
  signal sDOut   : std_logic_vector(sData'range);
175
  signal sDOutEn : std_logic;
176
 
177
begin
178
 
179
  -----------------------------------------------------------
180
  -- setup the DLLs for clock generation 
181
  -----------------------------------------------------------
182
 
183
  -- master clock must come from a dedicated clock pin
184
  clkin : IBUFG port map (I => clk, O => int_clkin);
185
 
186
  -- The external DLL is driven from the same source as the internal DLL
187
  -- if the clock divisor is 1.  If CLK_DIV is greater than 1, then the external DLL 
188
  -- is driven by the divided clock from the internal DLL.  Otherwise, the SDRAM will be
189
  -- clocked on the opposite edge if the internal and external logic are not in-phase.
190
  ext_clkin <= int_clkin    when (IN_PHASE and (CLK_DIV = 1.0)) else
191
                int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0))  else
192
                not int_clkin;
193
 
194
  -- Generate the DLLs for sync'ing the clocks as long as the clocks
195
  -- have a frequency high enough for the DLLs to lock
196
  gen_dlls : if IN_PHASE generate
197
 
198
    -- generate an internal clock sync'ed to the master clock
199
    dllint : CLKDLL
200
      generic map(
201
        CLKDV_DIVIDE => CLKDV_DIVIDE
202
        )
203
      port map(
204
        CLKIN        => int_clkin,
205
        CLKFB        => int_clk1x_b,
206
        CLK0         => int_clk1x,
207
        RST          => ZERO,
208
        CLK90        => open,
209
        CLK180       => open,
210
        CLK270       => open,
211
        CLK2X        => int_clk2x,
212
        CLKDV        => int_clkdv,
213
        LOCKED       => int_lock
214
        );
215
 
216
    -- sync'ed single, doubled and divided clocks for use by internal logic
217
    int_clk1x_buf : BUFG port map(I => int_clk1x, O => int_clk1x_b);
218
    int_clk2x_buf : BUFG port map(I => int_clk2x, O => int_clk2x_b);
219
    int_clkdv_buf : BUFG port map(I => int_clkdv, O => int_clkdv_b);
220
 
221
    -- The external DLL is held in a reset state until the internal DLL locks.
222
    -- Then the external DLL reset is released after a delay set by this shift register.
223
    -- This keeps the external DLL from locking onto the internal DLL clock signal
224
    -- until it is stable.
225
    SRL16_inst : SRL16
226
      generic map (
227
        INIT => X"0000"
228
        )
229
      port map (
230
        CLK  => clk_i,
231
        A0   => '1',
232
        A1   => '1',
233
        A2   => '1',
234
        A3   => '1',
235
        D    => int_lock,
236
        Q    => dllext_rst_n
237
        );
238
    dllext_rst <= not dllext_rst when CLK_DIV/=1.0 else ZERO;
239
 
240
    -- generate an external SDRAM clock sync'ed to the master clock
241
    sclkfb_buf : IBUFG port map(I => sclkfb, O => sclkfb_b);  -- SDRAM clock with PCB delays
242
--    sclkfb_buf : BUFGMUX port map(I => sclkfb, O => sclkfb_b);  -- SDRAM clock with PCB delays
243
    dllext     : CLKDLL port map(
244
      CLKIN                       => ext_clkin,  -- this is either the master clock or the divided clock from the internal DLL
245
      CLKFB                       => sclkfb_b,
246
      CLK0                        => ext_clk1x,
247
      RST                         => dllext_rst,
248
      CLK90                       => open,
249
      CLK180                      => open,
250
      CLK270                      => open,
251
      CLK2X                       => open,
252
      CLKDV                       => open,
253
      LOCKED                      => ext_lock
254
      );
255
 
256
  end generate;
257
 
258
  -- The buffered clock is just a buffered version of the master clock.
259
  bufclk <= int_clkin;
260
  -- The host-side clock comes from the CLK0 output of the internal DLL if the clock divisor is 1.
261
  -- Otherwise it comes from the CLKDV output if the clock divisor is greater than 1.
262
  -- Otherwise it is just a copy of the master clock if the DLLs aren't being used.
263
  clk_i  <= int_clk1x_b when (IN_PHASE and (CLK_DIV = 1.0)) else
264
            int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0))  else
265
            int_clkin;
266
  clk1x  <= clk_i;                      -- This is the output of the host-side clock
267
  clk2x  <= int_clk2x_b when IN_PHASE                       else int_clkin;  -- this is the doubled master clock
268
  sclk   <= ext_clk1x   when IN_PHASE                       else ext_clkin;  -- this is the clock for the external SDRAM
269
 
270
  -- indicate the lock status of the internal and external DLL
271
  lock_i <= int_lock and ext_lock when IN_PHASE else YES;
272
  lock   <= lock_i;                     -- lock signal for the host logic
273
 
274
  -- SDRAM memory controller module
275
  u1 : sdramCntl
276
    generic map(
277
      FREQ                 => SDRAM_FREQ,
278
      IN_PHASE             => IN_PHASE,
279
      PIPE_EN              => PIPE_EN,
280
      MAX_NOP              => MAX_NOP,
281
      MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
282
      DATA_WIDTH           => DATA_WIDTH,
283
      NROWS                => NROWS,
284
      NCOLS                => NCOLS,
285
      HADDR_WIDTH          => HADDR_WIDTH,
286
      SADDR_WIDTH          => SADDR_WIDTH
287
      )
288
    port map(
289
      clk                  => clk_i,    -- master clock from external clock source (unbuffered)
290
      lock                 => lock_i,   -- valid synchronized clocks indicator
291
      rst                  => rst,      -- reset
292
      rd                   => rd,       -- host-side SDRAM read control from memory tester
293
      wr                   => wr,       -- host-side SDRAM write control from memory tester
294
      rdPending            => rdPending,
295
      opBegun              => opBegun,  -- SDRAM memory read/write done indicator
296
      earlyOpBegun         => earlyOpBegun,  -- SDRAM memory read/write done indicator
297
      rdDone               => rdDone,   -- SDRAM memory read/write done indicator
298
      done                 => done,
299
      hAddr                => hAddr,    -- host-side address from memory tester
300
      hDIn                 => hDIn,     -- test data pattern from memory tester
301
      hDOut                => hDOut,    -- SDRAM data output to memory tester
302
      status               => status,   -- SDRAM controller state (for diagnostics)
303
      cke                  => cke,      -- SDRAM clock enable
304
      ce_n                 => cs_n,     -- SDRAM chip-select
305
      ras_n                => ras_n,    -- SDRAM RAS
306
      cas_n                => cas_n,    -- SDRAM CAS
307
      we_n                 => we_n,     -- SDRAM write-enable
308
      ba                   => ba,       -- SDRAM bank address
309
      sAddr                => sAddr,    -- SDRAM address
310
      sDIn                 => sData,    -- input data from SDRAM
311
      sDOut                => sDOut,    -- output data to SDRAM
312
      sDOutEn              => sDOutEn,  -- enable drivers to send data to SDRAM
313
      dqmh                 => dqmh,     -- SDRAM DQMH
314
      dqml                 => dqml      -- SDRAM DQML
315
      );
316
 
317
  sData <= sDOut when sDOutEn = YES else (others => 'Z');
318
 
319
end arch;

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