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--===========================================================================--
--
-- ACIA 6850 Test Bench
--
--
-- John Kent 6th February 2007
--
--
-------------------------------------------------------------------------------
library ieee;
   use ieee.std_logic_1164.all;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
   use ieee.numeric_std.all;
 
entity ACIA_6850_testbench is
end ACIA_6850_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for ACIA 6850 Unit
-------------------------------------------------------------------------------
architecture behavior of ACIA_6850_testbench is
  -----------------------------------------------------------------------------
  -- Signals
  -----------------------------------------------------------------------------
  -- CPU Interface signals
  signal SysClk       : Std_Logic;
  signal uart_reset   : Std_Logic;
  signal uart_cs      : Std_Logic;
  signal uart_rw      : Std_Logic;
  signal uart_addr    : Std_Logic;
  signal uart_data_in : Std_Logic_Vector(7 downto 0);
  signal uart_data_out: Std_Logic_Vector(7 downto 0);
  signal uart_irq     : Std_Logic;
  signal rxclk        : Std_Logic;
  signal txclk        : Std_Logic;
  signal rxbit        : Std_Logic;
  signal txbit        : Std_Logic;
  signal dcd_n        : Std_Logic;
  signal cts_n        : Std_Logic;
  signal rts_n        : Std_Logic;
 
-----------------------------------------------------------------
--
-- ACIA 6850 UART
--
-----------------------------------------------------------------
component ACIA_6850
  port (
     --
          -- CPU signals
          --
     clk      : in  Std_Logic;  -- System Clock
     rst      : in  Std_Logic;  -- Reset input (active high)
     cs       : in  Std_Logic;  -- miniUART Chip Select
     rw       : in  Std_Logic;  -- Read / Not Write
     irq      : out Std_Logic;  -- Interrupt
     Addr     : in  Std_Logic;  -- Register Select
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
     DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
     --
          -- Uart Signals
          --
     RxC      : in  Std_Logic;  -- Receive Baud Clock
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
     RxD      : in  Std_Logic;  -- Receive Data
     TxD      : out Std_Logic;  -- Transmit Data
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
     CTS_n    : in  Std_Logic;  -- Clear To Send
     RTS_n    : out Std_Logic );  -- Request To send
end component; --================== End of entity ==============================--
 
begin
 
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
 
my_acia  : ACIA_6850 port map (
    clk       => SysClk,
         rst       => uart_reset,
    cs        => uart_cs,
         rw        => uart_rw,
    Irq       => uart_irq,
    Addr      => uart_addr,
         Datain    => uart_data_in,
         DataOut   => uart_data_out,
         RxC       => rxclk,
         TxC       => txclk,
         RxD       => rxbit,
         TxD       => txbit,
         DCD_n     => dcd_n,
         CTS_n     => cts_n,
         RTS_n     => rts_n
         );
 
 
  -- *** Test Bench - User Defined Section ***
   tb : PROCESS
        variable count : integer;
   BEGIN
 
   cts_n <= '0';
        dcd_n <= '0';
 
                for count in 0 to 4096 loop
                   if (count mod 16) = 0 then
                     rxclk <= '1';
                          txclk <= '1';
                   elsif (count mod 16) = 8 then
                     rxclk <= '0';
                          txclk <= '0';
         end if;
 
                        case count is
                        when 0 =>
                                uart_reset <= '1';
                      uart_cs <= '0';
                                uart_rw <= '1';
                                uart_addr <= '0';
                                uart_data_in <= "00000000";
                                rxbit <= '1';
                        when 1 =>
                                uart_reset <= '0';
                        when 3 =>
                      uart_cs <= '1';
                                uart_rw <= '0'; -- write control
                                uart_addr <= '0';
                                uart_data_in <= "00010001";
                        when 4 =>
                      uart_cs <= '0';
                                uart_rw <= '1';
                                uart_addr <= '0';
                                uart_data_in <= "00000000";
                        when 5 =>
                      uart_cs <= '1';
                                uart_rw <= '0'; -- write data
                                uart_addr <= '1';
                                uart_data_in <= "01010101";
                        when 6 =>
                      uart_cs <= '0';
                                uart_rw <= '1';
                                uart_addr <= '1';
                                uart_data_in <= "00000000";
                        when 256 =>
            rxbit <= '0'; -- start
                        when 512 =>
                           rxbit <= '1'; -- bit 0
                        when 768 =>
            rxbit <= '0'; -- bit 1
                        when 1024 =>
                           rxbit <= '1'; -- bit 2
                        when 1280 =>
            rxbit <= '1'; -- bit3
                        when 1536 =>
                           rxbit <= '0'; -- bit 4
                        when 1792 =>
            rxbit <= '0'; -- bit 5
                        when 2048 =>
                           rxbit <= '1'; -- bit 6
                        when 2304 =>
            rxbit <= '0'; -- bit 7
                        when 2560 =>
                           rxbit <= '1'; -- stop 1
                        when 2816 =>
                           rxbit <= '1'; -- stop 2
                        when 3100 =>
                      uart_cs <= '1';
                                uart_rw <= '1'; -- read control
                                uart_addr <= '0';
                        when 3101 =>
                      uart_cs <= '0';
                                uart_rw <= '1';
                                uart_addr <= '0';
                        when 3102 =>
                      uart_cs <= '1';
                                uart_rw <= '1'; -- read data
                                uart_addr <= '1';
                        when 3103 =>
                      uart_cs <= '0';
                                uart_rw <= '1';
                                uart_addr <= '1';
                        when others =>
                           null;
                        end case;
                        SysClk <= '1';
                        wait for 40 ns;
                        SysClk <= '0';
                        wait for 40 ns;
                end loop;
 
      wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
end behavior; --===================== End of architecture =======================--
 

Line No.	Rev	Author	Line
1	19	dilbert57	`--===========================================================================--`
2			`--`
3			`-- ACIA 6850 Test Bench`
4			`--`
5			`--`
6			`-- John Kent 6th February 2007`
7			`--`
8			`--`
9			`-------------------------------------------------------------------------------`
10			`library ieee;`
11			`use ieee.std_logic_1164.all;`
12			`use IEEE.STD_LOGIC_ARITH.ALL;`
13			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
14			`use ieee.numeric_std.all;`
15
16			`entity ACIA_6850_testbench is`
17			`end ACIA_6850_testbench;`
18
19			`-------------------------------------------------------------------------------`
20			`-- Architecture for ACIA 6850 Unit`
21			`-------------------------------------------------------------------------------`
22			`architecture behavior of ACIA_6850_testbench is`
23			`-----------------------------------------------------------------------------`
24			`-- Signals`
25			`-----------------------------------------------------------------------------`
26			`-- CPU Interface signals`
27			`signal SysClk : Std_Logic;`
28			`signal uart_reset : Std_Logic;`
29			`signal uart_cs : Std_Logic;`
30			`signal uart_rw : Std_Logic;`
31			`signal uart_addr : Std_Logic;`
32			`signal uart_data_in : Std_Logic_Vector(7 downto 0);`
33			`signal uart_data_out: Std_Logic_Vector(7 downto 0);`
34			`signal uart_irq : Std_Logic;`
35			`signal rxclk : Std_Logic;`
36			`signal txclk : Std_Logic;`
37			`signal rxbit : Std_Logic;`
38			`signal txbit : Std_Logic;`
39			`signal dcd_n : Std_Logic;`
40			`signal cts_n : Std_Logic;`
41			`signal rts_n : Std_Logic;`
42
43			`-----------------------------------------------------------------`
44			`--`
45			`-- ACIA 6850 UART`
46			`--`
47			`-----------------------------------------------------------------`
48			`component ACIA_6850`
49			`port (`
50			`--`
51			`-- CPU signals`
52			`--`
53			`clk : in Std_Logic; -- System Clock`
54			`rst : in Std_Logic; -- Reset input (active high)`
55			`cs : in Std_Logic; -- miniUART Chip Select`
56			`rw : in Std_Logic; -- Read / Not Write`
57			`irq : out Std_Logic; -- Interrupt`
58			`Addr : in Std_Logic; -- Register Select`
59			`DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In`
60			`DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out`
61			`--`
62			`-- Uart Signals`
63			`--`
64			`RxC : in Std_Logic; -- Receive Baud Clock`
65			`TxC : in Std_Logic; -- Transmit Baud Clock`
66			`RxD : in Std_Logic; -- Receive Data`
67			`TxD : out Std_Logic; -- Transmit Data`
68			`DCD_n : in Std_Logic; -- Data Carrier Detect`
69			`CTS_n : in Std_Logic; -- Clear To Send`
70			`RTS_n : out Std_Logic ); -- Request To send`
71			`end component; --================== End of entity ==============================--`
72
73			`begin`
74
75			`-----------------------------------------------------------------------------`
76			`-- Instantiation of internal components`
77			`-----------------------------------------------------------------------------`
78
79			`my_acia : ACIA_6850 port map (`
80			`clk => SysClk,`
81			`rst => uart_reset,`
82			`cs => uart_cs,`
83			`rw => uart_rw,`
84			`Irq => uart_irq,`
85			`Addr => uart_addr,`
86			`Datain => uart_data_in,`
87			`DataOut => uart_data_out,`
88			`RxC => rxclk,`
89			`TxC => txclk,`
90			`RxD => rxbit,`
91			`TxD => txbit,`
92			`DCD_n => dcd_n,`
93			`CTS_n => cts_n,`
94			`RTS_n => rts_n`
95			`);`
96
97
98			`-- * Test Bench - User Defined Section *`
99			`tb : PROCESS`
100			`variable count : integer;`
101			`BEGIN`
102
103			`cts_n <= '0';`
104			`dcd_n <= '0';`
105
106			`for count in 0 to 4096 loop`
107			`if (count mod 16) = 0 then`
108			`rxclk <= '1';`
109			`txclk <= '1';`
110			`elsif (count mod 16) = 8 then`
111			`rxclk <= '0';`
112			`txclk <= '0';`
113			`end if;`
114
115			`case count is`
116			`when 0 =>`
117			`uart_reset <= '1';`
118			`uart_cs <= '0';`
119			`uart_rw <= '1';`
120			`uart_addr <= '0';`
121			`uart_data_in <= "00000000";`
122			`rxbit <= '1';`
123			`when 1 =>`
124			`uart_reset <= '0';`
125			`when 3 =>`
126			`uart_cs <= '1';`
127			`uart_rw <= '0'; -- write control`
128			`uart_addr <= '0';`
129			`uart_data_in <= "00010001";`
130			`when 4 =>`
131			`uart_cs <= '0';`
132			`uart_rw <= '1';`
133			`uart_addr <= '0';`
134			`uart_data_in <= "00000000";`
135			`when 5 =>`
136			`uart_cs <= '1';`
137			`uart_rw <= '0'; -- write data`
138			`uart_addr <= '1';`
139			`uart_data_in <= "01010101";`
140			`when 6 =>`
141			`uart_cs <= '0';`
142			`uart_rw <= '1';`
143			`uart_addr <= '1';`
144			`uart_data_in <= "00000000";`
145			`when 256 =>`
146			`rxbit <= '0'; -- start`
147			`when 512 =>`
148			`rxbit <= '1'; -- bit 0`
149			`when 768 =>`
150			`rxbit <= '0'; -- bit 1`
151			`when 1024 =>`
152			`rxbit <= '1'; -- bit 2`
153			`when 1280 =>`
154			`rxbit <= '1'; -- bit3`
155			`when 1536 =>`
156			`rxbit <= '0'; -- bit 4`
157			`when 1792 =>`
158			`rxbit <= '0'; -- bit 5`
159			`when 2048 =>`
160			`rxbit <= '1'; -- bit 6`
161			`when 2304 =>`
162			`rxbit <= '0'; -- bit 7`
163			`when 2560 =>`
164			`rxbit <= '1'; -- stop 1`
165			`when 2816 =>`
166			`rxbit <= '1'; -- stop 2`
167			`when 3100 =>`
168			`uart_cs <= '1';`
169			`uart_rw <= '1'; -- read control`
170			`uart_addr <= '0';`
171			`when 3101 =>`
172			`uart_cs <= '0';`
173			`uart_rw <= '1';`
174			`uart_addr <= '0';`
175			`when 3102 =>`
176			`uart_cs <= '1';`
177			`uart_rw <= '1'; -- read data`
178			`uart_addr <= '1';`
179			`when 3103 =>`
180			`uart_cs <= '0';`
181			`uart_rw <= '1';`
182			`uart_addr <= '1';`
183			`when others =>`
184			`null;`
185			`end case;`
186			`SysClk <= '1';`
187			`wait for 40 ns;`
188			`SysClk <= '0';`
189			`wait for 40 ns;`
190			`end loop;`
191
192			`wait; -- will wait forever`
193			`END PROCESS;`
194			`-- * End Test Bench - User Defined Section *`
195
196			`end behavior; --===================== End of architecture =======================--`
197

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[/] [System09/] [trunk/] [rtl/] [Testbench/] [ACIA_tb.vhd] - Blame information for rev 19