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1 19 dilbert57
--===========================================================================--
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--                                                                           --
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--                        VHDL 6850 ACIA TestBench                           --
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--                                                                           --
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--===========================================================================--
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--
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--
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-- File name      : ACIA_tb.vhd
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--
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-- Entity name    : ACIA6850_testbench
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--
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-- Purpose        : VHDL testbench for acia6850
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--
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-- Dependencies   : ieee.std_logic_1164
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--                  ieee.std_logic_unsigned
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--                  ieee.std_logic_arith
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--                  ieee.numeric_std
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--
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-- Author         : John E. Kent
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--
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-- Email          : dilbert57@opencores.org      
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--
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-- Web            : http://opencores.org/project,system09
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--
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--  Copyright (C) 2007 - 2011 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                                Revision History                           --
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--                                                                           --
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--===========================================================================--
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--
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-- Rev  Date        Author     Notes 
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-- 0.1  2007-02-06  John Kent  Initial Version
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-- 0.2  2011-10-09  John Kent  Renamed acia_6850 to acia6850
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--
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-------------------------------------------------------------------------------
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library ieee;
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   use ieee.std_logic_1164.all;
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   use IEEE.STD_LOGIC_ARITH.ALL;
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   use IEEE.STD_LOGIC_UNSIGNED.ALL;
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   use ieee.numeric_std.all;
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entity ACIA6850_testbench is
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end ACIA6850_testbench;
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-------------------------------------------------------------------------------
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-- Architecture for ACIA 6850 Unit
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-------------------------------------------------------------------------------
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architecture behavior of ACIA6850_testbench is
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  -----------------------------------------------------------------------------
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  -- Signals
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  -----------------------------------------------------------------------------
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  -- CPU Interface signals
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  signal SysClk       : Std_Logic;
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  signal uart_reset   : Std_Logic;
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  signal uart_cs      : Std_Logic;
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  signal uart_rw      : Std_Logic;
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  signal uart_addr    : Std_Logic;
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  signal uart_data_in : Std_Logic_Vector(7 downto 0);
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  signal uart_data_out: Std_Logic_Vector(7 downto 0);
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  signal uart_irq     : Std_Logic;
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  signal rxclk        : Std_Logic;
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  signal txclk        : Std_Logic;
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  signal rxbit        : Std_Logic;
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  signal txbit        : Std_Logic;
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  signal dcd_n        : Std_Logic;
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  signal cts_n        : Std_Logic;
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  signal rts_n        : Std_Logic;
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-----------------------------------------------------------------
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--
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-- ACIA 6850 UART
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--
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-----------------------------------------------------------------
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component ACIA6850
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  port (
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     --
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          -- CPU signals
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          --
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     clk      : in  std_logic;  -- System Clock
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     rst      : in  std_logic;  -- Reset input (active high)
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     cs       : in  std_logic;  -- miniUART Chip Select
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     rw       : in  std_logic;  -- Read / Not Write
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     addr     : in  std_logic;  -- Register Select
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     data_in  : in  std_logic_vector(7 downto 0); -- Data Bus In 
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     data_out : out std_logic_vector(7 downto 0); -- Data Bus Out
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     irq      : out std_logic;  -- Interrupt
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     --
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          -- Uart Signals
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          --
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     RxC      : in  std_logic;  -- Receive Baud Clock
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     TxC      : in  std_logic;  -- Transmit Baud Clock
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     RxD      : in  std_logic;  -- Receive Data
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     TxD      : out std_logic;  -- Transmit Data
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          DCD_n    : in  std_logic;  -- Data Carrier Detect
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     CTS_n    : in  std_logic;  -- Clear To Send
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     RTS_n    : out std_logic );  -- Request To send
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end component; --================== End of entity ==============================--
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begin
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  -----------------------------------------------------------------------------
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  -- Instantiation of internal components
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  -----------------------------------------------------------------------------
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my_acia  : ACIA6850 port map (
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    clk       => SysClk,
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         rst       => uart_reset,
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    cs        => uart_cs,
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         rw        => uart_rw,
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    addr      => uart_addr,
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         data_in   => uart_data_in,
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         data_out  => uart_data_out,
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    irq       => uart_irq,
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         RxC       => rxclk,
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         TxC       => txclk,
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         RxD       => rxbit,
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         TxD       => txbit,
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         DCD_n     => dcd_n,
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         CTS_n     => cts_n,
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         RTS_n     => rts_n
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         );
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  -- *** Test Bench - User Defined Section ***
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   tb : PROCESS
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        variable count : integer;
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   BEGIN
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   cts_n <= '0';
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        dcd_n <= '0';
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                for count in 0 to 4096 loop
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                   if (count mod 16) = 0 then
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                     rxclk <= '1';
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                          txclk <= '1';
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                   elsif (count mod 16) = 8 then
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                     rxclk <= '0';
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                          txclk <= '0';
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         end if;
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                        case count is
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                        when 0 =>
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                                uart_reset <= '1';
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                      uart_cs <= '0';
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                                uart_rw <= '1';
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                                uart_addr <= '0';
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                                uart_data_in <= "00000000";
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                                rxbit <= '1';
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                        when 1 =>
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                                uart_reset <= '0';
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                        when 3 =>
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                      uart_cs <= '1';
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                                uart_rw <= '0'; -- write control
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                                uart_addr <= '0';
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                                uart_data_in <= "00010001";
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                        when 4 =>
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                      uart_cs <= '0';
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                                uart_rw <= '1';
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                                uart_addr <= '0';
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                                uart_data_in <= "00000000";
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                        when 5 =>
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                      uart_cs <= '1';
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                                uart_rw <= '0'; -- write data
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                                uart_addr <= '1';
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                                uart_data_in <= "01010101";
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                        when 6 =>
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                      uart_cs <= '0';
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                                uart_rw <= '1';
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                                uart_addr <= '1';
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                                uart_data_in <= "00000000";
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                        when 256 =>
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            rxbit <= '0'; -- start
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                        when 512 =>
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                           rxbit <= '1'; -- bit 0
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                        when 768 =>
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            rxbit <= '0'; -- bit 1
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                        when 1024 =>
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                           rxbit <= '1'; -- bit 2
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                        when 1280 =>
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            rxbit <= '1'; -- bit3
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                        when 1536 =>
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                           rxbit <= '0'; -- bit 4
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                        when 1792 =>
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            rxbit <= '0'; -- bit 5
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                        when 2048 =>
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                           rxbit <= '1'; -- bit 6
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                        when 2304 =>
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            rxbit <= '0'; -- bit 7
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                        when 2560 =>
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                           rxbit <= '1'; -- stop 1
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                        when 2816 =>
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                           rxbit <= '1'; -- stop 2
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                        when 3100 =>
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                      uart_cs <= '1';
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                                uart_rw <= '1'; -- read control
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                                uart_addr <= '0';
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                        when 3101 =>
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                      uart_cs <= '0';
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                                uart_rw <= '1';
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                                uart_addr <= '0';
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                        when 3102 =>
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                      uart_cs <= '1';
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                                uart_rw <= '1'; -- read data
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                                uart_addr <= '1';
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                        when 3103 =>
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                      uart_cs <= '0';
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                                uart_rw <= '1';
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                                uart_addr <= '1';
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                        when others =>
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                           null;
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                        end case;
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                        SysClk <= '1';
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                        wait for 40 ns;
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                        SysClk <= '0';
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                        wait for 40 ns;
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                end loop;
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      wait; -- will wait forever
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   END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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end behavior; --===================== End of architecture =======================--
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