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[/] [System09/] [trunk/] [rtl/] [Testbench/] [testbench1.vhd] - Blame information for rev 122

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1 122 dilbert57
--===========================================================================--
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--                                                                           --
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--             TESTBENCH    testbench1 - CPU09 Testbench.                    --
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--                                                                           --
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--===========================================================================--
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--
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-- File name      : Testbench1.vhd
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--
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-- Purpose        : cpu09 Microprocessor Test Bench 1
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--                  Contains ROM to print out "Hello World"
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--                  on a none existant Uart
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_unsigned
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--                  ieee.std_logic_arith
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--                  ieee.numeric_std
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--
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-- Uses           : cpu09    (cpu09.vhd)      CPU core
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--                   
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-- Author         : John E. Kent
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--                  dilbert57@opencores.org      
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-- 
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--  Copyright (C) 2003 - 2010 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                                Revision History                           --
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--                                                                           --
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--===========================================================================--
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--
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-- Rev  Date       Author     Changes
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-- 0.1  2003-04-12 John Kent  First version
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-- 1.0  2003-09-06 John Kent  Initial release to Opencores.org
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-- 1.1  2004-01-25 John Kent  removed "test_alu" and "test_cc" from CPU component
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-- 1.2  2011-10-09 John Kent  updated for acia6850
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--
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--===========================================================================--
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library ieee;
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   use ieee.std_logic_1164.all;
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   use IEEE.STD_LOGIC_ARITH.ALL;
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   use IEEE.STD_LOGIC_UNSIGNED.ALL;
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   use ieee.numeric_std.all;
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--library work;
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--   use work.UART_Def.all;
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--   use work.typedefines.all;
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--   use work.memory.all;
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entity my_testbench1 is
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end my_testbench1;
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-------------------------------------------------------------------------------
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-- Architecture for memio Controller Unit
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-------------------------------------------------------------------------------
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architecture behavior of my_testbench1 is
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  -----------------------------------------------------------------------------
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  -- Signals
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  -----------------------------------------------------------------------------
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  -- CPU Interface signals
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  signal SysClk      : Std_Logic;
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  signal cpu_reset   : Std_Logic;
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  signal cpu_rw      : Std_Logic;
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  signal cpu_vma     : Std_Logic;
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  signal cpu_addr    : Std_Logic_Vector(15 downto 0);
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  signal cpu_data_in : Std_Logic_Vector(7 downto 0);
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  signal cpu_data_out: Std_Logic_Vector(7 downto 0);
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  signal cpu_irq     : Std_Logic;
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  signal cpu_nmi     : std_logic;
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  signal cpu_firq    : Std_Logic;
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  constant width   : integer := 8;
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  constant memsize : integer := 64;
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  type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
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  constant rom_data : rom_array :=
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  (
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    "10001110", "11111000", "00101000", -- F800 - 8E F828  RESET LDX #MSG
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         "10000110", "00010001",             -- F803 - 86 11          LDA #$11
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         "10110111", "11100000", "00000100", -- F805 - B7 E004        STA UARTCR
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    "10110110", "11100000", "00000100", -- F808 - B6 E004  POLL1 LDA UARTCR
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         "10000101", "00000010",             -- F80B - 85 02          BITA #TXBE
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         "00100110", "11111001",             -- F80D - 26 F9          BNE POLL1
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         "10100110", "10000000",             -- F80F - A6 80          LDA ,X+
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         "00100111", "00000110",             -- F811 - 27 06          BEQ POLL2
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         "00010010",                         -- F813 - 12             NOP
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         "10110111", "11100000", "00000101", -- F814 - B7 E005        STA UARTDR
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    "00100110", "11101111",             -- F817 - 26 EF          BNE POLL1
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         "10110110", "11100000", "00000100", -- F819 - B6 E004  POLL2 LDA UARTCR
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         "10000101", "00000001",             -- F81C - 85 01          BITA #RXBF
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         "00100111", "11111001",             -- F81E - 27 F9          BEQ POLL2
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         "10110110", "11100000", "00000101", -- F820 - B6 E005        LDA UARTDR
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         "01111110", "11111000", "00000000", -- F823 - 7E F800        JMP RESET
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         "00000000", "00000000",             -- F826 - 00 00          fcb $00,$00
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    "01001000", "01100101", "01101100", -- F828 - 48 65 6c MSG   FCC "Hel"
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         "01101100", "01101111", "00100000", -- F82B - 6c 6f 20       FCC "lo "
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         "01010111", "01101111", "01110010", -- F82E - 57 6f 72       FCC "Wor"
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    "01101100", "01100100",             -- F831 - 6c 64          FCC "ld"
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    "00001010", "00001101", "00000000", -- F833 - 0a 0d 00       FCB LF,CR,NULL
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    "00000000", "00000000",             -- F836 - 00 00          fcb null,null           
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         "11111000", "00000000",             -- F838 - F8 00          fdb $F800 ; Timer irq
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         "11111000", "00000000",             -- F83A - F8 00          fdb $F800 ; Ext IRQ
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         "11111000", "00000000",             -- F83C - F8 00          fcb $F800 ; SWI
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         "11111000", "00000000"              -- F83E - F8 00          fdb $F800 ; Reset
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         );
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component cpu09
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  port (
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         clk:        in std_logic;
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    rst:             in std_logic;
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    vma:             out        std_logic;
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    rw:       out       std_logic;              -- Asynchronous memory interface
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    addr:     out       std_logic_vector(15 downto 0);
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    data_in:  in        std_logic_vector(7 downto 0);
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         data_out: out std_logic_vector(7 downto 0);
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         halt:     in  std_logic;
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         hold:     in  std_logic;
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         irq:      in  std_logic;
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         nmi:      in  std_logic;
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         firq:     in  std_logic
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  );
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end component cpu09;
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begin
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cpu : cpu09  port map (
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         clk          => SysClk,
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    rst       => cpu_reset,
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    vma       => cpu_vma,
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    rw         => cpu_rw,
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    addr      => cpu_addr(15 downto 0),
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    data_in   => cpu_data_in,
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         data_out  => cpu_data_out,
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         halt      => '0',
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         hold      => '0',
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         irq       => cpu_irq,
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         nmi       => cpu_nmi,
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         firq      => cpu_firq
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  );
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  -- *** Test Bench - User Defined Section ***
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   tb : PROCESS
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        variable count : integer;
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   BEGIN
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        cpu_reset <= '0';
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        SysClk <= '0';
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   cpu_irq <= '0';
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   cpu_nmi <= '0';
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        cpu_firq <= '0';
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                for count in 0 to 512 loop
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                        SysClk <= '0';
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                        if count = 0 then
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                                cpu_reset <= '1';
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                        elsif count = 1 then
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                                cpu_reset <= '0';
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                        end if;
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                        wait for 100 ns;
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                        SysClk <= '1';
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                        wait for 100 ns;
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                end loop;
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      wait; -- will wait forever
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   END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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  rom : PROCESS( cpu_addr )
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  begin
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    cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
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  end process;
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end behavior; --===================== End of architecture =======================--
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