OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Testbench/] [testbench2.vhd] - Blame information for rev 142

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 122 dilbert57 
--===========================================================================--
2 
--                                                                           --
3 
--             TESTBENCH    testbench2 - CPU09 Testbench.                    --
4 
--                                                                           --
5 
--===========================================================================--
6 19 dilbert57 
--
7 
-- File name      : Testbench2.vhd
8 
--
9 
-- Purpose        : cpu09 Microprocessor Test Bench 2
10 
--                  Contains ROM to read sector from
11 
--                  a none existant Compact Flash module
12 
--
13 
-- Dependencies   : ieee.Std_Logic_1164
14 
--                  ieee.std_logic_unsigned
15 
--                  ieee.std_logic_arith
16 
--                  ieee.numeric_std
17 
--
18 
-- Uses           : cpu09    (cpu09.vhd)      CPU core
19 
--
20 
-- Author         : John E. Kent
21 
--                  dilbert57@opencores.org
22 122 dilbert57 
--
23 
--  Copyright (C) 2003 - 2010 John Kent
24 
--
25 
--  This program is free software: you can redistribute it and/or modify
26 
--  it under the terms of the GNU General Public License as published by
27 
--  the Free Software Foundation, either version 3 of the License, or
28 
--  (at your option) any later version.
29 
--
30 
--  This program is distributed in the hope that it will be useful,
31 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
32 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
33 
--  GNU General Public License for more details.
34 
--
35 
--  You should have received a copy of the GNU General Public License
36 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
37 
--
38 
--===========================================================================--
39 
--                                                                           --
40 
--                                Revision History                           --
41 
--                                                                           --
42 
--===========================================================================--
43 19 dilbert57 
--
44 122 dilbert57 
-- Rev  Date       Author     Changes
45 
-- 0.1  2003-04-12 John Kent  First version
46 
-- 1.0  2003-09-06 John Kent  Initial release to Opencores.org
47 
-- 1.1  2004-01-25 John Kent  removed "test_alu" and "test_cc" from CPU component
48 
-- 1.2  2011-10-09 John Kent  renamed address to addr on CPU component, updated header
49 19 dilbert57 
--
50 
--===========================================================================--
51 
 
52 
library ieee;
53 
   use ieee.std_logic_1164.all;
54 
   use IEEE.STD_LOGIC_ARITH.ALL;
55 
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
56 
   use ieee.numeric_std.all;
57 
 
58 
entity my_testbench2 is
59 
end my_testbench2;
60 
 
61 
-------------------------------------------------------------------------------
62 
-- Architecture for memio Controller Unit
63 
-------------------------------------------------------------------------------
64 
architecture behavior of my_testbench2 is
65 
  -----------------------------------------------------------------------------
66 
  -- Signals
67 
  -----------------------------------------------------------------------------
68 
 
69 
  -- CPU Interface signals
70 
  signal SysClk      : Std_Logic;
71 
  signal cpu_reset   : Std_Logic;
72 
  signal cpu_rw      : Std_Logic;
73 
  signal cpu_vma     : Std_Logic;
74 
  signal cpu_addr    : Std_Logic_Vector(15 downto 0);
75 
  signal cpu_data_in : Std_Logic_Vector(7 downto 0);
76 
  signal cpu_data_out: Std_Logic_Vector(7 downto 0);
77 
  signal cpu_irq     : Std_Logic;
78 
  signal cpu_nmi     : Std_Logic;
79 
  signal cpu_firq    : std_logic;
80 
 
81 
  constant width   : integer := 8;
82 
  constant memsize : integer := 128;
83 
 
84 
  type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
85 
 
86 
  constant rom_data : rom_array :=
87 
  (
88 
"00010000", -- $F800 LDS #$F878 (Point to dummy return to test stack)
89 
"11001110",
90 
"11111000",
91 
"01111000",
92 
"10000110", -- $F804 LDA #$E0 *** START
93 
"11100000",
94 
"00011111", -- $F806 TFR A,DPR
95 
"10001011",
96 
---------------------------
97 
-- "10001101", -- $F80E BSR WAITRDY $F86A
98 
-- "01100000",
99 
"10001101", -- $F808 BSR $F874 -- test sub call
100 
"01101010",
101 
---------------------------
102 
"10000110", -- $F80A LDA #$E0
103 
"11100000",
104 
"10010111", -- $F80C STA <$E016
105 
"00010110",
106 
---------------------------
107 
-- "10001101", -- $F80E BSR WAITRDY $F86A
108 
-- "01011010",
109 
"10001101", -- $F80E BSR $F810
110 
"00000000",
111 
--------------------------
112 
"10000110", -- $F810 LDA #$01
113 
"00000001",
114 
"10010111", -- $F812 STA <$E011
115 
"00010001",
116 
"10000110", -- $F814 LDA #$EF
117 
"11101111",
118 
"10010111", -- $F816 STA <$E017
119 
"00010111",
120 
--------------------------
121 
-- "10001101", -- $F818 BSR WAITRDY $F86A
122 
-- "01010000",
123 
"10001101", -- $F818 BSR $F816
124 
"00000000",
125 
--------------------------
126 
"00010000", -- $F81A LDY #$F800
127 
"10001110",
128 
"11111000",
129 
"00000000",
130 
"11000110", -- $F81E LDB #$7C
131 
"01111100",
132 
"10000110", -- $F820 LDA #$01 *** RDLP1
133 
"00000001",
134 
"10010111", -- $F822 STA <$E012
135 
"00010010",
136 
"11010111", -- $F824 STB <$E013
137 
"00010011",
138 
"10000110", -- $F826 LDA #$F4
139 
"11110100",
140 
"10010111", -- $F828 STA <$E014
141 
"00010100",
142 
"01001111", -- $F82A CLRA
143 
"10010111", -- $F82B STA <$E015
144 
"00010101",
145 
"10001110", -- $F82D LDX #512
146 
"00000010",
147 
"00000000",
148 
"10000110", -- $F830 LDA #$20
149 
"00100000",
150 
"10010111", -- $F832 STA <$E017
151 
"00010111",
152 
--------------------------
153 
-- "10001101", -- $F834 BSR WAITRDY $F86A
154 
-- "00110100",
155 
"10001101", -- $F834 BSR *
156 
"00000000",
157 
--------------------------
158 
"10010110", -- $F836 LDA <$E017 *** WAITDRQ
159 
"00010111",
160 
"10000101", -- $F838 BITA #$08
161 
"00001000",
162 
"00100111", -- $F83A BEQ WAITDRQ
163 
"11111010",
164 
"10010110", -- $F83C LDA <$E010
165 
"00010000",
166 
"10100111", -- $F83E STA ,Y+
167 
"10100000",
168 
"00110000", -- $F840 LEAX -1,X
169 
"00011111",
170 
"10001100", -- $F842 CMPX #$0000
171 
"00000000",
172 
"00000000",
173 
"00100110", -- $F845 BNE RDLP2
174 
"11110011",
175 
--------------------------
176 
-- "10001101", -- $F847 BSR WAITRDY $F86A
177 
-- "00100001",
178 
"10001101", -- $F847 BSR $F841
179 
"00000000",
180 
--------------------------
181 
"01011100", -- $F849 INCB
182 
"11000001", -- $F84A CMPB #$80
183 
"10000000",
184 
"00100110", -- $F84C BNE RDLP1
185 
"11010110",
186 
"10001110", -- $F84E LDX #$FF97
187 
"11111111",
188 
"10010111",
189 
"00010000", -- $F851 LDY #$F000
190 
"10001110",
191 
"11110000",
192 
"00000000",
193 
"11000110", -- $F855 LDB #$61
194 
"01100001",
195 
"10100110", -- $F857 LDA 0,X+ *** MOVELP
196 
"10000000",
197 
"10100111", -- $F859 STA 0,Y+
198 
"10100000",
199 
"01011010", -- $F85B DECB
200 
----------------------------
201 
-- "00100110", -- $F85C BNE MOVELP
202 
-- "11111001",
203 
"00100110", --$F85C BNE $F861
204 
"00000011",
205 
----------------------------
206 
"01111110", -- $F85E JMP $F000
207 
"11110000",
208 
"00000000",
209 
"00001111", -- $F861 CLR <$E030
210 
"00110000",
211 
"01001111", -- $F863 CLRA
212 
"00011111", -- $F864 TFR A,DPR
213 
"10001011",
214 
"01101110", -- $F866 JMP [$FFFE]
215 
"10011111",
216 
"11111111",
217 
"11111110",
218 
--
219 
-- Wait for Ready
220 
--
221 
"10010110", -- $F86A LDA <$E017 *** WAITRDY
222 
"00010111",
223 
"00101011", -- $F86C BMI WAITRDY
224 
"11111100",
225 
"10010110", -- $F86E LDA <$E017
226 
"00010111",
227 
"10000101", -- $F870 BITA #$40
228 
"01000000",
229 
"00100111", -- $F872 BNE WAITRQY
230 
"11110110",
231 
"00111001", -- $F874 RTS
232 
"00010010", -- $F875 NOP
233 
"11111000", -- $F876 FDB $F80A -- dummy sub return
234 
"00001010",
235 
"11111000", -- $F878 FDB $F800
236 
"00000000",
237 
"11111000", -- $F87A FDB $F800
238 
"00000000",
239 
"11111000", -- $F87C FDB $F800
240 
"00000000",
241 
"11111000", -- $F87E FDB $F800
242 
"00000000"
243 
         );
244 
 
245 
component cpu09
246 
  port (
247 
         clk:        in std_logic;
248 
    rst:             in std_logic;
249 
    rw:      out        std_logic;              -- Asynchronous memory interface
250 
    vma:             out        std_logic;
251 122 dilbert57 
    addr:     out       std_logic_vector(15 downto 0);
252 19 dilbert57 
    data_in:  in        std_logic_vector(7 downto 0);
253 
         data_out: out std_logic_vector(7 downto 0);
254 
         halt:     in  std_logic;
255 
         hold:     in  std_logic;
256 
         irq:      in  std_logic;
257 
         nmi:      in  std_logic;
258 
         firq:     in  std_logic
259 
  );
260 
end component cpu09;
261 
 
262 
 
263 
begin
264 
cpu : cpu09  port map (
265 
         clk         => SysClk,
266 
    rst      => cpu_reset,
267 
    rw       => cpu_rw,
268 
    vma       => cpu_vma,
269 122 dilbert57 
    addr      => cpu_addr(15 downto 0),
270 19 dilbert57 
    data_in   => cpu_data_in,
271 
         data_out  => cpu_data_out,
272 
         halt      => '0',
273 
         hold      => '0',
274 
         irq       => cpu_irq,
275 
         nmi       => cpu_nmi,
276 
         firq      => cpu_firq
277 
  );
278 
 
279 
  -- *** Test Bench - User Defined Section ***
280 
   tb : PROCESS
281 
        variable count : integer;
282 
   BEGIN
283 
 
284 
        cpu_reset <= '0';
285 
        SysClk <= '0';
286 
   cpu_irq <= '0';
287 
   cpu_nmi <= '0';
288 
        cpu_firq <= '0';
289 
 
290 
                for count in 0 to 512 loop
291 
                        SysClk <= '0';
292 
                        if count = 0 then
293 
                                cpu_reset <= '1';
294 
                        elsif count = 1 then
295 
                                cpu_reset <= '0';
296 
                        end if;
297 
                        wait for 100 ns;
298 
                        SysClk <= '1';
299 
                        wait for 100 ns;
300 
                end loop;
301 
 
302 
      wait; -- will wait forever
303 
   END PROCESS;
304 
-- *** End Test Bench - User Defined Section ***
305 
 
306 
 
307 
  rom : PROCESS( cpu_addr )
308 
  begin
309 
    cpu_data_in <= rom_data(conv_integer(cpu_addr(6 downto 0)));
310 
  end process;
311 
 
312 
end behavior; --===================== End of architecture =======================--
313 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.