OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Testbench/] [testbench3.vhd] - Blame information for rev 66

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 dilbert57
--===========================================================================----
2
--
3
--  T E S T B E N C H    tesetbench3 - CPU09 Testbench.
4
--
5
--  www.OpenCores.Org - September 2003
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : Testbench3.vhd
9
--
10
-- Purpose        : cpu09 Microprocessor Test Bench 3
11
--                  Contains ROM to test interrupts
12
--
13
-- Dependencies   : ieee.Std_Logic_1164
14
--                  ieee.std_logic_unsigned
15
--                  ieee.std_logic_arith
16
--                  ieee.numeric_std
17
--
18
-- Uses           : cpu09    (cpu09.vhd)      CPU core
19
--                   
20
-- Author         : John E. Kent
21
--                  dilbert57@opencores.org      
22
--
23
--===========================================================================----
24
--
25
-- Revision History:
26
--===========================================================================--
27
--
28
-- Version 0.1 - 12 Apr 2003 - John Kent 
29
-- First version
30
--
31
-- Version 1.0 - 6 Sep 2003 - John Kent
32
-- Initial release to Open Cores
33
--
34
-- Version 1.1 - 26 Feb 2004 - John kent
35
-- removed test_alu and test_cc signals from
36
-- CPU component.
37
--===========================================================================--
38
 
39
library ieee;
40
   use ieee.std_logic_1164.all;
41
   use IEEE.STD_LOGIC_ARITH.ALL;
42
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
43
   use ieee.numeric_std.all;
44
 
45
entity my_testbench3 is
46
end my_testbench3;
47
 
48
-------------------------------------------------------------------------------
49
-- Architecture for memio Controller Unit
50
-------------------------------------------------------------------------------
51
architecture behavior of my_testbench3 is
52
  -----------------------------------------------------------------------------
53
  -- Signals
54
  -----------------------------------------------------------------------------
55
  signal cpu_irq    : std_Logic;
56
  signal cpu_firq   : std_logic;
57
  signal cpu_nmi    : std_logic;
58
 
59
  -- CPU Interface signals
60
  signal SysClk      : Std_Logic;
61
  signal cpu_reset   : Std_Logic;
62
  signal cpu_rw      : Std_Logic;
63
  signal cpu_vma     : Std_Logic;
64
  signal cpu_addr    : Std_Logic_Vector(15 downto 0);
65
  signal cpu_data_in : Std_Logic_Vector(7 downto 0);
66
  signal cpu_data_out: Std_Logic_Vector(7 downto 0);
67
 
68
  constant width   : integer := 8;
69
  constant memsize : integer := 64;
70
 
71
  type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
72
 
73
  constant rom_data : rom_array :=
74
  (
75
         "00010000", "11001110", "11111000", "00110000", -- F800 - 10CE F830 RET1    LDS #STACK
76
         "00111111",                                     -- F804 -   3F              SWI
77
         "00010000", "00111111",                         -- F805 - 103F      SWIVEC  SWI2
78
         "00010001", "00111111",                         -- F807 - 113F      SWI2VEC SWI3
79
         "00111011",                                     -- F809 -   3B      SWI3VEC RTI
80
         "00100000", "11111110",                         -- F80A -   20 FE           BRA *
81
         "10110001",                                     -- F80C -   B1      STACK3 FCB $B1 ; CC
82
         "00110010",                                     -- F80D -   32             FCB $32 ; ACCA
83
         "00110011",                                     -- F8OE -   33             FCB $33 ; ACCB
84
         "00110100",                                     -- F8OF -   34             FCB $34 ; DPR
85
         "00110101", "00110110",                         -- F810 - 3536             FDB $3536 ; IX
86
    "00110111", "00111000",                         -- F812 - 3738             FDB $3738 ; IY
87
    "00111001", "00111010",                         -- F814 - 393A             FDB $393A ; UP
88
         "11111000", "00001001",                         -- F816 - F809             FDB SWI3VEC ; PC
89
         "10100001",                                     -- F818 -   A1      STACK2 FCB $A1 ; CC
90
         "00100010",                                     -- F819 -   22             FCB $22 ; ACCA
91
         "00100011",                                     -- F81A -   23             FCB $23 ; ACCB
92
         "00100100",                                     -- F81B -   24             FCB $24 ; DPR
93
         "00100101", "00100110",                         -- F81C - 2526             FDB $2526 ; IX
94
    "00100111", "00101000",                         -- F81E - 2728             FDB $2728 ; IY
95
    "00101001", "00101010",                         -- F820 - 292A             FDB $292A ; UP
96
         "11111000", "00001001",                         -- F822 - F809             FDB SWI3VEC ; PC
97
         "10010001",                                     -- F824 -   91      STACK1 FCB $91 ; CC
98
         "00010010",                                     -- F825 -   12             FCB $12 ; ACCA
99
         "00010011",                                     -- F826 -   13             FCB $13 ; ACCB
100
         "00010100",                                     -- F827 -   14             FCB $14 ; DPR
101
         "00010101", "00010110",                         -- F828 - 1516             FDB $1516 ; IX
102
    "00010111", "00011000",                         -- F82A - 1718             FDB $1718 ; IY
103
    "00011001", "00011010",                         -- F82C - 191A             FDB $191A ; UP
104
         "11111000", "00000000",                         -- F82E - F800             FDB RESET ; PC
105
                                                                                                                                         -- F830             STACK  EQU *
106
                                                                                                                                         --
107
                                                                                                                                         -- Interrupt Cectors Start Here
108
                                                                                                                                         --
109
         "11111000", "00000000",                         -- F830 - F800             FDB RESET ; RESV
110
    "11111000", "00001001",                         -- F832 - F809             FDB SWIVEC3 ; SWI3
111
         "11111000", "00000111",                         -- F834 - F807             FDB SWIVEC2 ; SWI2
112
         "11111000", "00000000",                         -- F836 - F800             fdb RESET ; FIRQ
113
         "11111000", "00000000",                         -- F838 - F800             fdb RESET ; IRQ
114
         "11111000", "00000101",                         -- F83A - F805             fdb SWIVEC ; SWI
115
         "11111000", "00000000",                         -- F83C - F800             fcb RESET ; NMI
116
         "11111000", "00000000"                          -- F83E - F800             fdb RESET ; Reset
117
         );
118
 
119
component cpu09
120
  port (
121
         clk:        in std_logic;
122
    rst:             in std_logic;
123
    rw:      out        std_logic;              -- Asynchronous memory interface
124
    vma:             out        std_logic;
125
    address:  out       std_logic_vector(15 downto 0);
126
    data_in:  in        std_logic_vector(7 downto 0);
127
         data_out: out std_logic_vector(7 downto 0);
128
         halt:     in  std_logic;
129
         hold:     in  std_logic;
130
         irq:      in  std_logic;
131
         nmi:      in  std_logic;
132
         firq:     in  std_logic
133
  );
134
end component cpu09;
135
 
136
 
137
begin
138
cpu : cpu09  port map (
139
         clk         => SysClk,
140
    rst      => cpu_reset,
141
    rw       => cpu_rw,
142
    vma       => cpu_vma,
143
    address   => cpu_addr(15 downto 0),
144
    data_in   => cpu_data_in,
145
         data_out  => cpu_data_out,
146
         halt      => '0',
147
         hold      => '0',
148
         irq       => cpu_irq,
149
         nmi       => cpu_nmi,
150
         firq      => cpu_firq
151
  );
152
 
153
  -- *** Test Bench - User Defined Section ***
154
   tb : PROCESS
155
        variable count : integer;
156
   BEGIN
157
 
158
        cpu_reset <= '0';
159
        SysClk <= '0';
160
   cpu_irq <= '0';
161
   cpu_nmi <= '0';
162
        cpu_firq <= '0';
163
 
164
                for count in 0 to 512 loop
165
                        SysClk <= '0';
166
                        if count = 0 then
167
                                cpu_reset <= '1';
168
                        elsif count = 1 then
169
                                cpu_reset <= '0';
170
                        end if;
171
                        wait for 100 ns;
172
                        SysClk <= '1';
173
                        wait for 100 ns;
174
                end loop;
175
 
176
      wait; -- will wait forever
177
   END PROCESS;
178
-- *** End Test Bench - User Defined Section ***
179
 
180
 
181
  rom : PROCESS( cpu_addr )
182
  begin
183
    cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
184
  end process;
185
 
186
end behavior; --===================== End of architecture =======================--
187
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.