OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Testbench/] [testbench5.vhd] - Blame information for rev 100

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 dilbert57 
--===========================================================================----
2 
--
3 
--  T E S T B E N C H    tesetbench3 - CPU09 Testbench.
4 
--
5 
--  www.OpenCores.Org - September 2003
6 
--  This core adheres to the GNU public license
7 
--
8 
-- File name      : Testbench5.vhd
9 
--
10 
-- Purpose        : cpu09 Microprocessor Test Bench 3
11 
--                  Contains ROM to test interrupts
12 
--
13 
-- Dependencies   : ieee.Std_Logic_1164
14 
--                  ieee.std_logic_unsigned
15 
--                  ieee.std_logic_arith
16 
--                  ieee.numeric_std
17 
--
18 
-- Uses           : cpu09    (cpu09.vhd)      CPU core
19 
--
20 
-- Author         : John E. Kent
21 
--                  dilbert57@opencores.org
22 
--
23 
--===========================================================================----
24 
--
25 
-- Revision History:
26 
--===========================================================================--
27 
--
28 
-- Version 0.1 - 12st April 2003 - John Kent
29 
-- First version
30 
--
31 
-- Version 1.0 - 6 Sep 2003 - John Kent
32 
-- Initial release to Open Cores
33 
--
34 
-- Version 1.1 - 25th Jan 2004 - John Kent
35 
-- removed "test_alu" and "test_cc"
36 
--
37 
--===========================================================================--
38 
 
39 
library ieee;
40 
   use ieee.std_logic_1164.all;
41 
   use IEEE.STD_LOGIC_ARITH.ALL;
42 
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
43 
   use ieee.numeric_std.all;
44 
 
45 
entity my_testbench5 is
46 
end my_testbench5;
47 
 
48 
-------------------------------------------------------------------------------
49 
-- Architecture for  test bench for cpu09
50 
-------------------------------------------------------------------------------
51 
architecture behavior of my_testbench5 is
52 
  -----------------------------------------------------------------------------
53 
  -- Signals
54 
  -----------------------------------------------------------------------------
55 
  signal cpu_irq    : std_Logic;
56 
  signal cpu_firq   : std_logic;
57 
  signal cpu_nmi    : std_logic;
58 
 
59 
  -- CPU Interface signals
60 
  signal SysClk      : Std_Logic;
61 
  signal cpu_reset   : Std_Logic;
62 
  signal cpu_rw      : Std_Logic;
63 
  signal cpu_vma     : Std_Logic;
64 
  signal cpu_addr    : Std_Logic_Vector(15 downto 0);
65 
  signal cpu_data_in : Std_Logic_Vector(7 downto 0);
66 
  signal cpu_data_out: Std_Logic_Vector(7 downto 0);
67 
 
68 
  constant width   : integer := 8;
69 
  constant memsize : integer := 128;
70 
 
71 
  type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
72 
 
73 
  constant rom_data : rom_array :=
74 
  (
75 
         x"10", x"CE", x"F8", x"30", -- F800 - 10CE F830 RESET   LDS #$F830
76 
                x"CE", x"20", x"00", -- F804 -   CE 2000         LDU #$2000
77 
                x"8E", x"F8", x"02", -- F807 -   8E 5000         LDX #$F802
78 
         x"10", x"8E", x"80", x"00", -- F80A - 108E 8000         LDY #$8000
79 
                x"86", x"55",        -- F80E -   86 55           LDA #$55
80 
                          x"C6", x"F0",        -- F810 -   C6 F0           LDB #$F0
81 
                          x"97", x"40",        -- F812 -   97 40           STA <$40
82 
                          x"B7", x"90", x"00", -- F814 -   B7 9000         STA $9000
83 
                          x"A7", x"09",        -- F817 -   A7 09           STA 9,X ($F80B)
84 
                          x"A7", x"29",        -- F819 -   A7 29           STA 9,Y ($8009)
85 
                          x"A7", x"49",        -- F81B -   A7 49           STA 9,U ($2009)
86 
                          x"A7", x"69",        -- F81D -   A7 69           STA 9,S ($F839)
87 
                          x"A7", x"80",        -- F81F -   A7 80           STA ,X+ ($F802)
88 
                          x"A7", x"81",        -- F821 -   A7 81           STA ,X++     ($F803)
89 
                          x"A7", x"91",        -- F823 -   A7 91           STA [,X++] ($2000)
90 
                          x"A7", x"82",        -- F825 -   A7 82           STA ,-X ($F806)
91 
                          x"A7", x"83",        -- F827 -   A7 83           STA ,--X     ($F804)
92 
                          x"A7", x"93",        -- F829 -   A7 93           STA [,--X] ($2000)
93 
                          x"A7", x"84",        -- F82B -   A7 84           STA ,X ($F802)
94 
                          x"A7", x"94",        -- F82D -   A7 94           STA [,X] ($F830)
95 
                          x"A7", x"85",        -- F82F -   A7 85           STA B,X ($F7F2)
96 
                          x"A7", x"95",        -- F831 -   A7 95           STA [B,X] ($01A7)
97 
                          x"A7", x"86",        -- F833 -   A7 86           STA A,X ($F857)
98 
                          x"A7", x"96",        -- F835 -   A7 96           STA [A,X] ($A78C)
99 
                          x"A7", x"88", x"FF", -- F837 -   A7 88 FF        STA -1,X ($F831)
100 
                          x"A7", x"88", x"01", -- F83A -   A7 88 01        STA 1,X ($F833)
101 
                          x"A7", x"98", x"FF", -- F83D -   A7 98 FF        STA [-1,X] ([$F801])
102 
                          x"A7", x"98", x"01", -- F840 -   A7 98 01        STA [1,X] ([$F803])
103 
         x"A7", x"89", x"FF", x"FF", -- F843 -   A7 89 FFFF      STA -1,X ($F801)
104 
         x"A7", x"89", x"00", x"01", -- F847 -   A7 89 0001      STA 1,X ($F803)
105 
         x"A7", x"99", x"FF", x"FF", -- F84B -   A7 99 FFFF      STA [-1,X] ([$F801])
106 
         x"A7", x"99", x"00", x"01", -- F84F -   A7 99 0001      STA [1,X] ([$F803])
107 
                          x"A7", x"8B",        -- F853 -   A7 8B           STA D,X ($4BF2)
108 
                          x"A7", x"9B",        -- F855 -   A7 9B           STA [D,X] ([$4BF2]))
109 
                          x"A7", x"8C", x"FF", -- F857 -   A7 8C FF        STA -1,X ($F801)
110 
                          x"A7", x"8C", x"01", -- F85A -   A7 8C 01        STA 1,X ($F803)
111 
                          x"A7", x"9C", x"FF", -- F85D -   A7 9C FF        STA [-1,X] ([$F801])
112 
                          x"A7", x"9C", x"01", -- F860 -   A7 9C 01        STA [1,X] ([$F803])
113 
         x"A7", x"8D", x"FF", x"FF", -- F863 -   A7 8D FFFF      STA -1,X ($F801)
114 
         x"A7", x"8D", x"00", x"01", -- F867 -   A7 8D 0001      STA 1,X ($F803)
115 
         x"A7", x"9D", x"FF", x"FF", -- F86B -   A7 9D FFFF      STA [-1,X] ([$F801])
116 
         x"A7", x"9D", x"00", x"01", -- F86F -   A7 9D 0001      STA [1,X] ([$F803])
117 
         x"A7", x"8F", x"A0", x"00", -- F873 -   A7 8F A000      STA $A000
118 
         x"A7", x"9F", x"A0", x"00", -- F877 -   A7 9F A000      STA [$A000]
119 
                          x"7E", x"F8", x"00", -- F87B -   7E F800         JMP RESET
120 
                x"F8", x"00"         -- F87E -      F800         fdb RESET ; Reset
121 
         );
122 
 
123 
component cpu09
124 
  port (
125 
         clk:        in std_logic;
126 
    rst:             in std_logic;
127 
    rw:      out        std_logic;              -- Asynchronous memory interface
128 
    vma:             out        std_logic;
129 
    address:  out       std_logic_vector(15 downto 0);
130 
    data_in:  in        std_logic_vector(7 downto 0);
131 
         data_out: out std_logic_vector(7 downto 0);
132 
         halt:     in  std_logic;
133 
         hold:     in  std_logic;
134 
         irq:      in  std_logic;
135 
         nmi:      in  std_logic;
136 
         firq:     in  std_logic
137 
  );
138 
end component cpu09;
139 
 
140 
 
141 
begin
142 
cpu : cpu09  port map (
143 
         clk         => SysClk,
144 
    rst      => cpu_reset,
145 
    rw       => cpu_rw,
146 
    vma       => cpu_vma,
147 
    address   => cpu_addr(15 downto 0),
148 
    data_in   => cpu_data_in,
149 
         data_out  => cpu_data_out,
150 
         halt      => '0',
151 
         hold      => '0',
152 
         irq       => cpu_irq,
153 
         nmi       => cpu_nmi,
154 
         firq      => cpu_firq
155 
  );
156 
 
157 
  -- *** Test Bench - User Defined Section ***
158 
   tb : PROCESS
159 
        variable count : integer;
160 
   BEGIN
161 
 
162 
        cpu_reset <= '0';
163 
        SysClk <= '0';
164 
   cpu_irq <= '0';
165 
   cpu_nmi <= '0';
166 
        cpu_firq <= '0';
167 
 
168 
                for count in 0 to 512 loop
169 
                        SysClk <= '0';
170 
                        if count = 0 then
171 
                                cpu_reset <= '1';
172 
                        elsif count = 1 then
173 
                                cpu_reset <= '0';
174 
                        end if;
175 
                        wait for 100 ns;
176 
                        SysClk <= '1';
177 
                        wait for 100 ns;
178 
                end loop;
179 
 
180 
      wait; -- will wait forever
181 
   END PROCESS;
182 
-- *** End Test Bench - User Defined Section ***
183 
 
184 
 
185 
  rom : PROCESS( cpu_addr )
186 
  begin
187 
    cpu_data_in <= rom_data(conv_integer(cpu_addr(6 downto 0)));
188 
  end process;
189 
 
190 
end behavior; --===================== End of architecture =======================--
191 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.