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dilbert57 |
--===========================================================================--
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-- --
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-- TESTBENCH testbench5 - CPU09 Testbench. --
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-- --
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--===========================================================================--
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dilbert57 |
--
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-- File name : Testbench5.vhd
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--
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dilbert57 |
-- Purpose : cpu09 Microprocessor Test Bench 5
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dilbert57 |
-- Contains ROM to test interrupts
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_arith
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-- ieee.numeric_std
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--
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dilbert57 |
-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core
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dilbert57 |
--
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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dilbert57 |
--
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-- Copyright (C) 2003 - 2011 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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-- Rev Date Author Changes
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-- 0.1 2003-04-12 John Kent First version
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-- 1.0 2003-09-06 John Kent Initial release to Opencores.org
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-- 1.1 2004-02-25 John kent removed test_alu and test_cc signals from CPU component.
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-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header
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dilbert57 |
--
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--===========================================================================--
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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entity my_testbench5 is
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end my_testbench5;
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-------------------------------------------------------------------------------
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-- Architecture for test bench for cpu09
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-------------------------------------------------------------------------------
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architecture behavior of my_testbench5 is
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-----------------------------------------------------------------------------
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-- Signals
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-----------------------------------------------------------------------------
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signal cpu_irq : std_Logic;
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signal cpu_firq : std_logic;
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signal cpu_nmi : std_logic;
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-- CPU Interface signals
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signal SysClk : Std_Logic;
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signal cpu_reset : Std_Logic;
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signal cpu_rw : Std_Logic;
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signal cpu_vma : Std_Logic;
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signal cpu_addr : Std_Logic_Vector(15 downto 0);
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signal cpu_data_in : Std_Logic_Vector(7 downto 0);
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signal cpu_data_out: Std_Logic_Vector(7 downto 0);
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constant width : integer := 8;
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constant memsize : integer := 128;
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type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
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constant rom_data : rom_array :=
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(
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x"10", x"CE", x"F8", x"30", -- F800 - 10CE F830 RESET LDS #$F830
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x"CE", x"20", x"00", -- F804 - CE 2000 LDU #$2000
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x"8E", x"F8", x"02", -- F807 - 8E 5000 LDX #$F802
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x"10", x"8E", x"80", x"00", -- F80A - 108E 8000 LDY #$8000
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x"86", x"55", -- F80E - 86 55 LDA #$55
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x"C6", x"F0", -- F810 - C6 F0 LDB #$F0
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x"97", x"40", -- F812 - 97 40 STA <$40
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x"B7", x"90", x"00", -- F814 - B7 9000 STA $9000
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x"A7", x"09", -- F817 - A7 09 STA 9,X ($F80B)
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x"A7", x"29", -- F819 - A7 29 STA 9,Y ($8009)
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x"A7", x"49", -- F81B - A7 49 STA 9,U ($2009)
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x"A7", x"69", -- F81D - A7 69 STA 9,S ($F839)
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x"A7", x"80", -- F81F - A7 80 STA ,X+ ($F802)
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x"A7", x"81", -- F821 - A7 81 STA ,X++ ($F803)
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x"A7", x"91", -- F823 - A7 91 STA [,X++] ($2000)
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x"A7", x"82", -- F825 - A7 82 STA ,-X ($F806)
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x"A7", x"83", -- F827 - A7 83 STA ,--X ($F804)
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x"A7", x"93", -- F829 - A7 93 STA [,--X] ($2000)
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x"A7", x"84", -- F82B - A7 84 STA ,X ($F802)
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x"A7", x"94", -- F82D - A7 94 STA [,X] ($F830)
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x"A7", x"85", -- F82F - A7 85 STA B,X ($F7F2)
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x"A7", x"95", -- F831 - A7 95 STA [B,X] ($01A7)
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x"A7", x"86", -- F833 - A7 86 STA A,X ($F857)
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x"A7", x"96", -- F835 - A7 96 STA [A,X] ($A78C)
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x"A7", x"88", x"FF", -- F837 - A7 88 FF STA -1,X ($F831)
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x"A7", x"88", x"01", -- F83A - A7 88 01 STA 1,X ($F833)
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x"A7", x"98", x"FF", -- F83D - A7 98 FF STA [-1,X] ([$F801])
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x"A7", x"98", x"01", -- F840 - A7 98 01 STA [1,X] ([$F803])
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x"A7", x"89", x"FF", x"FF", -- F843 - A7 89 FFFF STA -1,X ($F801)
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x"A7", x"89", x"00", x"01", -- F847 - A7 89 0001 STA 1,X ($F803)
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x"A7", x"99", x"FF", x"FF", -- F84B - A7 99 FFFF STA [-1,X] ([$F801])
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x"A7", x"99", x"00", x"01", -- F84F - A7 99 0001 STA [1,X] ([$F803])
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x"A7", x"8B", -- F853 - A7 8B STA D,X ($4BF2)
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x"A7", x"9B", -- F855 - A7 9B STA [D,X] ([$4BF2]))
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x"A7", x"8C", x"FF", -- F857 - A7 8C FF STA -1,X ($F801)
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x"A7", x"8C", x"01", -- F85A - A7 8C 01 STA 1,X ($F803)
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x"A7", x"9C", x"FF", -- F85D - A7 9C FF STA [-1,X] ([$F801])
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x"A7", x"9C", x"01", -- F860 - A7 9C 01 STA [1,X] ([$F803])
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x"A7", x"8D", x"FF", x"FF", -- F863 - A7 8D FFFF STA -1,X ($F801)
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x"A7", x"8D", x"00", x"01", -- F867 - A7 8D 0001 STA 1,X ($F803)
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x"A7", x"9D", x"FF", x"FF", -- F86B - A7 9D FFFF STA [-1,X] ([$F801])
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x"A7", x"9D", x"00", x"01", -- F86F - A7 9D 0001 STA [1,X] ([$F803])
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x"A7", x"8F", x"A0", x"00", -- F873 - A7 8F A000 STA $A000
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x"A7", x"9F", x"A0", x"00", -- F877 - A7 9F A000 STA [$A000]
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x"7E", x"F8", x"00", -- F87B - 7E F800 JMP RESET
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x"F8", x"00" -- F87E - F800 fdb RESET ; Reset
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);
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component cpu09
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port (
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clk: in std_logic;
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rst: in std_logic;
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rw: out std_logic; -- Asynchronous memory interface
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vma: out std_logic;
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dilbert57 |
addr: out std_logic_vector(15 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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halt: in std_logic;
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hold: in std_logic;
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irq: in std_logic;
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nmi: in std_logic;
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firq: in std_logic
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);
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end component cpu09;
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begin
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cpu : cpu09 port map (
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clk => SysClk,
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rst => cpu_reset,
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rw => cpu_rw,
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vma => cpu_vma,
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addr => cpu_addr(15 downto 0),
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data_in => cpu_data_in,
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data_out => cpu_data_out,
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halt => '0',
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hold => '0',
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irq => cpu_irq,
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nmi => cpu_nmi,
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firq => cpu_firq
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);
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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variable count : integer;
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BEGIN
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cpu_reset <= '0';
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SysClk <= '0';
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cpu_irq <= '0';
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cpu_nmi <= '0';
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cpu_firq <= '0';
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for count in 0 to 512 loop
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SysClk <= '0';
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if count = 0 then
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cpu_reset <= '1';
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elsif count = 1 then
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cpu_reset <= '0';
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end if;
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wait for 100 ns;
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SysClk <= '1';
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wait for 100 ns;
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end loop;
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wait; -- will wait forever
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END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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rom : PROCESS( cpu_addr )
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begin
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cpu_data_in <= rom_data(conv_integer(cpu_addr(6 downto 0)));
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end process;
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end behavior; --===================== End of architecture =======================--
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