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dilbert57 |
--===========================================================================----
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--
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-- T E S T B E N C H tesetbench3 - CPU09 Testbench.
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--
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-- www.OpenCores.Org - September 2003
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-- This core adheres to the GNU public license
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--
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-- File name : Testbench6.vhd
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--
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-- Purpose : cpu09 Microprocessor Test Bench 6
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-- Tests STS indexed
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_arith
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-- ieee.numeric_std
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--
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-- Uses : cpu09 (cpu09.vhd) CPU core
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--
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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--
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--===========================================================================----
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--
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-- Revision History:
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--===========================================================================--
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--
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-- Version 0.1 - 12st April 2003 - John Kent
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-- First version
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--
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-- Version 1.0 - 6 Sep 2003 - John Kent
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-- Initial release to Open Cores
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--
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-- Version 1.1 - 25th Jan 2004 - John Kent
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-- removed "test_alu" and "test_cc"
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--
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--===========================================================================--
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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entity my_testbench6 is
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end my_testbench6;
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-------------------------------------------------------------------------------
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-- Architecture for memio Controller Unit
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-------------------------------------------------------------------------------
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architecture behavior of my_testbench6 is
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-----------------------------------------------------------------------------
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-- Signals
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-----------------------------------------------------------------------------
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signal cpu_irq : std_Logic;
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signal cpu_firq : std_logic;
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signal cpu_nmi : std_logic;
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-- CPU Interface signals
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signal SysClk : Std_Logic;
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signal cpu_reset : Std_Logic;
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signal cpu_rw : Std_Logic;
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signal cpu_vma : Std_Logic;
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signal cpu_addr : Std_Logic_Vector(15 downto 0);
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signal cpu_data_in : Std_Logic_Vector(7 downto 0);
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signal cpu_data_out: Std_Logic_Vector(7 downto 0);
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constant width : integer := 8;
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constant memsize : integer := 64;
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type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
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constant rom_data : rom_array :=
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(
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x"10",x"CE", x"F8", x"30", -- F800 - 10CE F830 RET1 LDS #STACK
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x"CE",x"B0",x"00", -- F804 - CE B000 LDU #$B000
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x"10",x"EF",x"C8",x"00", -- F807 - 10EF C800 STS $00,U
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x"12",x"12",x"12", -- F80B - 12 12 12
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"00110011", -- F8OE - 33 FCB $33 ; ACCB
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"00110100", -- F8OF - 34 FCB $34 ; DPR
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"00110101", "00110110", -- F810 - 3536 FDB $3536 ; IX
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"00110111", "00111000", -- F812 - 3738 FDB $3738 ; IY
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"00111001", "00111010", -- F814 - 393A FDB $393A ; UP
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"11111000", "00001001", -- F816 - F809 FDB SWI3VEC ; PC
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"10100001", -- F818 - A1 STACK2 FCB $A1 ; CC
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"00100010", -- F819 - 22 FCB $22 ; ACCA
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"00100011", -- F81A - 23 FCB $23 ; ACCB
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"00100100", -- F81B - 24 FCB $24 ; DPR
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"00100101", "00100110", -- F81C - 2526 FDB $2526 ; IX
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"00100111", "00101000", -- F81E - 2728 FDB $2728 ; IY
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"00101001", "00101010", -- F820 - 292A FDB $292A ; UP
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"11111000", "00001001", -- F822 - F809 FDB SWI3VEC ; PC
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"10010001", -- F824 - 91 STACK1 FCB $91 ; CC
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"00010010", -- F825 - 12 FCB $12 ; ACCA
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"00010011", -- F826 - 13 FCB $13 ; ACCB
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"00010100", -- F827 - 14 FCB $14 ; DPR
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"00010101", "00010110", -- F828 - 1516 FDB $1516 ; IX
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"00010111", "00011000", -- F82A - 1718 FDB $1718 ; IY
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"00011001", "00011010", -- F82C - 191A FDB $191A ; UP
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"11111000", "00000000", -- F82E - F800 FDB RESET ; PC
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-- F830 STACK EQU *
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--
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-- Interrupt Cectors Start Here
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--
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"11111000", "00000000", -- F830 - F800 FDB RESET ; RESV
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"11111000", "00001001", -- F832 - F809 FDB SWIVEC3 ; SWI3
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"11111000", "00000111", -- F834 - F807 FDB SWIVEC2 ; SWI2
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"11111000", "00000000", -- F836 - F800 fdb RESET ; FIRQ
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"11111000", "00000000", -- F838 - F800 fdb RESET ; IRQ
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"11111000", "00000101", -- F83A - F805 fdb SWIVEC ; SWI
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"11111000", "00000000", -- F83C - F800 fcb RESET ; NMI
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"11111000", "00000000" -- F83E - F800 fdb RESET ; Reset
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);
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component cpu09
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port (
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clk: in std_logic;
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rst: in std_logic;
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rw: out std_logic; -- Asynchronous memory interface
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vma: out std_logic;
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address: out std_logic_vector(15 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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halt: in std_logic;
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hold: in std_logic;
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irq: in std_logic;
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nmi: in std_logic;
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firq: in std_logic
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);
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end component cpu09;
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begin
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cpu : cpu09 port map (
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clk => SysClk,
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rst => cpu_reset,
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rw => cpu_rw,
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vma => cpu_vma,
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address => cpu_addr(15 downto 0),
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data_in => cpu_data_in,
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data_out => cpu_data_out,
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halt => '0',
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hold => '0',
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irq => cpu_irq,
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nmi => cpu_nmi,
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firq => cpu_firq
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);
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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variable count : integer;
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BEGIN
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cpu_reset <= '0';
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SysClk <= '0';
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cpu_irq <= '0';
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cpu_nmi <= '0';
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cpu_firq <= '0';
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for count in 0 to 512 loop
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SysClk <= '0';
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if count = 0 then
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cpu_reset <= '1';
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elsif count = 1 then
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cpu_reset <= '0';
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end if;
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wait for 100 ns;
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SysClk <= '1';
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wait for 100 ns;
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end loop;
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wait; -- will wait forever
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END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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rom : PROCESS( cpu_addr )
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begin
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cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
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end process;
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end behavior; --===================== End of architecture =======================--
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