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[/] [System09/] [trunk/] [rtl/] [Testbench/] [vdu8_tb.vhd] - Blame information for rev 203

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Line No. Rev Author Line
1 122 dilbert57
--===========================================================================--
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--                                                                           --
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--             TESTBENCH    vdu8_tb - VDU8 Testbench.                    --
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--                                                                           --
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--===========================================================================--
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--
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-- File name      : vdu8_tb.vhd
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--
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-- Purpose        : Test system09 VDU8 component
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_unsigned
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--                  ieee.std_logic_arith
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--                  ieee.numeric_std
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--
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-- Uses           : vdu8     (..\VHDL\vdu8.vhd)              CPU core
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--                  ram_2k   (..\Spartan3\ram2k_b16.vhd)      2KB block RAM
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--                  char_rom (..\Spartan3\char_rom2k_b16.vhd) 2KB chracter block ROM
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--                   
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-- Author         : John E. Kent
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--                  dilbert57@opencores.org      
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-- 
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--  Copyright (C) 2008 - 2011 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                                Revision History                           --
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--                                                                           --
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--===========================================================================--
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--
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-- Rev  Date       Author     Changes
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-- 0.1  2008-07-30 John Kent  First version
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-- 0.2  2011-10-09 John Kent  updated header & vdu component
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--
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--===========================================================================--
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library ieee;
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   use ieee.std_logic_1164.all;
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   use IEEE.STD_LOGIC_ARITH.ALL;
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   use IEEE.STD_LOGIC_UNSIGNED.ALL;
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   use ieee.numeric_std.all;
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library unisim;
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   use unisim.vcomponents.all;
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entity my_vdu8_tb is
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end my_vdu8_tb;
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architecture behavior of my_vdu8_tb is
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constant CPU_FREQ             : natural := 25_000_000;  -- CPU Clock (Hz)
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constant PIX_FREQ             : natural := 25_000_000;  -- VGA Pixel Clock
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         -- CRTC output signals
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signal    vga_vsync_n  : Std_Logic;
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signal    vga_hsync_n  : Std_Logic;
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signal    vga_blue     : std_logic;
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signal    vga_green    : std_logic;
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signal    vga_red      : std_logic;
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-- CPU Debug Interface signals
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signal    cpu_reset     : Std_Logic;
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signal    cpu_clk       : Std_Logic;
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signal    cpu_rw        : std_logic;
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signal    cpu_addr      : std_logic_vector(2 downto 0);
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signal    vdu_data_out  : std_logic_vector(7 downto 0);
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signal    cpu_data_out  : std_logic_vector(7 downto 0);
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signal    pix_clk       : std_logic;
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signal    vdu_cs        : std_logic;
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----------------------------------------
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--
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-- Video Display Unit.
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--
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----------------------------------------
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component vdu8
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  generic(
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        VGA_CLK_FREQ           : integer := PIX_FREQ; -- HZ
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             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
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             VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
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             VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us
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             VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us
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             VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us
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             VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
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             VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
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             VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
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             VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
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             VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
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  );
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  port(
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    -- control register interface
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    vdu_clk      : in  std_logic;       -- 12.5/25 MHz CPU Clock
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    vdu_rst      : in  std_logic;
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    vdu_cs       : in  std_logic;
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    vdu_rw       : in  std_logic;
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    vdu_addr     : in  std_logic_vector(2 downto 0);
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    vdu_data_in  : in  std_logic_vector(7 downto 0);
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    vdu_data_out : out std_logic_vector(7 downto 0);
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    -- vga port connections
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    vga_clk      : in  std_logic;       -- 25MHz clock
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    vga_red_o    : out std_logic;
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    vga_green_o  : out std_logic;
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    vga_blue_o   : out std_logic;
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    vga_hsync_o  : out std_logic;
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    vga_vsync_o  : out std_logic
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    );
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end component;
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begin
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----------------------------------------
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--
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-- Video Display Unit instantiation
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--
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----------------------------------------
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my_vdu : vdu8
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  generic map(
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      VGA_CLK_FREQ           => PIX_FREQ, -- HZ
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           VGA_HOR_CHARS          => 80, -- CHARACTERS
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           VGA_HOR_CHAR_PIXELS    => 8,  -- PIXELS
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           VGA_HOR_FRONT_PORCH    => 16, -- PIXELS
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           VGA_HOR_SYNC           => 96, -- PIXELS
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           VGA_HOR_BACK_PORCH     => 48, -- PIXELS
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           VGA_VER_CHARS          => 25, -- CHARACTERS
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           VGA_VER_CHAR_LINES     => 16, -- LINES
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           VGA_VER_FRONT_PORCH    => 10, -- LINES
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           VGA_VER_SYNC           => 2,  -- LINES
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           VGA_VER_BACK_PORCH     => 34  -- LINES
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  )
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  port map(
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                -- Control Registers
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                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
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      vdu_rst       => cpu_reset,
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                vdu_cs        => vdu_cs,
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                vdu_rw        => cpu_rw,
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                vdu_addr      => cpu_addr(2 downto 0),
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                vdu_data_in   => cpu_data_out,
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                vdu_data_out  => vdu_data_out,
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      -- vga port connections
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      vga_clk       => pix_clk,                                  -- 25 MHz VDU pixel clock
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      vga_red_o     => vga_red,
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      vga_green_o   => vga_green,
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      vga_blue_o    => vga_blue,
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      vga_hsync_o   => vga_hsync_n,
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      vga_vsync_o   => vga_vsync_n
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   );
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events : PROCESS(pix_clk)
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variable count : integer := 0;
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BEGIN
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                if falling_edge(cpu_clk) then
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                   case count is
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                        --
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                        -- reset VDU registers
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                        --
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                   when 0 =>
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                          cpu_reset    <= '1';
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                          vdu_cs       <= '0';
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                          cpu_rw       <= '1';
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                          cpu_addr     <= "000";
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                          cpu_data_out <= "00000000";
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         when  8 =>
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                          cpu_reset <= '0';
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         --
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                        -- write data register
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                        --
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         when 10 =>
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                          vdu_cs       <= '1';
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                          cpu_rw       <= '0';
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                          cpu_addr     <= "000";
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                          cpu_data_out <= "01101001";
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         when 11 =>
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                          vdu_cs       <= '0';
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                          cpu_rw       <= '1';
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         --
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                        -- write attribute register
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                        --
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         when 12 =>
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                          vdu_cs       <= '1';
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                          cpu_rw       <= '0';
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                          cpu_addr     <= "001";
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                          cpu_data_out <= "00000111";
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         when 13 =>
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                          vdu_cs       <= '0';
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                          cpu_rw       <= '1';
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         --
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                        -- write cursor column ?
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         when 14 =>
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                          vdu_cs       <= '1';
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                          cpu_rw       <= '0';
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                          cpu_addr     <= "010";
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                          cpu_data_out <= "00000001";
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         when 15 =>
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                          vdu_cs       <= '0';
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                          cpu_rw       <= '1';
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         --
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                        -- write cursor row ?
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                        --
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         when 16 =>
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                          vdu_cs       <= '1';
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                          cpu_rw       <= '0';
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                          cpu_addr     <= "011";
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                          cpu_data_out <= "00000011";
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         when 17 =>
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                          vdu_cs       <= '0';
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                          cpu_rw       <= '1';
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         --
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                        -- write vertical offset
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                        --
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         when 18 =>
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                          vdu_cs       <= '1';
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                          cpu_rw       <= '0';
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                          cpu_addr     <= "100";
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                          cpu_data_out <= "00001001";
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         when 19 =>
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                          vdu_cs       <= '0';
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                          cpu_rw       <= '1';
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         when others =>
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                          null;
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         end case;
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                        count := count + 1;
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       end if;
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end process;
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--
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-- Generate a master clock for the SDRAM controller
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--
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   tb : PROCESS
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        variable i : integer;
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   BEGIN
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                for i in 0 to 360000 loop
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                        pix_clk <= '0';
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                        cpu_clk <= '0';
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                        wait for 20 ns;
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                        pix_clk <= '1';
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                        cpu_clk <= '1';
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                        wait for 20 ns;
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      end loop;
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      wait; -- will wait forever
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   end process;
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-- *** End Test Bench - User Defined Section ***
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end architecture;

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