OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [VHDL/] [SevenSegment.vhd] - Blame information for rev 104

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 99 davidgb
--===========================================================================--
2
--                                                                           --
3
--  SevenSegment.vhd - Synthesizable Multiplex Seven Segment LED Driver      --
4
--                                                                           --
5
--===========================================================================--
6 19 dilbert57
--
7 99 davidgb
--  File name      : SevenSegment.vhd
8 19 dilbert57
--
9 99 davidgb
--  Entity name    : SevenSegment
10 19 dilbert57
--
11 99 davidgb
--  Purpose        : 4 x 8 bit lathes to display 7 segments
12
--                   Multiplexes segment registers across 4 displays.
13
--                   For use on the Digilent Spartan 3 Starter Board
14 19 dilbert57
--                  
15 99 davidgb
--  Dependencies   : ieee.std_logic_1164
16
--                   ieee.std_logic_unsigned
17
--                   unisim.vcomponents
18
--
19
--  Author         : John E. Kent
20
--
21
--  Email          : dilbert57@opencores.org      
22
--
23
--  Web            : http://opencores.org/project,system09
24
--
25
--  SevenSegment.vhd is a multiplexed seven segment LED display driver written in VHDL
26
-- 
27
--  Copyright (C) 2004 - 2010 John Kent
28
--
29
--  This program is free software: you can redistribute it and/or modify
30
--  it under the terms of the GNU General Public License as published by
31
--  the Free Software Foundation, either version 3 of the License, or
32
--  (at your option) any later version.
33
--
34
--  This program is distributed in the hope that it will be useful,
35
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
36
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
37
--  GNU General Public License for more details.
38
--
39
--  You should have received a copy of the GNU General Public License
40
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
41
--
42
--===========================================================================--
43
--                                                                           --
44
--                              Revision  History                            --
45
--                                                                           --
46
--===========================================================================--
47
--
48
-- Version  Author        Date               Description
49
-- 0.1      John Kent     19 Oct 2004        Initial version
50
-- 0.2      John Kent     21 Nov 2006        Inverted segment registers 
51
--                                           so '0' in segment registers 
52
--                                           switches segment OFF
53
-- 0.3      John Kent     31 May 2010        Updated Header and GPL.
54 19 dilbert57
--
55
 
56
library ieee;
57 99 davidgb
   use ieee.std_logic_1164.all;
58
   use ieee.std_logic_unsigned.all;
59
 
60
library unisim;
61
   use unisim.vcomponents.all;
62 19 dilbert57
 
63
entity seven_segment is
64
        port (
65
         clk       : in  std_logic;
66
    rst       : in  std_logic;
67
    cs        : in  std_logic;
68
    rw        : in  std_logic;
69
    addr      : in  std_logic_vector(1 downto 0);
70
    data_in   : in  std_logic_vector(7 downto 0);
71
         data_out  : out std_logic_vector(7 downto 0);
72
         segments  : out std_logic_vector(7 downto 0);
73
         digits   : out std_logic_vector(3 downto 0)
74
         );
75
end;
76
 
77
architecture rtl of seven_segment is
78 99 davidgb
signal seg_reg0     : std_logic_vector(7 downto 0);
79
signal seg_reg1     : std_logic_vector(7 downto 0);
80
signal seg_reg2     : std_logic_vector(7 downto 0);
81
signal seg_reg3     : std_logic_vector(7 downto 0);
82 19 dilbert57
 
83 99 davidgb
signal ClockDivider : std_logic_vector(13 downto 0);
84
signal WhichDigit   : std_logic_vector(1 downto 0);
85 19 dilbert57
 
86
begin
87
 
88
---------------------------------
89
--
90
-- Write Segment registers
91
--
92
---------------------------------
93
 
94
seg_write : process( clk, rst, addr, cs, rw, data_in )
95
begin
96
  if clk'event and clk = '0' then
97
    if rst = '1' then
98
      seg_reg0 <= "00000000";
99
      seg_reg1 <= "00000000";
100
      seg_reg2 <= "00000000";
101
      seg_reg3 <= "00000000";
102
    else
103
           if cs = '1' and rw = '0' then
104
        case addr is
105
             when "00" =>
106
                    seg_reg0 <= data_in;
107
             when "01" =>
108
                    seg_reg1 <= data_in;
109
             when "10" =>
110
                    seg_reg2 <= data_in;
111
             when "11" =>
112
                    seg_reg3 <= data_in;
113
        when others =>
114
                    null;
115
                  end case;
116
           end if;
117
         end if;
118
  end if;
119
end process;
120
 
121
---------------------------------
122
--
123
-- Read Segment registers
124
--
125
---------------------------------
126
 
127
seg_read : process(  addr,
128
                     seg_reg0, seg_reg1, seg_reg2, seg_reg3 )
129
begin
130
      case addr is
131
             when "00" =>
132
                    data_out <= seg_reg0;
133
             when "01" =>
134
                    data_out <= seg_reg1;
135
             when "10" =>
136
                    data_out <= seg_reg2;
137
             when "11" =>
138
                    data_out <= seg_reg3;
139
        when others =>
140
                    null;
141
                end case;
142
end process;
143
 
144
---------------------------------
145
--
146
-- Output Segment registers
147
--
148
---------------------------------
149
 
150
seg_out : process( rst, Clk)
151
begin
152
                if rst = '1' then
153
                        ClockDivider <= (others => '0');
154
                        WhichDigit   <= "00";
155
                        Segments     <= "00000000";
156
                        Digits      <= "1111";
157
                elsif Clk'Event and Clk = '0' then
158
                        if ClockDivider = "11000011010011" then
159
                                ClockDivider <= (others => '0');
160
                                case WhichDigit is      -- note that everything is pipelined
161
                                        when "00" =>
162
                                                Digits   <= "1110";
163
                                                Segments <= not( seg_reg0 );
164
                                        when "01" =>
165 99 davidgb
                                                Digits   <= "1101";
166 19 dilbert57
                                                Segments <= not( seg_reg1 );
167
                                        when "10" =>
168 99 davidgb
                                                Digits   <= "1011";
169 19 dilbert57
                                                Segments <= not( seg_reg2 );
170
                                        when "11" =>
171 99 davidgb
                                                Digits   <= "0111";
172 19 dilbert57
                                                Segments <= not( seg_reg3 );
173
                                        when others =>
174
                                           null;
175
                                end case;
176
                                WhichDigit <= WhichDigit + 1;
177
                        else
178
                                ClockDivider <= ClockDivider + 1;
179
                        end if;
180
                end if;
181
end process;
182
 
183
end rtl;
184
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.