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[/] [System09/] [trunk/] [rtl/] [VHDL/] [SevenSegmentDisplay.vhd] - Blame information for rev 211

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1 19 dilbert57
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--  Uncomment the following lines to use the declarations that are
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--  provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity SevenSegmentDisplay is
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    Port ( Clk : in std_logic;
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           Reset : in std_logic;
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           Value0 : in std_logic_vector(3 downto 0);
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           Value1 : in std_logic_vector(3 downto 0);
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           Value2 : in std_logic_vector(3 downto 0);
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           Value3 : in std_logic_vector(3 downto 0);
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                          DPs    : in std_logic_vector(3 downto 0);
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                          Blanks        : in std_logic_vector(3 downto 0);
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           DigitSelect : out std_logic_vector(3 downto 0);
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           Segments : out std_logic_vector(7 downto 0));
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end SevenSegmentDisplay;
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architecture Behavioral of SevenSegmentDisplay is
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        signal ClockDivider             : std_logic_vector(13 downto 0);
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        signal WhichDigit                       : std_logic_vector(1 downto 0);
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        signal Result                           : std_logic_vector(7 downto 0);
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        signal DigitValue                       : std_logic_vector(3 downto 0);
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        signal DP                                       : std_logic;
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        signal Blank                            : std_logic;
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        component DecoderDriver
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        port(
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                DigitValue      : in std_logic_vector(3 downto 0);
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                DP                              : in std_logic;
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                Blank                   : in std_logic;
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                Segments                : out std_logic_vector(7 downto 0));
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        end component;
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begin
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        process(Reset,Clk) is
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        begin
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                if Reset = '1' then
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                        ClockDivider <= (others => '0');
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                        WhichDigit   <= "00";
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                        DigitSelect     <= "1111";
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                elsif Clk = '1' and Clk'Event then
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                        if ClockDivider = "11000011010011" then
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                                ClockDivider <= (others => '0');
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                                Segments <= Result;
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                                case WhichDigit is      -- note that everything is pipelined
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                                        when "00" =>
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                                                DigitSelect <= "1110";
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                                                DigitValue <= Value1;
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                                                DP <= DPs(1);
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                                                Blank <= Blanks(1);
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                                        when "01" =>
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                                                DigitSelect <= "1101";
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                                                DigitValue <= Value2;
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                                                DP <= DPs(2);
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                                                Blank <= Blanks(2);
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                                        when "10" =>
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                                                DigitSelect <= "1011";
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                                                DigitValue <= Value3;
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                                                DP <= DPs(3);
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                                                Blank <= Blanks(3);
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                                        when "11" =>
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                                                DigitSelect <= "0111";
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                                                DigitValue <= Value0;
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                                                DP <= DPs(0);
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                                                Blank <= Blanks(0);
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                                        when others => null;
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                                end case;
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                                WhichDigit <= WhichDigit + 1;
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                        else
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                                ClockDivider <= ClockDivider + 1;
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                        end if;
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                end if;
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        end process;
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        Inst_DecoderDriver: DecoderDriver PORT MAP (
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                DigitValue => DigitValue,
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                DP => DP,
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                Blank => Blank,
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                Segments => Result
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        );
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end Behavioral;

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