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[/] [System09/] [trunk/] [rtl/] [VHDL/] [cpu09l.vhd] - Blame information for rev 127

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1 122 dilbert57
--===========================================================================--
2
--                                                                           --
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--        Synthesizable 6809 instruction compatible VHDL CPU core            --
4
--                                                                           --
5
--===========================================================================--
6
--
7
-- File name      : cpu09l.vhd
8
--
9
-- Entity name    : cpu09
10
--
11
-- Purpose        : 6809 instruction compatible CPU core written in VHDL
12
--                  with Last Instruction Cycle, bus available, bus status,
13
--                  and instruction fetch signals.
14
--                  Not cycle compatible with the original 6809 CPU
15
--
16
-- Dependencies   : ieee.std_logic_1164
17
--                  ieee.std_logic_unsigned
18
--
19
-- Author         : John E. Kent
20
--
21
-- Email          : dilbert57@opencores.org      
22
--
23
-- Web            : http://opencores.org/project,system09
24
--
25
-- Description    : VMA (valid memory address) is hight whenever a valid memory
26
--                  access is made by an instruction fetch, interrupt vector fetch
27
--                  or a data read or write otherwise it is low indicating an idle
28
--                  bus cycle.
29
--                  IFETCH (instruction fetch output) is high whenever an
30
--                  instruction byte is read i.e. the program counter is applied 
31
--                  to the address bus.
32
--                  LIC (last instruction cycle output) is normally low
33
--                  but goes high on the last cycle of an instruction.
34
--                  BA (bus available output) is normally low but goes high while
35
--                  waiting in a Sync instruction state or the CPU is halted
36
--                  i.e. a DMA grant.
37
--                  BS (bus status output) is normally low but goes high during an
38
--                  interrupt or reset vector fetch or the processor is halted
39
--                  i.e. a DMA grant.
40
-- 
41
--  Copyright (C) 2003 - 2010 John Kent
42
--
43
--  This program is free software: you can redistribute it and/or modify
44
--  it under the terms of the GNU General Public License as published by
45
--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
47
--
48
--  This program is distributed in the hope that it will be useful,
49
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
50
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
52
--
53
--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
55
--
56
--===========================================================================--
57
--                                                                           --
58
--                                Revision History                           --
59
--                                                                           --
60
--===========================================================================--
61
--
62
-- Version 0.1 - 26 June 2003 - John Kent
63
-- Added extra level in state stack
64
-- fixed some calls to the extended addressing state
65
--
66
-- Version 0.2 - 5 Sept 2003 - John Kent
67
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
68
-- Added/Fixed STY and STS instructions.
69
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
70
-- CMPX Loaded ACCA and ACCB - Now fixed 
71
--
72
-- Version 1.0 - 6 Sep 2003 - John Kent 
73
-- Initial release to Open Cores
74
-- reversed clock edge
75
--
76
-- Version 1.1 - 29 November 2003 John kent
77
--      ACCA and ACCB indexed offsets are 2's complement.
78
-- ALU Right Mux now sign extends ACCA & ACCB offsets
79
-- Absolute Indirect addressing performed a read on the
80
-- second byte of the address rather than a fetch
81
-- so it formed an incorrect address. Now fixed. 
82
--
83
-- Version 1.2 - 29 November 2003 John Kent
84
-- LEAX and LEAY affect the Z bit only
85
--      LEAS and LEAU do not affect any condition codes
86
-- added an extra ALU control for LEA.
87
--
88
-- Version 1.3 - 12 December 2003 John Kent
89
-- CWAI did not work, was missed a PUSH_ST on calling
90
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
91
-- finding this fault.
92
--
93
-- Version 1.4 - 12 December 2003 John Kent
94
-- Missing cc_ctrl assignment in otherwise case of 
95
-- lea_state resulted in cc_ctrl being latched in
96
-- that state.  
97
-- The otherwise statement should never be reached,
98
-- and has been fixed simply to resolve synthesis warnings.
99
--
100
-- Version 1.5 - 17 january 2004 John kent
101
-- The clear instruction used "alu_ld8" to control the ALU
102
-- rather than "alu_clr". This mean the Carry was not being
103
-- cleared correctly.
104
--
105
-- Version 1.6 - 24 January 2004 John Kent
106
-- Fixed problems in PSHU instruction
107
--
108
-- Version 1.7 - 25 January 2004 John Kent
109
-- removed redundant "alu_inx" and "alu_dex'
110
-- Removed "test_alu" and "test_cc"
111
-- STD instruction did not set condition codes
112
-- JMP direct was not decoded properly
113
-- CLR direct performed an unwanted read cycle
114
-- Bogus "latch_md" in Page2 indexed addressing
115
--
116
-- Version 1.8 - 27 January 2004 John Kent
117
-- CWAI in decode1_state should increment the PC.
118
-- ABX is supposed to be an unsigned addition.
119
-- Added extra ALU function
120
-- ASR8 slightly changed in the ALU.
121
--
122
--      Version 1.9 - 20 August 2005
123
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
124
-- rather than LSR16. There was a problem with single 
125
-- operand instructions using the MD register which is
126
-- sign extended on the first 8 bit fetch.
127
--
128
-- Version 1.10 - 13 September 2005
129
-- TFR & EXG instructions did not work for the Condition Code Register
130
-- An extra case has been added to the ALU for the alu_tfr control 
131
-- to assign the left ALU input (alu_left) to the condition code
132
-- outputs (cc_out). 
133
--
134
-- Version 1.11 - 16 September 2005
135
-- JSR ,X should not predecrement S before calculating the jump address.
136
-- The reason is that JSR [0,S] needs S to point to the top of the stack
137
-- to fetch a valid vector address. The solution is to have the addressing
138
-- mode microcode called before decrementing S and then decrementing S in
139
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
140
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
141
-- pushed on the stack. This adds one extra bus cycle, but resolves the
142
-- addressing conflict. I've also removed the pre-decement S in 
143
-- JSR EXTENDED as it also calls JSR_STATE.
144
--
145
-- Version 1.12 - 6th June 2006
146
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
147
-- This is different to the 6800. CLR should reset the V bit.
148
--
149
-- Version 1.13 - 7th July 2006
150
-- Disable NMI on reset until S Stack pointer has been loaded.
151
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
152
--
153
-- Version 1.14 - 11th July 2006
154
-- 1. Added new state to RTI called rti_entire_state.
155
-- This state tests the CC register after it has been loaded
156
-- from the stack. Previously the current CC was tested which
157
-- was incorrect. The Entire Flag should be set before the
158
-- interrupt stacks the CC.
159
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
160
-- which was an enumerated state, but not defined anywhere.
161
-- rti_state has been changed to rti_cc_state so that bogus interrupt
162
-- will perform an RTI after entering that state.
163
-- 3. Sync should generate an interrupt if the interrupt masks
164
-- are cleared. If the interrupt masks are set, then an interrupt
165
-- will cause the the PC to advance to the next instruction.
166
-- Note that I don't wait for an interrupt to be asserted for
167
-- three clock cycles.
168
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
169
-- the Multiply instruction replacing "alu_add16". This is similar 
170
-- to "alu_add16" except it sets the Carry bit to B7 of the result
171
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
172
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
173
-- flags. The logic was re-arranged so that it adds md or zero so 
174
-- that the Carry condition code is set on zero multiplicands.
175
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
176
-- and Zero Flags. It will also affect the Overflow (V) flag although
177
-- the operation is undefined. It's anyones guess what DAA does to V.
178
--
179
-- Version 1.15 - 25th Feb 2007 - John Kent
180
-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
181
-- Changed sensitivity lists.
182
--
183
-- Version 1.16 - 5th February 2008 - John Kent
184
-- FIRQ interrupts should take priority over IRQ Interrupts.
185
-- This presumably means they should be tested for before IRQ
186
-- when they happen concurrently.
187
--
188
-- Version 1.17 - 18th February 2008 - John Kent
189
-- NMI in CWAI should mask IRQ and FIRQ interrupts
190
--
191
-- Version 1.18 - 21st February 2008 - John Kent
192
-- Removed default register settings in each case statement
193
-- and placed them at the beginning of the state sequencer.
194
-- Modified the SYNC instruction so that the interrupt vector(iv)
195
-- is not set unless an unmasked FIRQ or IRQ is received.
196
--
197
-- Version 1.19 - 25th February 2008 - John Kent
198
-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
199
-- Enumerated separate states for MASKI and MASKIF states
200
-- Removed code on BSR/JSR in fetch cycle
201
--
202
-- Version 1.10 - 8th October 2011 - John Kent
203
-- added fetch output which should go high during the fetch cycle
204
--
205
-- Version 1.11 - 8th October 2011 - John Kent
206
-- added Last Instruction Cycle signal
207
-- replaced fetch with ifetch (instruction fetch) signal
208
-- added ba & bs (bus available & bus status) signals
209
--
210
library ieee;
211
use ieee.std_logic_1164.all;
212
use ieee.std_logic_unsigned.all;
213
 
214
entity cpu09 is
215
        port (
216
                clk      :      in std_logic;                     -- E clock input (falling edge)
217
                rst      :  in std_logic;                     -- reset input (active high)
218
                vma      : out std_logic;                     -- valid memory address (active high)
219
      lic      : out std_logic;                     -- last instruction cycle (active high)
220
      ifetch   : out std_logic;                     -- instruction fetch cycle (active high)
221
      ba       : out std_logic;                     -- bus available (high on sync wait or DMA grant)
222
      bs       : out std_logic;                     -- bus status (high on interrupt or reset vector fetch or DMA grant)
223
                addr     : out std_logic_vector(15 downto 0); -- address bus output
224
                rw       : out std_logic;                     -- read not write output
225
           data_out : out std_logic_vector(7 downto 0);  -- data bus output
226
           data_in  :  in std_logic_vector(7 downto 0);  -- data bus input
227
                irq      :  in std_logic;                     -- interrupt request input (active high)
228
                firq     :  in std_logic;                     -- fast interrupt request input (active high)
229
                nmi      :  in std_logic;                     -- non maskable interrupt request input (active high)
230
                halt     :  in std_logic;                     -- halt input (active high) grants DMA
231
                hold     :  in std_logic                      -- hold input (active high) extend bus cycle
232
                );
233
end cpu09;
234
 
235
architecture rtl of cpu09 is
236
 
237
  constant EBIT : integer := 7;
238
  constant FBIT : integer := 6;
239
  constant HBIT : integer := 5;
240
  constant IBIT : integer := 4;
241
  constant NBIT : integer := 3;
242
  constant ZBIT : integer := 2;
243
  constant VBIT : integer := 1;
244
  constant CBIT : integer := 0;
245
 
246
  --
247
  -- Interrupt vector modifiers
248
  --
249
  constant RST_VEC  : std_logic_vector(2 downto 0) := "111";
250
  constant NMI_VEC  : std_logic_vector(2 downto 0) := "110";
251
  constant SWI_VEC  : std_logic_vector(2 downto 0) := "101";
252
  constant IRQ_VEC  : std_logic_vector(2 downto 0) := "100";
253
  constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
254
  constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
255
  constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
256
  constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
257
 
258
        type state_type is (-- Start off in Reset
259
                            reset_state,
260
                                                          -- Fetch Interrupt Vectors (including reset)
261
                                                          vect_lo_state, vect_hi_state,
262
                       -- Fetch Instruction Cycle
263
                       fetch_state,
264
                                                          -- Decode Instruction Cycles
265
                       decode1_state, decode2_state, decode3_state,
266
                                                          -- Calculate Effective Address
267
                                                     imm16_state,
268
                                 indexed_state, index8_state, index16_state, index16_2_state,
269
                                                          pcrel8_state, pcrel16_state, pcrel16_2_state,
270
                                                          indexaddr_state, indexaddr2_state,
271
                                                     postincr1_state, postincr2_state,
272
                                                          indirect_state, indirect2_state, indirect3_state,
273
                       extended_state,
274
                                                          -- single ops
275
                                                          single_op_read_state,
276
                                                     single_op_exec_state,
277
                            single_op_write_state,
278
                                                          -- Dual op states
279
                                                          dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
280
                                                     dual_op_write8_state, dual_op_write16_state,
281
                       -- 
282
                                                     sync_state, halt_state, error_state,
283
                                                          --
284
                                                          andcc_state, orcc_state,
285
                                                          tfr_state, exg_state, exg1_state,
286
                                                          lea_state,
287
                                                          -- Multiplication
288
                                                     mul_state, mulea_state, muld_state,
289
                                                     mul0_state, mul1_state, mul2_state, mul3_state,
290
                                                     mul4_state, mul5_state, mul6_state, mul7_state,
291
                                                          --  Branches
292
                                                          lbranch_state, sbranch_state,
293
                                                          -- Jumps, Subroutine Calls and Returns
294
                       jsr_state, jmp_state,
295
                       push_return_hi_state, push_return_lo_state,
296
                       pull_return_hi_state, pull_return_lo_state,
297
                                                          -- Interrupt cycles
298
                                                          int_nmiirq_state, int_firq_state,
299
                                                          int_entire_state, int_fast_state,
300
                                                          int_pcl_state,  int_pch_state,
301
                                                     int_upl_state,  int_uph_state,
302
                                                     int_iyl_state,  int_iyh_state,
303
                                                     int_ixl_state,  int_ixh_state,
304
                                                     int_dp_state,
305
                                           int_accb_state, int_acca_state,
306
                                                     int_cc_state,
307
                                                     int_cwai_state,
308
                                                          int_maski_state, int_maskif_state,
309
                                                          -- Return From Interrupt
310
                                                     rti_cc_state,   rti_entire_state,
311
                                                          rti_acca_state, rti_accb_state,
312
                                                     rti_dp_state,
313
                                                     rti_ixl_state,  rti_ixh_state,
314
                                                     rti_iyl_state,  rti_iyh_state,
315
                                                     rti_upl_state,  rti_uph_state,
316
                                                     rti_pcl_state,  rti_pch_state,
317
                                                          -- Push Registers using SP
318
                                                          pshs_state,
319
                                                     pshs_pcl_state,  pshs_pch_state,
320
                                                     pshs_upl_state,  pshs_uph_state,
321
                                                     pshs_iyl_state,  pshs_iyh_state,
322
                                                     pshs_ixl_state,  pshs_ixh_state,
323
                                                     pshs_dp_state,
324
                                                     pshs_acca_state, pshs_accb_state,
325
                                                     pshs_cc_state,
326
                                                          -- Pull Registers using SP
327
                                                          puls_state,
328
                                                          puls_cc_state,
329
                                                          puls_acca_state, puls_accb_state,
330
                                                          puls_dp_state,
331
                                                     puls_ixl_state,  puls_ixh_state,
332
                                                     puls_iyl_state,  puls_iyh_state,
333
                                                     puls_upl_state,  puls_uph_state,
334
                                                     puls_pcl_state,  puls_pch_state,
335
                                                          -- Push Registers using UP
336
                                                          pshu_state,
337
                                                     pshu_pcl_state,  pshu_pch_state,
338
                                                     pshu_spl_state,  pshu_sph_state,
339
                                                     pshu_iyl_state,  pshu_iyh_state,
340
                                                     pshu_ixl_state,  pshu_ixh_state,
341
                                                     pshu_dp_state,
342
                                                     pshu_acca_state, pshu_accb_state,
343
                                                     pshu_cc_state,
344
                                                          -- Pull Registers using UP
345
                                                          pulu_state,
346
                                                          pulu_cc_state,
347
                                                          pulu_acca_state, pulu_accb_state,
348
                                                          pulu_dp_state,
349
                                                     pulu_ixl_state,  pulu_ixh_state,
350
                                                     pulu_iyl_state,  pulu_iyh_state,
351
                                                     pulu_spl_state,  pulu_sph_state,
352
                                                     pulu_pcl_state,  pulu_pch_state );
353
 
354
        type stack_type is array(2 downto 0) of state_type;
355
        type st_type    is (idle_st, push_st, pull_st );
356
        type addr_type  is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
357
        type dout_type  is (cc_dout, acca_dout, accb_dout, dp_dout,
358
                       ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
359
                       up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
360
                       pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
361
   type op_type    is (reset_op, fetch_op, latch_op );
362
   type pre_type   is (reset_pre, fetch_pre, latch_pre );
363
   type cc_type    is (reset_cc, load_cc, pull_cc, latch_cc );
364
   type acca_type  is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
365
   type accb_type  is (reset_accb, load_accb, pull_accb, latch_accb );
366
   type dp_type    is (reset_dp, load_dp, pull_dp, latch_dp );
367
        type ix_type    is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
368
        type iy_type    is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
369
        type sp_type    is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
370
        type up_type    is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
371
        type pc_type    is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
372
   type md_type    is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
373
   type ea_type    is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
374
        type iv_type    is (latch_iv, reset_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv);
375
        type nmi_type   is (reset_nmi, set_nmi, latch_nmi );
376
        type left_type  is (cc_left, acca_left, accb_left, dp_left,
377
                                                          ix_left, iy_left, up_left, sp_left,
378
                       accd_left, md_left, pc_left, ea_left );
379
        type right_type is (ea_right, zero_right, one_right, two_right,
380
                       acca_right, accb_right, accd_right,
381
                                                          md_right, md_sign5_right, md_sign8_right );
382
   type alu_type   is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
383
                       alu_and, alu_ora, alu_eor,
384
                       alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
385
                                                     alu_lsr16, alu_lsl16,
386
                                                     alu_ror8, alu_rol8, alu_mul,
387
                                                     alu_asr8, alu_asl8, alu_lsr8,
388
                                                     alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
389
                                                          alu_seif, alu_sei, alu_see, alu_cle,
390
                                                     alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
391
 
392
        signal op_code:     std_logic_vector(7 downto 0);
393
        signal pre_code:    std_logic_vector(7 downto 0);
394
        signal acca:        std_logic_vector(7 downto 0);
395
        signal accb:        std_logic_vector(7 downto 0);
396
   signal cc:          std_logic_vector(7 downto 0);
397
        signal cc_out:      std_logic_vector(7 downto 0);
398
        signal dp:          std_logic_vector(7 downto 0);
399
        signal xreg:        std_logic_vector(15 downto 0);
400
        signal yreg:        std_logic_vector(15 downto 0);
401
        signal sp:          std_logic_vector(15 downto 0);
402
        signal up:          std_logic_vector(15 downto 0);
403
        signal ea:          std_logic_vector(15 downto 0);
404
        signal pc:              std_logic_vector(15 downto 0);
405
        signal md:          std_logic_vector(15 downto 0);
406
   signal left:        std_logic_vector(15 downto 0);
407
   signal right:       std_logic_vector(15 downto 0);
408
        signal out_alu:     std_logic_vector(15 downto 0);
409
        signal iv:          std_logic_vector(2 downto 0);
410
        signal nmi_req:     std_logic;
411
        signal nmi_ack:     std_logic;
412
        signal nmi_enable:  std_logic;
413
 
414
        signal state:        state_type;
415
        signal next_state:   state_type;
416
        signal saved_state:  state_type;
417
        signal return_state: state_type;
418
        signal state_stack:  stack_type;
419
        signal st_ctrl:      st_type;
420
   signal pc_ctrl:      pc_type;
421
   signal ea_ctrl:      ea_type;
422
   signal op_ctrl:      op_type;
423
        signal pre_ctrl:     pre_type;
424
        signal md_ctrl:      md_type;
425
        signal acca_ctrl:    acca_type;
426
        signal accb_ctrl:    accb_type;
427
        signal ix_ctrl:      ix_type;
428
        signal iy_ctrl:      iy_type;
429
        signal cc_ctrl:      cc_type;
430
        signal dp_ctrl:      dp_type;
431
        signal sp_ctrl:      sp_type;
432
        signal up_ctrl:      up_type;
433
        signal iv_ctrl:      iv_type;
434
        signal left_ctrl:    left_type;
435
        signal right_ctrl:   right_type;
436
   signal alu_ctrl:     alu_type;
437
   signal addr_ctrl:    addr_type;
438
   signal dout_ctrl:    dout_type;
439
   signal nmi_ctrl:     nmi_type;
440
 
441
 
442
begin
443
 
444
----------------------------------
445
--
446
-- State machine stack
447
--
448
----------------------------------
449
--state_stack_proc: process( clk, hold, state_stack, st_ctrl, 
450
--                           return_state, fetch_state  )
451
state_stack_proc: process( clk, state_stack )
452
begin
453
  if clk'event and clk = '0' then
454
    if hold= '1' then
455
           state_stack(0) <= state_stack(0);
456
           state_stack(1) <= state_stack(1);
457
           state_stack(2) <= state_stack(2);
458
         else
459
           case st_ctrl is
460
                when idle_st =>
461
                  state_stack(0) <= state_stack(0);
462
             state_stack(1) <= state_stack(1);
463
             state_stack(2) <= state_stack(2);
464
      when push_st =>
465
                  state_stack(0) <= return_state;
466
             state_stack(1) <= state_stack(0);
467
             state_stack(2) <= state_stack(1);
468
      when pull_st =>
469
                  state_stack(0) <= state_stack(1);
470
             state_stack(1) <= state_stack(2);
471
             state_stack(2) <= fetch_state;
472
                when others =>
473
                  state_stack(0) <= state_stack(0);
474
             state_stack(1) <= state_stack(1);
475
             state_stack(2) <= state_stack(2);
476
           end case;
477
    end if;
478
  end if;
479
  saved_state <= state_stack(0);
480
end process;
481
 
482
----------------------------------
483
--
484
-- Program Counter Control
485
--
486
----------------------------------
487
 
488
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
489
pc_reg: process( clk )
490
begin
491
  if clk'event and clk = '0' then
492
    if hold= '1' then
493
           pc <= pc;
494
         else
495
    case pc_ctrl is
496
         when reset_pc =>
497
           pc <= "0000000000000000";
498
         when load_pc =>
499
           pc <= out_alu(15 downto 0);
500
         when pull_lo_pc =>
501
           pc(7 downto 0) <= data_in;
502
         when pull_hi_pc =>
503
           pc(15 downto 8) <= data_in;
504
         when incr_pc =>
505
           pc <= pc + 1;
506
         when others =>
507
--       when latch_pc =>
508
      pc <= pc;
509
    end case;
510
         end if;
511
  end if;
512
end process;
513
 
514
----------------------------------
515
--
516
-- Effective Address  Control
517
--
518
----------------------------------
519
 
520
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
521
ea_reg: process( clk )
522
begin
523
 
524
  if clk'event and clk = '0' then
525
    if hold= '1' then
526
           ea <= ea;
527
         else
528
    case ea_ctrl is
529
         when reset_ea =>
530
           ea <= "0000000000000000";
531
         when fetch_first_ea =>
532
           ea(7 downto 0) <= data_in;
533
      ea(15 downto 8) <= dp;
534
         when fetch_next_ea =>
535
           ea(15 downto 8) <= ea(7 downto 0);
536
      ea(7 downto 0)  <= data_in;
537
         when load_ea =>
538
           ea <= out_alu(15 downto 0);
539
         when others =>
540
--       when latch_ea =>
541
      ea <= ea;
542
    end case;
543
         end if;
544
  end if;
545
end process;
546
 
547
--------------------------------
548
--
549
-- Accumulator A
550
--
551
--------------------------------
552
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
553
acca_reg : process( clk )
554
begin
555
  if clk'event and clk = '0' then
556
    if hold= '1' then
557
           acca <= acca;
558
         else
559
    case acca_ctrl is
560
    when reset_acca =>
561
           acca <= "00000000";
562
         when load_acca =>
563
           acca <= out_alu(7 downto 0);
564
         when load_hi_acca =>
565
           acca <= out_alu(15 downto 8);
566
         when pull_acca =>
567
           acca <= data_in;
568
         when others =>
569
--       when latch_acca =>
570
           acca <= acca;
571
    end case;
572
         end if;
573
  end if;
574
end process;
575
 
576
--------------------------------
577
--
578
-- Accumulator B
579
--
580
--------------------------------
581
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
582
accb_reg : process( clk )
583
begin
584
  if clk'event and clk = '0' then
585
    if hold= '1' then
586
           accb <= accb;
587
         else
588
    case accb_ctrl is
589
    when reset_accb =>
590
           accb <= "00000000";
591
         when load_accb =>
592
           accb <= out_alu(7 downto 0);
593
         when pull_accb =>
594
           accb <= data_in;
595
         when others =>
596
--       when latch_accb =>
597
           accb <= accb;
598
    end case;
599
         end if;
600
  end if;
601
end process;
602
 
603
--------------------------------
604
--
605
-- X Index register
606
--
607
--------------------------------
608
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
609
ix_reg : process( clk )
610
begin
611
  if clk'event and clk = '0' then
612
    if hold= '1' then
613
           xreg <= xreg;
614
         else
615
    case ix_ctrl is
616
    when reset_ix =>
617
           xreg <= "0000000000000000";
618
         when load_ix =>
619
           xreg <= out_alu(15 downto 0);
620
         when pull_hi_ix =>
621
           xreg(15 downto 8) <= data_in;
622
         when pull_lo_ix =>
623
           xreg(7 downto 0) <= data_in;
624
         when others =>
625
--       when latch_ix =>
626
           xreg <= xreg;
627
    end case;
628
         end if;
629
  end if;
630
end process;
631
 
632
--------------------------------
633
--
634
-- Y Index register
635
--
636
--------------------------------
637
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
638
iy_reg : process( clk )
639
begin
640
  if clk'event and clk = '0' then
641
    if hold= '1' then
642
           yreg <= yreg;
643
         else
644
    case iy_ctrl is
645
    when reset_iy =>
646
           yreg <= "0000000000000000";
647
         when load_iy =>
648
           yreg <= out_alu(15 downto 0);
649
         when pull_hi_iy =>
650
           yreg(15 downto 8) <= data_in;
651
         when pull_lo_iy =>
652
           yreg(7 downto 0) <= data_in;
653
         when others =>
654
--       when latch_iy =>
655
           yreg <= yreg;
656
    end case;
657
         end if;
658
  end if;
659
end process;
660
 
661
--------------------------------
662
--
663
-- S stack pointer
664
--
665
--------------------------------
666
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
667
sp_reg : process( clk )
668
begin
669
  if clk'event and clk = '0' then
670
    if hold= '1' then
671
           sp <= sp;
672
                nmi_enable <= nmi_enable;
673
         else
674
    case sp_ctrl is
675
    when reset_sp =>
676
           sp <= "0000000000000000";
677
                nmi_enable <= '0';
678
         when load_sp =>
679
           sp <= out_alu(15 downto 0);
680
                nmi_enable <= '1';
681
         when pull_hi_sp =>
682
           sp(15 downto 8) <= data_in;
683
                nmi_enable <= nmi_enable;
684
         when pull_lo_sp =>
685
           sp(7 downto 0) <= data_in;
686
                nmi_enable <= '1';
687
         when others =>
688
--       when latch_sp =>
689
           sp <= sp;
690
                nmi_enable <= nmi_enable;
691
    end case;
692
         end if;
693
  end if;
694
end process;
695
 
696
--------------------------------
697
--
698
-- U stack pointer
699
--
700
--------------------------------
701
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
702
up_reg : process( clk )
703
begin
704
  if clk'event and clk = '0' then
705
    if hold= '1' then
706
           up <= up;
707
         else
708
    case up_ctrl is
709
    when reset_up =>
710
           up <= "0000000000000000";
711
         when load_up =>
712
           up <= out_alu(15 downto 0);
713
         when pull_hi_up =>
714
           up(15 downto 8) <= data_in;
715
         when pull_lo_up =>
716
           up(7 downto 0) <= data_in;
717
         when others =>
718
--       when latch_up =>
719
           up <= up;
720
    end case;
721
         end if;
722
  end if;
723
end process;
724
 
725
--------------------------------
726
--
727
-- Memory Data
728
--
729
--------------------------------
730
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
731
md_reg : process( clk )
732
begin
733
  if clk'event and clk = '0' then
734
    if hold= '1' then
735
           md <= md;
736
         else
737
    case md_ctrl is
738
    when reset_md =>
739
           md <= "0000000000000000";
740
         when load_md =>
741
           md <= out_alu(15 downto 0);
742
         when fetch_first_md => -- sign extend md for branches
743
           md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
744
                              data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
745
           md(7 downto 0) <= data_in;
746
         when fetch_next_md =>
747
           md(15 downto 8) <= md(7 downto 0);
748
                md(7 downto 0) <= data_in;
749
         when shiftl_md =>
750
           md(15 downto 1) <= md(14 downto 0);
751
                md(0) <= '0';
752
         when others =>
753
--       when latch_md =>
754
           md <= md;
755
    end case;
756
         end if;
757
  end if;
758
end process;
759
 
760
 
761
----------------------------------
762
--
763
-- Condition Codes
764
--
765
----------------------------------
766
 
767
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
768
cc_reg: process( clk )
769
begin
770
  if clk'event and clk = '0' then
771
    if hold= '1' then
772
           cc <= cc;
773
         else
774
    case cc_ctrl is
775
         when reset_cc =>
776
           cc <= "11010000"; -- set EBIT, FBIT & IBIT
777
         when load_cc =>
778
           cc <= cc_out;
779
         when pull_cc =>
780
      cc <= data_in;
781
         when others =>
782
--  when latch_cc =>
783
      cc <= cc;
784
    end case;
785
         end if;
786
  end if;
787
end process;
788
 
789
----------------------------------
790
--
791
-- Direct Page register
792
--
793
----------------------------------
794
 
795
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
796
dp_reg: process( clk )
797
begin
798
  if clk'event and clk = '0' then
799
    if hold= '1' then
800
           dp <= dp;
801
         else
802
    case dp_ctrl is
803
         when reset_dp =>
804
           dp <= "00000000";
805
         when load_dp =>
806
           dp <= out_alu(7 downto 0);
807
         when pull_dp =>
808
      dp <= data_in;
809
         when others =>
810
--  when latch_dp =>
811
      dp <= dp;
812
    end case;
813
         end if;
814
  end if;
815
end process;
816
 
817
----------------------------------
818
--
819
-- interrupt vector
820
--
821
----------------------------------
822
 
823
--iv_mux: process( clk, iv_ctrl, hold, iv )
824
iv_mux: process( clk )
825
begin
826
  if clk'event and clk = '0' then
827
    if hold= '1' then
828
           iv <= iv;
829
         else
830
    case iv_ctrl is
831
         when reset_iv =>
832
           iv <= RST_VEC;
833
         when nmi_iv =>
834
      iv <= NMI_VEC;
835
         when swi_iv =>
836
      iv <= SWI_VEC;
837
         when irq_iv =>
838
      iv <= IRQ_VEC;
839
         when firq_iv =>
840
           iv <= FIRQ_VEC;
841
         when swi2_iv =>
842
      iv <= SWI2_VEC;
843
         when swi3_iv =>
844
      iv <= SWI3_VEC;
845
         when resv_iv =>
846
      iv <= RESV_VEC;
847
         when others =>
848
           iv <= iv;
849
    end case;
850
         end if;
851
  end if;
852
end process;
853
 
854
 
855
----------------------------------
856
--
857
-- op code register
858
--
859
----------------------------------
860
 
861
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
862
op_reg: process( clk )
863
begin
864
  if clk'event and clk = '0' then
865
    if hold= '1' then
866
           op_code <= op_code;
867
         else
868
    case op_ctrl is
869
         when reset_op =>
870
           op_code <= "00010010";
871
         when fetch_op =>
872
      op_code <= data_in;
873
         when others =>
874
--       when latch_op =>
875
           op_code <= op_code;
876
    end case;
877
         end if;
878
  end if;
879
end process;
880
 
881
 
882
----------------------------------
883
--
884
-- pre byte op code register
885
--
886
----------------------------------
887
 
888
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
889
pre_reg: process( clk )
890
begin
891
  if clk'event and clk = '0' then
892
    if hold= '1' then
893
           pre_code <= pre_code;
894
         else
895
    case pre_ctrl is
896
         when reset_pre =>
897
           pre_code <= "00000000";
898
         when fetch_pre =>
899
      pre_code <= data_in;
900
         when others =>
901
--       when latch_pre =>
902
           pre_code <= pre_code;
903
    end case;
904
         end if;
905
  end if;
906
end process;
907
 
908
--------------------------------
909
--
910
-- state machine
911
--
912
--------------------------------
913
 
914
--change_state: process( clk, rst, state, hold, next_state )
915
change_state: process( clk )
916
begin
917
  if clk'event and clk = '0' then
918
    if rst = '1' then
919
           state <= reset_state;
920
    else
921
           if hold = '1' then
922
                  state <= state;
923
                else
924
        state <= next_state;
925
                end if;
926
         end if;
927
  end if;
928
end process;
929
        -- output
930
 
931
------------------------------------
932
--
933
-- Nmi register
934
--
935
------------------------------------
936
 
937
--nmi_reg: process( clk, nmi_ctrl, hold, nmi_ack )
938
nmi_reg: process( clk )
939
begin
940
  if clk'event and clk='0' then
941
    if hold = '1' then
942
      nmi_ack <= nmi_ack;
943
    else
944
    case nmi_ctrl is
945
         when set_nmi =>
946
      nmi_ack <= '1';
947
         when reset_nmi =>
948
           nmi_ack <= '0';
949
         when others =>
950
--  when latch_nmi =>
951
           nmi_ack <= nmi_ack;
952
         end case;
953
         end if;
954
  end if;
955
end process;
956
 
957
------------------------------------
958
--
959
-- Detect Edge of NMI interrupt
960
--
961
------------------------------------
962
 
963
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
964
nmi_handler : process( rst, clk )
965
begin
966
  if rst='1' then
967
         nmi_req <= '0';
968
  elsif clk'event and clk='0' then
969
           if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
970
             nmi_req <= '1';
971
           else
972
                  if (nmi='0') and (nmi_ack='1') then
973
               nmi_req <= '0';
974
                  end if;
975
                end if;
976
  end if;
977
end process;
978
 
979
 
980
----------------------------------
981
--
982
-- Address output multiplexer
983
--
984
----------------------------------
985
 
986
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
987
begin
988
  ifetch <= '0';
989
  vma    <= '1';
990
  rw     <= '1';
991
  addr <= "1111111111111111";
992
  case addr_ctrl is
993
    when fetch_ad =>
994
           addr   <= pc;
995
      ifetch <= '1';
996
         when read_ad =>
997
           addr <= ea;
998
    when write_ad =>
999
           addr <= ea;
1000
                rw   <= '0';
1001
         when pushs_ad =>
1002
           addr <= sp;
1003
                rw   <= '0';
1004
    when pulls_ad =>
1005
           addr <= sp;
1006
         when pushu_ad =>
1007
           addr <= up;
1008
                rw   <= '0';
1009
    when pullu_ad =>
1010
           addr <= up;
1011
         when int_hi_ad =>
1012
           addr <= "111111111111" & iv & "0";
1013
    when int_lo_ad =>
1014
           addr <= "111111111111" & iv & "1";
1015
         when others =>
1016
      vma  <= '0';
1017
  end case;
1018
end process;
1019
 
1020
--------------------------------
1021
--
1022
-- Data Bus output
1023
--
1024
--------------------------------
1025
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
1026
begin
1027
    case dout_ctrl is
1028
         when cc_dout => -- condition code register
1029
           data_out <= cc;
1030
         when acca_dout => -- accumulator a
1031
           data_out <= acca;
1032
         when accb_dout => -- accumulator b
1033
           data_out <= accb;
1034
         when dp_dout => -- direct page register
1035
           data_out <= dp;
1036
         when ix_lo_dout => -- X index reg
1037
           data_out <= xreg(7 downto 0);
1038
         when ix_hi_dout => -- X index reg
1039
           data_out <= xreg(15 downto 8);
1040
         when iy_lo_dout => -- Y index reg
1041
           data_out <= yreg(7 downto 0);
1042
         when iy_hi_dout => -- Y index reg
1043
           data_out <= yreg(15 downto 8);
1044
         when up_lo_dout => -- U stack pointer
1045
           data_out <= up(7 downto 0);
1046
         when up_hi_dout => -- U stack pointer
1047
           data_out <= up(15 downto 8);
1048
         when sp_lo_dout => -- S stack pointer
1049
           data_out <= sp(7 downto 0);
1050
         when sp_hi_dout => -- S stack pointer
1051
           data_out <= sp(15 downto 8);
1052
         when md_lo_dout => -- alu output
1053
           data_out <= md(7 downto 0);
1054
         when md_hi_dout => -- alu output
1055
           data_out <= md(15 downto 8);
1056
         when pc_lo_dout => -- low order pc
1057
           data_out <= pc(7 downto 0);
1058
         when pc_hi_dout => -- high order pc
1059
           data_out <= pc(15 downto 8);
1060
         when others =>
1061
           data_out <= "00000000";
1062
    end case;
1063
end process;
1064
 
1065
----------------------------------
1066
--
1067
-- Left Mux
1068
--
1069
----------------------------------
1070
 
1071
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
1072
begin
1073
  case left_ctrl is
1074
         when cc_left =>
1075
           left(15 downto 8) <= "00000000";
1076
                left(7 downto 0)  <= cc;
1077
         when acca_left =>
1078
           left(15 downto 8) <= "00000000";
1079
                left(7 downto 0)  <= acca;
1080
         when accb_left =>
1081
           left(15 downto 8) <= "00000000";
1082
                left(7 downto 0)  <= accb;
1083
         when dp_left =>
1084
           left(15 downto 8) <= "00000000";
1085
                left(7 downto 0)  <= dp;
1086
         when accd_left =>
1087
           left(15 downto 8) <= acca;
1088
                left(7 downto 0)  <= accb;
1089
         when md_left =>
1090
           left <= md;
1091
         when ix_left =>
1092
           left <= xreg;
1093
         when iy_left =>
1094
           left <= yreg;
1095
         when sp_left =>
1096
           left <= sp;
1097
         when up_left =>
1098
           left <= up;
1099
         when pc_left =>
1100
           left <= pc;
1101
         when others =>
1102
--       when ea_left =>
1103
           left <= ea;
1104
    end case;
1105
end process;
1106
 
1107
----------------------------------
1108
--
1109
-- Right Mux
1110
--
1111
----------------------------------
1112
 
1113
right_mux: process( right_ctrl, md, acca, accb, ea )
1114
begin
1115
  case right_ctrl is
1116
         when ea_right =>
1117
           right <= ea;
1118
         when zero_right =>
1119
           right <= "0000000000000000";
1120
         when one_right =>
1121
           right <= "0000000000000001";
1122
         when two_right =>
1123
           right <= "0000000000000010";
1124
         when acca_right =>
1125
           if acca(7) = '0' then
1126
             right <= "00000000" & acca(7 downto 0);
1127
                else
1128
                  right <= "11111111" & acca(7 downto 0);
1129
                end if;
1130
         when accb_right =>
1131
           if accb(7) = '0' then
1132
             right <= "00000000" & accb(7 downto 0);
1133
                else
1134
                  right <= "11111111" & accb(7 downto 0);
1135
                end if;
1136
         when accd_right =>
1137
           right <= acca & accb;
1138
         when md_sign5_right =>
1139
           if md(4) = '0' then
1140
             right <= "00000000000" & md(4 downto 0);
1141
                else
1142
                  right <= "11111111111" & md(4 downto 0);
1143
                end if;
1144
         when md_sign8_right =>
1145
           if md(7) = '0' then
1146
             right <= "00000000" & md(7 downto 0);
1147
                else
1148
                  right <= "11111111" & md(7 downto 0);
1149
                end if;
1150
         when others =>
1151
--       when md_right =>
1152
           right <= md;
1153
    end case;
1154
end process;
1155
 
1156
----------------------------------
1157
--
1158
-- Arithmetic Logic Unit
1159
--
1160
----------------------------------
1161
 
1162
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
1163
variable valid_lo, valid_hi : boolean;
1164
variable carry_in : std_logic;
1165
variable daa_reg : std_logic_vector(7 downto 0);
1166
begin
1167
 
1168
  case alu_ctrl is
1169
         when alu_adc | alu_sbc |
1170
              alu_rol8 | alu_ror8 =>
1171
           carry_in := cc(CBIT);
1172
    when alu_asr8 =>
1173
           carry_in := left(7);
1174
         when others =>
1175
           carry_in := '0';
1176
  end case;
1177
 
1178
  valid_lo := left(3 downto 0) <= 9;
1179
  valid_hi := left(7 downto 4) <= 9;
1180
 
1181
  if (cc(CBIT) = '0') then
1182
    if( cc(HBIT) = '1' ) then
1183
                if valid_hi then
1184
                  daa_reg := "00000110";
1185
                else
1186
                  daa_reg := "01100110";
1187
           end if;
1188
    else
1189
                if valid_lo then
1190
                  if valid_hi then
1191
                    daa_reg := "00000000";
1192
                  else
1193
                    daa_reg := "01100000";
1194
                  end if;
1195
                else
1196
             if( left(7 downto 4) <= 8 ) then
1197
                    daa_reg := "00000110";
1198
                  else
1199
                         daa_reg := "01100110";
1200
                  end if;
1201
                end if;
1202
         end if;
1203
  else
1204
    if ( cc(HBIT) = '1' )then
1205
                daa_reg := "01100110";
1206
         else
1207
                if valid_lo then
1208
                  daa_reg := "01100000";
1209
           else
1210
                  daa_reg := "01100110";
1211
                end if;
1212
         end if;
1213
  end if;
1214
 
1215
  case alu_ctrl is
1216
         when alu_add8 | alu_inc |
1217
              alu_add16 | alu_adc | alu_mul =>
1218
                out_alu <= left + right + ("000000000000000" & carry_in);
1219
         when alu_sub8 | alu_dec |
1220
              alu_sub16 | alu_sbc =>
1221
           out_alu <= left - right - ("000000000000000" & carry_in);
1222
    when alu_abx =>
1223
           out_alu <= left + ("00000000" & right(7 downto 0)) ;
1224
         when alu_and =>
1225
           out_alu   <= left and right;         -- and/bit
1226
         when alu_ora =>
1227
           out_alu   <= left or right;  -- or
1228
         when alu_eor =>
1229
           out_alu   <= left xor right;         -- eor/xor
1230
         when alu_lsl16 | alu_asl8 | alu_rol8 =>
1231
           out_alu   <= left(14 downto 0) & carry_in;    -- rol8/asl8/lsl16
1232
         when alu_lsr16 =>
1233
           out_alu   <= carry_in & left(15 downto 1);   -- lsr16
1234
         when alu_lsr8 | alu_asr8 | alu_ror8 =>
1235
           out_alu   <= "00000000" & carry_in & left(7 downto 1);       -- ror8/asr8/lsr8
1236
         when alu_neg =>
1237
           out_alu   <= right - left;   -- neg (right=0)
1238
         when alu_com =>
1239
           out_alu   <= not left;
1240
         when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
1241
           out_alu   <= right;           -- clr, ld
1242
         when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
1243
           out_alu   <= left;
1244
         when alu_daa =>
1245
           out_alu   <= left + ("00000000" & daa_reg);
1246
         when alu_sex =>
1247
           if left(7) = '0' then
1248
              out_alu <= "00000000" & left(7 downto 0);
1249
                else
1250
                   out_alu <= "11111111" & left(7 downto 0);
1251
                end if;
1252
         when others =>
1253
           out_alu   <= left; -- nop
1254
    end case;
1255
 
1256
         --
1257
         -- carry bit
1258
         --
1259
    case alu_ctrl is
1260
         when alu_add8 | alu_adc  =>
1261
      cc_out(CBIT) <= (left(7) and right(7)) or
1262
                                (left(7) and not out_alu(7)) or
1263
                                                   (right(7) and not out_alu(7));
1264
         when alu_sub8 | alu_sbc =>
1265
      cc_out(CBIT) <= ((not left(7)) and right(7)) or
1266
                                ((not left(7)) and out_alu(7)) or
1267
                                                         (right(7) and out_alu(7));
1268
         when alu_add16  =>
1269
      cc_out(CBIT) <= (left(15) and right(15)) or
1270
                                (left(15) and not out_alu(15)) or
1271
                                                   (right(15) and not out_alu(15));
1272
         when alu_sub16 =>
1273
      cc_out(CBIT) <= ((not left(15)) and right(15)) or
1274
                                ((not left(15)) and out_alu(15)) or
1275
                                                         (right(15) and out_alu(15));
1276
         when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
1277
           cc_out(CBIT) <= left(0);
1278
         when alu_rol8 | alu_asl8 =>
1279
           cc_out(CBIT) <= left(7);
1280
         when alu_lsl16 =>
1281
           cc_out(CBIT) <= left(15);
1282
         when alu_com =>
1283
           cc_out(CBIT) <= '1';
1284
         when alu_neg | alu_clr =>
1285
           cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
1286
                                out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
1287
    when alu_mul =>
1288
                cc_out(CBIT) <= out_alu(7);
1289
    when alu_daa =>
1290
           if ( daa_reg(7 downto 4) = "0110" ) then
1291
                  cc_out(CBIT) <= '1';
1292
                else
1293
                  cc_out(CBIT) <= '0';
1294
           end if;
1295
         when alu_andcc =>
1296
      cc_out(CBIT) <= left(CBIT) and cc(CBIT);
1297
         when alu_orcc =>
1298
      cc_out(CBIT) <= left(CBIT) or cc(CBIT);
1299
         when alu_tfr =>
1300
      cc_out(CBIT) <= left(CBIT);
1301
         when others =>
1302
      cc_out(CBIT) <= cc(CBIT);
1303
    end case;
1304
         --
1305
         -- Zero flag
1306
         --
1307
    case alu_ctrl is
1308
         when alu_add8 | alu_sub8 |
1309
              alu_adc | alu_sbc |
1310
              alu_and | alu_ora | alu_eor |
1311
              alu_inc | alu_dec |
1312
                        alu_neg | alu_com | alu_clr |
1313
                        alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1314
                   alu_ld8  | alu_st8 | alu_sex | alu_daa =>
1315
      cc_out(ZBIT) <= not( out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
1316
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
1317
         when alu_add16 | alu_sub16 | alu_mul |
1318
              alu_lsl16 | alu_lsr16 |
1319
                   alu_ld16  | alu_st16 | alu_lea =>
1320
      cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
1321
                                out_alu(11) or out_alu(10) or out_alu(9)  or out_alu(8)  or
1322
                                out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
1323
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
1324
         when alu_andcc =>
1325
      cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
1326
         when alu_orcc =>
1327
      cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
1328
         when alu_tfr =>
1329
      cc_out(ZBIT) <= left(ZBIT);
1330
         when others =>
1331
      cc_out(ZBIT) <= cc(ZBIT);
1332
    end case;
1333
 
1334
    --
1335
         -- negative flag
1336
         --
1337
    case alu_ctrl is
1338
         when alu_add8 | alu_sub8 |
1339
              alu_adc | alu_sbc |
1340
              alu_and | alu_ora | alu_eor |
1341
              alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1342
              alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
1343
                        alu_ld8  | alu_st8 | alu_sex | alu_daa =>
1344
      cc_out(NBIT) <= out_alu(7);
1345
         when alu_add16 | alu_sub16 |
1346
              alu_lsl16 | alu_lsr16 |
1347
                        alu_ld16 | alu_st16 =>
1348
                cc_out(NBIT) <= out_alu(15);
1349
         when alu_andcc =>
1350
      cc_out(NBIT) <= left(NBIT) and cc(NBIT);
1351
         when alu_orcc =>
1352
      cc_out(NBIT) <= left(NBIT) or cc(NBIT);
1353
         when alu_tfr =>
1354
      cc_out(NBIT) <= left(NBIT);
1355
         when others =>
1356
      cc_out(NBIT) <= cc(NBIT);
1357
    end case;
1358
 
1359
    --
1360
         -- Interrupt mask flag
1361
    --
1362
    case alu_ctrl is
1363
         when alu_andcc =>
1364
      cc_out(IBIT) <= left(IBIT) and cc(IBIT);
1365
         when alu_orcc =>
1366
      cc_out(IBIT) <= left(IBIT) or cc(IBIT);
1367
         when alu_tfr =>
1368
      cc_out(IBIT) <= left(IBIT);
1369
    when alu_seif | alu_sei =>
1370
           cc_out(IBIT) <= '1';
1371
         when others =>
1372
                cc_out(IBIT) <= cc(IBIT);             -- interrupt mask
1373
    end case;
1374
 
1375
    --
1376
    -- Half Carry flag
1377
         --
1378
    case alu_ctrl is
1379
         when alu_add8 | alu_adc =>
1380
      cc_out(HBIT) <= (left(3) and right(3)) or
1381
                     (right(3) and not out_alu(3)) or
1382
                      (left(3) and not out_alu(3));
1383
         when alu_andcc =>
1384
      cc_out(HBIT) <= left(HBIT) and cc(HBIT);
1385
         when alu_orcc =>
1386
      cc_out(HBIT) <= left(HBIT) or cc(HBIT);
1387
         when alu_tfr =>
1388
      cc_out(HBIT) <= left(HBIT);
1389
         when others =>
1390
                cc_out(HBIT) <= cc(HBIT);
1391
    end case;
1392
 
1393
    --
1394
    -- Overflow flag
1395
         --
1396
    case alu_ctrl is
1397
         when alu_add8 | alu_adc =>
1398
      cc_out(VBIT) <= (left(7)  and      right(7)  and (not out_alu(7))) or
1399
                 ((not left(7)) and (not right(7)) and      out_alu(7));
1400
         when alu_sub8 | alu_sbc =>
1401
      cc_out(VBIT) <= (left(7)  and (not right(7)) and (not out_alu(7))) or
1402
                 ((not left(7)) and      right(7)  and      out_alu(7));
1403
         when alu_add16 =>
1404
      cc_out(VBIT) <= (left(15)  and      right(15)  and (not out_alu(15))) or
1405
                 ((not left(15)) and (not right(15)) and      out_alu(15));
1406
         when alu_sub16 =>
1407
      cc_out(VBIT) <= (left(15)  and (not right(15)) and (not out_alu(15))) or
1408
                 ((not left(15)) and      right(15) and       out_alu(15));
1409
         when alu_inc =>
1410
           cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
1411
                                      left(3)  and left(2) and left(1) and left(0));
1412
         when alu_dec | alu_neg =>
1413
           cc_out(VBIT) <= (left(7)  and (not left(6)) and (not left(5)) and (not left(4)) and
1414
                            (not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
1415
-- 6809 Programming reference manual says
1416
-- V not affected by ASR, LSR and ROR
1417
-- This is different to the 6800
1418
-- John Kent 6th June 2006
1419
--       when alu_asr8 =>
1420
--         cc_out(VBIT) <= left(0) xor left(7);
1421
--       when alu_lsr8 | alu_lsr16 =>
1422
--         cc_out(VBIT) <= left(0);
1423
--       when alu_ror8 =>
1424
--      cc_out(VBIT) <= left(0) xor cc(CBIT);
1425
    when alu_lsl16 =>
1426
      cc_out(VBIT) <= left(15) xor left(14);
1427
         when alu_rol8 | alu_asl8 =>
1428
      cc_out(VBIT) <= left(7) xor left(6);
1429
--
1430
-- 11th July 2006 - John Kent
1431
-- What DAA does with V is anyones guess
1432
-- It is undefined in the 6809 programming manual
1433
--
1434
         when alu_daa =>
1435
      cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
1436
-- CLR resets V Bit
1437
-- John Kent 6th June 2006
1438
         when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
1439
              alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
1440
      cc_out(VBIT) <= '0';
1441
         when alu_andcc =>
1442
      cc_out(VBIT) <= left(VBIT) and cc(VBIT);
1443
         when alu_orcc =>
1444
      cc_out(VBIT) <= left(VBIT) or cc(VBIT);
1445
         when alu_tfr =>
1446
      cc_out(VBIT) <= left(VBIT);
1447
         when others =>
1448
                cc_out(VBIT) <= cc(VBIT);
1449
    end case;
1450
 
1451
         case alu_ctrl is
1452
         when alu_andcc =>
1453
      cc_out(FBIT) <= left(FBIT) and cc(FBIT);
1454
         when alu_orcc =>
1455
      cc_out(FBIT) <= left(FBIT) or cc(FBIT);
1456
         when alu_tfr =>
1457
      cc_out(FBIT) <= left(FBIT);
1458
    when alu_seif =>
1459
           cc_out(FBIT) <= '1';
1460
         when others =>
1461
      cc_out(FBIT) <= cc(FBIT);
1462
         end case;
1463
 
1464
         case alu_ctrl is
1465
         when alu_andcc =>
1466
      cc_out(EBIT) <= left(EBIT) and cc(EBIT);
1467
         when alu_orcc =>
1468
      cc_out(EBIT) <= left(EBIT) or cc(EBIT);
1469
         when alu_tfr =>
1470
      cc_out(EBIT) <= left(EBIT);
1471
    when alu_see =>
1472
           cc_out(EBIT) <= '1';
1473
    when alu_cle =>
1474
           cc_out(EBIT) <= '0';
1475
         when others =>
1476
           cc_out(EBIT) <= cc(EBIT);
1477
         end case;
1478
end process;
1479
 
1480
------------------------------------
1481
--
1482
-- state sequencer
1483
--
1484
------------------------------------
1485
process( state, saved_state,
1486
         op_code, pre_code,
1487
                        cc, ea, md, iv,
1488
                        irq, firq, nmi_req, nmi_ack, halt )
1489
variable cond_true : boolean;  -- variable used to evaluate coditional branches
1490
begin
1491
        ba         <= '0';
1492
        bs         <= '0';
1493
        lic        <= '0';
1494
        -- Registers preserved
1495
        cc_ctrl    <= latch_cc;
1496
        acca_ctrl  <= latch_acca;
1497
        accb_ctrl  <= latch_accb;
1498
        dp_ctrl    <= latch_dp;
1499
        ix_ctrl    <= latch_ix;
1500
        iy_ctrl    <= latch_iy;
1501
        up_ctrl    <= latch_up;
1502
        sp_ctrl    <= latch_sp;
1503
        pc_ctrl    <= latch_pc;
1504
        md_ctrl    <= latch_md;
1505
        ea_ctrl    <= latch_ea;
1506
        iv_ctrl    <= latch_iv;
1507
        op_ctrl    <= latch_op;
1508
        pre_ctrl   <= latch_pre;
1509
        nmi_ctrl   <= latch_nmi;
1510
                  -- ALU Idle
1511
        left_ctrl  <= pc_left;
1512
        right_ctrl <= zero_right;
1513
        alu_ctrl   <= alu_nop;
1514
                  -- Bus idle
1515
        addr_ctrl  <= idle_ad;
1516
        dout_ctrl  <= cc_dout;
1517
                  -- Next State Fetch
1518
        st_ctrl      <= idle_st;
1519
        return_state <= fetch_state;
1520
        next_state   <= fetch_state;
1521
 
1522
                    case state is
1523
          when reset_state =>        --  released from reset
1524
                            -- reset the registers
1525
             op_ctrl    <= reset_op;
1526
             pre_ctrl   <= reset_pre;
1527
             cc_ctrl    <= reset_cc;
1528
                                 acca_ctrl  <= reset_acca;
1529
                                 accb_ctrl  <= reset_accb;
1530
             dp_ctrl    <= reset_dp;
1531
                                 ix_ctrl    <= reset_ix;
1532
                                 iy_ctrl    <= reset_iy;
1533
                       up_ctrl    <= reset_up;
1534
                       sp_ctrl    <= reset_sp;
1535
                       pc_ctrl    <= reset_pc;
1536
                            ea_ctrl    <= reset_ea;
1537
                                 md_ctrl    <= reset_md;
1538
                                 iv_ctrl    <= reset_iv;
1539
                                 nmi_ctrl   <= reset_nmi;
1540
                       next_state <= vect_hi_state;
1541
 
1542
                         --
1543
                         -- Jump via interrupt vector
1544
                         -- iv holds interrupt type
1545
                         -- fetch PC hi from vector location
1546
                         --
1547
          when vect_hi_state =>
1548
                                 -- fetch pc low interrupt vector
1549
                       pc_ctrl    <= pull_hi_pc;
1550
             addr_ctrl  <= int_hi_ad;
1551
             bs         <= '1';
1552
                       next_state <= vect_lo_state;
1553
                         --
1554
                         -- jump via interrupt vector
1555
                         -- iv holds vector type
1556
                         -- fetch PC lo from vector location
1557
                         --
1558
          when vect_lo_state =>
1559
                                 -- fetch the vector low byte
1560
                       pc_ctrl    <= pull_lo_pc;
1561
             addr_ctrl  <= int_lo_ad;
1562
             bs         <= '1';
1563
                       next_state <= fetch_state;
1564
                         --
1565
                         -- Here to fetch an instruction
1566
                         -- PC points to opcode
1567
                         -- Should service interrupt requests at this point
1568
                         -- either from the timer
1569
                         -- or from the external input.
1570
                         --
1571
          when fetch_state =>
1572
                                   -- fetch the op code
1573
                              op_ctrl    <= fetch_op;
1574
               pre_ctrl   <= fetch_pre;
1575
               ea_ctrl    <= reset_ea;
1576
                                   -- Fetch op code
1577
               addr_ctrl  <= fetch_ad;
1578
                                   --
1579
                                        case op_code(7 downto 6) is
1580
                                        when "10" => -- acca
1581
                                     case op_code(3 downto 0) is
1582
                                          when "0000" => -- suba
1583
                                            left_ctrl  <= acca_left;
1584
                                            right_ctrl <= md_right;
1585
                                            alu_ctrl   <= alu_sub8;
1586
                                                 cc_ctrl    <= load_cc;
1587
                                            acca_ctrl  <= load_acca;
1588
                                          when "0001" => -- cmpa
1589
                                            left_ctrl   <= acca_left;
1590
                                            right_ctrl  <= md_right;
1591
                                            alu_ctrl    <= alu_sub8;
1592
                                                 cc_ctrl     <= load_cc;
1593
                                          when "0010" => -- sbca
1594
                                            left_ctrl   <= acca_left;
1595
                                            right_ctrl  <= md_right;
1596
                                            alu_ctrl    <= alu_sbc;
1597
                                                 cc_ctrl     <= load_cc;
1598
                                            acca_ctrl   <= load_acca;
1599
                                          when "0011" =>
1600
                                            case pre_code is
1601
                                                 when "00010000" => -- page 2 -- cmpd
1602
                                              left_ctrl   <= accd_left;
1603
                                              right_ctrl  <= md_right;
1604
                                              alu_ctrl    <= alu_sub16;
1605
                                                   cc_ctrl     <= load_cc;
1606
                                                 when "00010001" => -- page 3 -- cmpu
1607
                                              left_ctrl   <= up_left;
1608
                                              right_ctrl  <= md_right;
1609
                                              alu_ctrl    <= alu_sub16;
1610
                                                   cc_ctrl     <= load_cc;
1611
                                                 when others => -- page 1 -- subd
1612
                                              left_ctrl   <= accd_left;
1613
                                              right_ctrl  <= md_right;
1614
                                              alu_ctrl    <= alu_sub16;
1615
                                                   cc_ctrl     <= load_cc;
1616
                                              acca_ctrl   <= load_hi_acca;
1617
                                                   accb_ctrl   <= load_accb;
1618
                                                 end case;
1619
                                          when "0100" => -- anda
1620
                                            left_ctrl   <= acca_left;
1621
                                            right_ctrl  <= md_right;
1622
                                            alu_ctrl    <= alu_and;
1623
                                                 cc_ctrl     <= load_cc;
1624
                                            acca_ctrl   <= load_acca;
1625
                                          when "0101" => -- bita
1626
                                            left_ctrl   <= acca_left;
1627
                                            right_ctrl  <= md_right;
1628
                                            alu_ctrl    <= alu_and;
1629
                                                 cc_ctrl     <= load_cc;
1630
                                          when "0110" => -- ldaa
1631
                                            left_ctrl   <= acca_left;
1632
                                            right_ctrl  <= md_right;
1633
                                            alu_ctrl    <= alu_ld8;
1634
                                                 cc_ctrl     <= load_cc;
1635
                                            acca_ctrl   <= load_acca;
1636
                                          when "0111" => -- staa
1637
                                            left_ctrl   <= acca_left;
1638
                                            right_ctrl  <= md_right;
1639
                                            alu_ctrl    <= alu_st8;
1640
                                                 cc_ctrl     <= load_cc;
1641
                                          when "1000" => -- eora
1642
                                            left_ctrl   <= acca_left;
1643
                                            right_ctrl  <= md_right;
1644
                                            alu_ctrl    <= alu_eor;
1645
                                                 cc_ctrl     <= load_cc;
1646
                                            acca_ctrl   <= load_acca;
1647
                                          when "1001" => -- adca
1648
                                            left_ctrl   <= acca_left;
1649
                                            right_ctrl  <= md_right;
1650
                                            alu_ctrl    <= alu_adc;
1651
                                                 cc_ctrl     <= load_cc;
1652
                                            acca_ctrl   <= load_acca;
1653
                                          when "1010" => -- oraa
1654
                                            left_ctrl   <= acca_left;
1655
                                            right_ctrl  <= md_right;
1656
                                            alu_ctrl    <= alu_ora;
1657
                                                 cc_ctrl     <= load_cc;
1658
                                            acca_ctrl   <= load_acca;
1659
                                          when "1011" => -- adda
1660
                                            left_ctrl   <= acca_left;
1661
                                            right_ctrl  <= md_right;
1662
                                            alu_ctrl    <= alu_add8;
1663
                                                 cc_ctrl     <= load_cc;
1664
                                            acca_ctrl   <= load_acca;
1665
                                          when "1100" =>
1666
                                            case pre_code is
1667
                                                 when "00010000" => -- page 2 -- cmpy
1668
                                              left_ctrl   <= iy_left;
1669
                                              right_ctrl  <= md_right;
1670
                                              alu_ctrl    <= alu_sub16;
1671
                                                   cc_ctrl     <= load_cc;
1672
                                                 when "00010001" => -- page 3 -- cmps
1673
                                              left_ctrl   <= sp_left;
1674
                                              right_ctrl  <= md_right;
1675
                                              alu_ctrl    <= alu_sub16;
1676
                                                   cc_ctrl     <= load_cc;
1677
                                                 when others => -- page 1 -- cmpx
1678
                                              left_ctrl   <= ix_left;
1679
                                              right_ctrl  <= md_right;
1680
                                              alu_ctrl    <= alu_sub16;
1681
                                                   cc_ctrl     <= load_cc;
1682
                                                 end case;
1683
                                          when "1101" => -- bsr / jsr
1684
                                            null;
1685
                                          when "1110" => -- ldx
1686
                                            case pre_code is
1687
                                                 when "00010000" => -- page 2 -- ldy
1688
                                              left_ctrl   <= iy_left;
1689
                                              right_ctrl  <= md_right;
1690
                                              alu_ctrl    <= alu_ld16;
1691
                                                   cc_ctrl     <= load_cc;
1692
                     iy_ctrl     <= load_iy;
1693
                                                 when others =>   -- page 1 -- ldx
1694
                                              left_ctrl   <= ix_left;
1695
                                              right_ctrl  <= md_right;
1696
                                              alu_ctrl    <= alu_ld16;
1697
                                                   cc_ctrl     <= load_cc;
1698
                     ix_ctrl     <= load_ix;
1699
                                                 end case;
1700
                                          when "1111" => -- stx
1701
                                            case pre_code is
1702
                                                 when "00010000" => -- page 2 -- sty
1703
                                              left_ctrl   <= iy_left;
1704
                                              right_ctrl  <= md_right;
1705
                                              alu_ctrl    <= alu_st16;
1706
                                                   cc_ctrl     <= load_cc;
1707
                                                 when others =>     -- page 1 -- stx
1708
                                              left_ctrl   <= ix_left;
1709
                                              right_ctrl  <= md_right;
1710
                                              alu_ctrl    <= alu_st16;
1711
                                                   cc_ctrl     <= load_cc;
1712
                                                 end case;
1713
                                          when others =>
1714
                                            null;
1715
                                          end case;
1716
                                        when "11" => -- accb dual op
1717
                                     case op_code(3 downto 0) is
1718
                                          when "0000" => -- subb
1719
                                            left_ctrl   <= accb_left;
1720
                                            right_ctrl  <= md_right;
1721
                                            alu_ctrl    <= alu_sub8;
1722
                                                 cc_ctrl     <= load_cc;
1723
                   accb_ctrl   <= load_accb;
1724
                                          when "0001" => -- cmpb
1725
                                            left_ctrl   <= accb_left;
1726
                                            right_ctrl  <= md_right;
1727
                                            alu_ctrl    <= alu_sub8;
1728
                                                 cc_ctrl     <= load_cc;
1729
                                          when "0010" => -- sbcb
1730
                                            left_ctrl   <= accb_left;
1731
                                            right_ctrl  <= md_right;
1732
                                            alu_ctrl    <= alu_sbc;
1733
                                                 cc_ctrl     <= load_cc;
1734
                   accb_ctrl   <= load_accb;
1735
                                          when "0011" => -- addd
1736
                                            left_ctrl   <= accd_left;
1737
                                            right_ctrl  <= md_right;
1738
                                            alu_ctrl    <= alu_add16;
1739
                                                 cc_ctrl     <= load_cc;
1740
                                            acca_ctrl   <= load_hi_acca;
1741
                                                 accb_ctrl   <= load_accb;
1742
                                          when "0100" => -- andb
1743
                                            left_ctrl   <= accb_left;
1744
                                            right_ctrl  <= md_right;
1745
                                            alu_ctrl    <= alu_and;
1746
                                                 cc_ctrl     <= load_cc;
1747
                   accb_ctrl   <= load_accb;
1748
                                          when "0101" => -- bitb
1749
                                            left_ctrl   <= accb_left;
1750
                                            right_ctrl  <= md_right;
1751
                                            alu_ctrl    <= alu_and;
1752
                                                 cc_ctrl     <= load_cc;
1753
                                          when "0110" => -- ldab
1754
                                            left_ctrl   <= accb_left;
1755
                                            right_ctrl  <= md_right;
1756
                                            alu_ctrl    <= alu_ld8;
1757
                                                 cc_ctrl     <= load_cc;
1758
                   accb_ctrl   <= load_accb;
1759
                                          when "0111" => -- stab
1760
                                            left_ctrl   <= accb_left;
1761
                                            right_ctrl  <= md_right;
1762
                                            alu_ctrl    <= alu_st8;
1763
                                                 cc_ctrl     <= load_cc;
1764
                                          when "1000" => -- eorb
1765
                                            left_ctrl   <= accb_left;
1766
                                            right_ctrl  <= md_right;
1767
                                            alu_ctrl    <= alu_eor;
1768
                                                 cc_ctrl     <= load_cc;
1769
                   accb_ctrl   <= load_accb;
1770
                                          when "1001" => -- adcb
1771
                                            left_ctrl   <= accb_left;
1772
                                            right_ctrl  <= md_right;
1773
                                            alu_ctrl    <= alu_adc;
1774
                                                 cc_ctrl     <= load_cc;
1775
                   accb_ctrl   <= load_accb;
1776
                                          when "1010" => -- orab
1777
                                            left_ctrl   <= accb_left;
1778
                                            right_ctrl  <= md_right;
1779
                                            alu_ctrl    <= alu_ora;
1780
                                                 cc_ctrl     <= load_cc;
1781
                   accb_ctrl   <= load_accb;
1782
                                          when "1011" => -- addb
1783
                                            left_ctrl   <= accb_left;
1784
                                            right_ctrl  <= md_right;
1785
                                            alu_ctrl    <= alu_add8;
1786
                                                 cc_ctrl     <= load_cc;
1787
                   accb_ctrl   <= load_accb;
1788
                                          when "1100" => -- ldd
1789
                                            left_ctrl   <= accd_left;
1790
                                            right_ctrl  <= md_right;
1791
                                            alu_ctrl    <= alu_ld16;
1792
                                                 cc_ctrl     <= load_cc;
1793
                                            acca_ctrl   <= load_hi_acca;
1794
                   accb_ctrl   <= load_accb;
1795
                                          when "1101" => -- std
1796
                                            left_ctrl   <= accd_left;
1797
                                            right_ctrl  <= md_right;
1798
                                            alu_ctrl    <= alu_st16;
1799
                                                 cc_ctrl     <= load_cc;
1800
                                          when "1110" => -- ldu
1801
                                            case pre_code is
1802
                                                 when "00010000" => -- page 2 -- lds
1803
                                              left_ctrl   <= sp_left;
1804
                                              right_ctrl  <= md_right;
1805
                                              alu_ctrl    <= alu_ld16;
1806
                                                   cc_ctrl     <= load_cc;
1807
                                                   sp_ctrl     <= load_sp;
1808
                                                 when others => -- page 1 -- ldu
1809
                                              left_ctrl   <= up_left;
1810
                                              right_ctrl  <= md_right;
1811
                                              alu_ctrl    <= alu_ld16;
1812
                                                   cc_ctrl     <= load_cc;
1813
                     up_ctrl     <= load_up;
1814
                                                 end case;
1815
                                          when "1111" =>
1816
                                            case pre_code is
1817
                                                 when "00010000" => -- page 2 -- sts
1818
                                              left_ctrl   <= sp_left;
1819
                                              right_ctrl  <= md_right;
1820
                                              alu_ctrl    <= alu_st16;
1821
                                                   cc_ctrl     <= load_cc;
1822
                                                 when others =>     -- page 1 -- stu
1823
                                              left_ctrl   <= up_left;
1824
                                              right_ctrl  <= md_right;
1825
                                              alu_ctrl    <= alu_st16;
1826
                                                   cc_ctrl     <= load_cc;
1827
                                                 end case;
1828
                                          when others =>
1829
                                            null;
1830
                                          end case;
1831
                                        when others =>
1832
                                          null;
1833
                                        end case;
1834
                                 if halt = '1' then
1835
                              iv_ctrl    <= reset_iv;
1836
                              next_state <= halt_state;
1837
                                 -- service non maskable interrupts
1838
                            elsif (nmi_req = '1') and (nmi_ack = '0') then
1839
                              iv_ctrl    <= nmi_iv;
1840
                                   nmi_ctrl   <= set_nmi;
1841
                              next_state <= int_nmiirq_state;
1842
                                 -- service maskable interrupts
1843
                            else
1844
                                   --
1845
                                        -- nmi request is not cleared until nmi input goes low
1846
                                        --
1847
                                   if(nmi_req = '0') and (nmi_ack='1') then
1848
                                     nmi_ctrl <= reset_nmi;
1849
                                        end if;
1850
                                        --
1851
                                        -- FIRQ & IRQ are level sensitive
1852
                                        --
1853
               if (firq = '1') and (cc(FBIT) = '0') then
1854
                                iv_ctrl    <= firq_iv;
1855
                                next_state <= int_firq_state;
1856
                                   elsif (irq = '1') and (cc(IBIT) = '0') then
1857
                                iv_ctrl    <= irq_iv;
1858
                                next_state <= int_nmiirq_state;
1859
               else
1860
                                     -- Advance the PC to fetch next instruction byte
1861
                                iv_ctrl    <= reset_iv; -- default to reset
1862
                 pc_ctrl    <= incr_pc;
1863
                                next_state <= decode1_state;
1864
               end if;
1865
                                 end if;
1866
                          --
1867
                          -- Here to decode instruction
1868
                          -- and fetch next byte of intruction
1869
                          -- whether it be necessary or not
1870
                          --
1871
           when decode1_state =>
1872
                                 -- fetch first byte of address or immediate data
1873
             ea_ctrl    <= fetch_first_ea;
1874
                                 md_ctrl    <= fetch_first_md;
1875
             addr_ctrl  <= fetch_ad;
1876
                            case op_code(7 downto 4) is
1877
                                 --
1878
                                 -- direct single op (2 bytes)
1879
                                 -- 6809 => 6 cycles
1880
                                 -- cpu09 => 5 cycles
1881
                            -- 1 op=(pc) / pc=pc+1
1882
                                 -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
1883
                                 -- 3 md_lo=(ea) / pc=pc
1884
                                 -- 4 alu_left=md / md=alu_out / pc=pc
1885
                                 -- 5 (ea)=md_lo / pc=pc
1886
                                 --
1887
                                 -- Exception is JMP
1888
                            -- 6809 => 3 cycles
1889
                                 -- cpu09 => 3 cycles
1890
                                 -- 1 op=(pc) / pc=pc+1
1891
                                 -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
1892
                                 -- 3 pc=ea
1893
                                 --
1894
                  when "0000" =>
1895
                                        -- advance the PC
1896
               pc_ctrl    <= incr_pc;
1897
                                        case op_code(3 downto 0) is
1898
                                   when "1110" => -- jmp
1899
                                     next_state <= jmp_state;
1900
                                        when "1111" => -- clr
1901
                                     next_state <= single_op_exec_state;
1902
                                        when others =>
1903
                                     next_state <= single_op_read_state;
1904
                                        end case;
1905
 
1906
                                 -- acca / accb inherent instructions
1907
                  when "0001" =>
1908
                    case op_code(3 downto 0) is
1909
                                        --
1910
                                        -- Page2 pre byte
1911
                                        -- pre=(pc) / pc=pc+1
1912
                                        -- op=(pc) / pc=pc+1
1913
                                        --
1914
                         when "0000" => -- page2
1915
                                op_ctrl    <= fetch_op;
1916
                                          -- advance pc
1917
                 pc_ctrl    <= incr_pc;
1918
                                          next_state <= decode2_state;
1919
 
1920
                                        --
1921
                                        -- Page3 pre byte
1922
                                        -- pre=(pc) / pc=pc+1
1923
                                        -- op=(pc) / pc=pc+1
1924
                                        --
1925
                         when "0001" => -- page3
1926
                                op_ctrl    <= fetch_op;
1927
                                          -- advance pc
1928
                 pc_ctrl    <= incr_pc;
1929
                                          next_state <= decode3_state;
1930
 
1931
                                        --
1932
                                        -- nop - No operation ( 1 byte )
1933
                                        -- 6809 => 2 cycles
1934
                                        -- cpu09 => 2 cycles
1935
                                        -- 1 op=(pc) / pc=pc+1
1936
                                        -- 2 decode
1937
                                        -- 
1938
                         when "0010" => -- nop
1939
                 lic          <= '1';
1940
                                          next_state   <= fetch_state;
1941
 
1942
                                        --
1943
                                        -- sync - halt execution until an interrupt is received
1944
                                        -- interrupt may be NMI, IRQ or FIRQ
1945
                                        -- program execution continues if the 
1946
                                        -- interrupt is asserted for 3 clock cycles
1947
                                        -- note that registers are not pushed onto the stack
1948
                                        -- CPU09 => Interrupts need only be asserted for one clock cycle
1949
                                        --
1950
                         when "0011" => -- sync
1951
                                          next_state   <= sync_state;
1952
 
1953
                                        --
1954
                                        -- lbra -- long branch (3 bytes)
1955
                                        -- 6809 => 5 cycles
1956
                                        -- cpu09 => 4 cycles
1957
                                        -- 1 op=(pc) / pc=pc+1
1958
                                        -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
1959
                                        -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
1960
                                        -- 4 pc=pc+md
1961
                                        --
1962
                         when "0110" =>
1963
                                          -- increment the pc
1964
                 pc_ctrl    <= incr_pc;
1965
                                          next_state <= lbranch_state;
1966
 
1967
                                        --
1968
                                        -- lbsr - long branch to subroutine (3 bytes)
1969
                                        -- 6809 => 9 cycles
1970
                                        -- cpu09 => 6 cycles
1971
                                        -- 1 op=(pc) /pc=pc+1
1972
                                        -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
1973
                                        -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
1974
                                        -- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
1975
                                        -- 5 (sp)=pc_hi / pc=pc
1976
                                        -- 6 pc=pc+md
1977
                                        --
1978
                         when "0111" =>
1979
                                          -- pre decrement sp
1980
                 left_ctrl  <= sp_left;
1981
                 right_ctrl <= one_right;
1982
                 alu_ctrl   <= alu_sub16;
1983
                 sp_ctrl    <= load_sp;
1984
                                          -- increment the pc
1985
                 pc_ctrl    <= incr_pc;
1986
                                          next_state <= lbranch_state;
1987
 
1988
                         when "1001" => -- daa
1989
                                          left_ctrl  <= acca_left;
1990
                      right_ctrl <= accb_right;
1991
                                          alu_ctrl   <= alu_daa;
1992
                 cc_ctrl    <= load_cc;
1993
                                          acca_ctrl  <= load_acca;
1994
                 lic        <= '1';
1995
                                          next_state <= fetch_state;
1996
 
1997
                         when "1010" => -- orcc
1998
                                          -- increment the pc
1999
                 pc_ctrl      <= incr_pc;
2000
                                     st_ctrl      <= push_st;
2001
                                     return_state <= fetch_state;
2002
                                          next_state   <= orcc_state;
2003
 
2004
                         when "1100" => -- andcc
2005
                                          -- increment the pc
2006
                 pc_ctrl      <= incr_pc;
2007
                                     st_ctrl      <= push_st;
2008
                                     return_state <= fetch_state;
2009
                                          next_state   <= andcc_state;
2010
 
2011
                         when "1101" => -- sex
2012
                                          -- have sex
2013
                 left_ctrl  <= accb_left;
2014
                 right_ctrl <= zero_right;
2015
                 alu_ctrl   <= alu_sex;
2016
                                          cc_ctrl    <= load_cc;
2017
                                          acca_ctrl  <= load_hi_acca;
2018
                 lic        <= '1';
2019
                                          next_state <= fetch_state;
2020
 
2021
                         when "1110" => -- exg
2022
                                          -- increment the pc
2023
                 pc_ctrl    <= incr_pc;
2024
                                          next_state <= exg_state;
2025
 
2026
                         when "1111" => -- tfr
2027
                                          -- increment the pc
2028
                 pc_ctrl      <= incr_pc;
2029
                                          -- call transfer as a subroutine
2030
                                     st_ctrl      <= push_st;
2031
                                     return_state <= fetch_state;
2032
                                          next_state   <= tfr_state;
2033
 
2034
                         when others =>
2035
                                          -- increment the pc
2036
                 pc_ctrl    <= incr_pc;
2037
                 lic        <= '1';
2038
                                          next_state <= fetch_state;
2039
                         end case;
2040
             --
2041
                                 -- Short branch conditional
2042
                                 -- 6809 => always 3 cycles
2043
                                 -- cpu09 => always = 3 cycles
2044
                                 -- 1 op=(pc) / pc=pc+1
2045
                                 -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
2046
                                 -- 3 if cc tru pc=pc+md else pc=pc
2047
                                 --
2048
                  when "0010" => -- branch conditional
2049
                                        -- increment the pc
2050
               pc_ctrl    <= incr_pc;
2051
               next_state <= sbranch_state;
2052
                                 --
2053
                                 -- Single byte stack operators
2054
                                 -- Do not advance PC
2055
                                 --
2056
                  when "0011" =>
2057
                                        --
2058
                                        -- lea - load effective address (2+ bytes)
2059
                                        -- 6809 => 4 cycles + addressing mode
2060
                                        -- cpu09 => 4 cycles + addressing mode
2061
                                        -- 1 op=(pc) / pc=pc+1
2062
                                        -- 2 md_lo=(pc) / pc=pc+1
2063
                                        -- 3 calculate ea
2064
                                        -- 4 ix/iy/sp/up = ea
2065
                                        --
2066
                    case op_code(3 downto 0) is
2067
                         when "0000" |  -- leax
2068
                              "0001" |  -- leay
2069
                              "0010" |  -- leas
2070
                              "0011" => -- leau
2071
                                                -- advance PC
2072
                  pc_ctrl      <= incr_pc;
2073
                                      st_ctrl      <= push_st;
2074
                                      return_state <= lea_state;
2075
                                                next_state   <= indexed_state;
2076
 
2077
                                        --
2078
                                        -- pshs - push registers onto sp stack
2079
                                        -- 6809 => 5 cycles + registers
2080
                                        -- cpu09 => 3 cycles + registers
2081
                                        --  1 op=(pc) / pc=pc+1
2082
                                        --  2 ea_lo=(pc) / pc=pc+1 
2083
                                        --  3 if ea(7 downto 0) != "00000000" then sp=sp-1
2084
                                        --  4 if ea(7) = 1 (sp)=pcl, sp=sp-1
2085
                                        --  5 if ea(7) = 1 (sp)=pch
2086
                                        --    if ea(6 downto 0) != "0000000" then sp=sp-1
2087
                                        --  6 if ea(6) = 1 (sp)=upl, sp=sp-1
2088
                                        --  7 if ea(6) = 1 (sp)=uph
2089
                                        --    if ea(5 downto 0) != "000000" then sp=sp-1
2090
                                        --  8 if ea(5) = 1 (sp)=iyl, sp=sp-1
2091
                                        --  9 if ea(5) = 1 (sp)=iyh
2092
                                        --    if ea(4 downto 0) != "00000" then sp=sp-1
2093
                                        -- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
2094
                                        -- 11 if ea(4) = 1 (sp)=ixh
2095
                                        --    if ea(3 downto 0) != "0000" then sp=sp-1
2096
                                        -- 12 if ea(3) = 1 (sp)=dp
2097
                                        --    if ea(2 downto 0) != "000" then sp=sp-1
2098
                                        -- 13 if ea(2) = 1 (sp)=accb
2099
                                        --    if ea(1 downto 0) != "00" then sp=sp-1
2100
                                        -- 14 if ea(1) = 1 (sp)=acca
2101
                                        --    if ea(0 downto 0) != "0" then sp=sp-1
2102
                                        -- 15 if ea(0) = 1 (sp)=cc
2103
                                        --
2104
                         when "0100" => -- pshs
2105
                                                -- advance PC
2106
                  pc_ctrl    <= incr_pc;
2107
                                                next_state <= pshs_state;
2108
 
2109
                                        --
2110
                                        -- puls - pull registers of sp stack
2111
                                        -- 6809 => 5 cycles + registers
2112
                                        -- cpu09 => 3 cycles + registers
2113
                                        --
2114
                         when "0101" => -- puls
2115
                                                -- advance PC
2116
                  pc_ctrl    <= incr_pc;
2117
                                                next_state <= puls_state;
2118
 
2119
                                        --
2120
                                        -- pshu - push registers onto up stack
2121
                                        -- 6809 => 5 cycles + registers
2122
                                        -- cpu09 => 3 cycles + registers
2123
                                        --
2124
                         when "0110" => -- pshu
2125
                                                -- advance PC
2126
                  pc_ctrl    <= incr_pc;
2127
                                                next_state <= pshu_state;
2128
 
2129
                                        --
2130
                                        -- pulu - pull registers of up stack
2131
                                        -- 6809 => 5 cycles + registers
2132
                                        -- cpu09 => 3 cycles + registers
2133
                                        --
2134
                         when "0111" => -- pulu
2135
                                                -- advance PC
2136
                  pc_ctrl    <= incr_pc;
2137
                                                next_state <= pulu_state;
2138
 
2139
                                        --
2140
                                        -- rts - return from subroutine
2141
                                        -- 6809 => 5 cycles
2142
                                        -- cpu09 => 4 cycles 
2143
                                        -- 1 op=(pc) / pc=pc+1
2144
                                        -- 2 decode op
2145
                                        -- 3 pc_hi = (sp) / sp=sp+1
2146
                                        -- 4 pc_lo = (sp) / sp=sp+1
2147
                                        --
2148
                         when "1001" =>
2149
                                      st_ctrl      <= push_st;
2150
                                      return_state <= fetch_state;
2151
                                                next_state   <= pull_return_hi_state;
2152
 
2153
                                        --
2154
                                        -- add accb to index register
2155
                                        -- *** Note: this is an unsigned addition.
2156
                                        --           does not affect any condition codes
2157
                                        -- 6809 => 3 cycles
2158
                                        -- cpu09 => 2 cycles
2159
                                        -- 1 op=(pc) / pc=pc+1
2160
                                        -- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
2161
                                        --
2162
                         when "1010" => -- abx
2163
                            left_ctrl  <= ix_left;
2164
                            right_ctrl <= accb_right;
2165
                                                alu_ctrl   <= alu_abx;
2166
                                                ix_ctrl    <= load_ix;
2167
                  lic        <= '1';
2168
                                                next_state <= fetch_state;
2169
 
2170
                         when "1011" => -- rti
2171
                                                next_state <= rti_cc_state;
2172
 
2173
                         when "1100" => -- cwai #$<cc_mask>
2174
                                           -- pre decrement sp
2175
                            left_ctrl    <= sp_left;
2176
                            right_ctrl   <= one_right;
2177
                                                alu_ctrl     <= alu_sub16;
2178
                                                sp_ctrl      <= load_sp;
2179
                  iv_ctrl      <= reset_iv;
2180
                                                --      increment pc
2181
                  pc_ctrl      <= incr_pc;
2182
                                      st_ctrl      <= push_st;
2183
                                      return_state <= int_entire_state; -- set entire flag
2184
                                                next_state   <= andcc_state;
2185
 
2186
                         when "1101" => -- mul
2187
                                                next_state <= mul_state;
2188
 
2189
                         when "1111" => -- swi
2190
                                           -- predecrement SP
2191
                            left_ctrl  <= sp_left;
2192
                            right_ctrl <= one_right;
2193
                                                alu_ctrl   <= alu_sub16;
2194
                                                sp_ctrl    <= load_sp;
2195
                  iv_ctrl    <= swi_iv;
2196
                                                next_state <= int_entire_state;
2197
 
2198
                         when others =>
2199
                  lic        <= '1';
2200
                                                next_state <= fetch_state;
2201
 
2202
                         end case;
2203
                                 --
2204
                                 -- Accumulator A Single operand
2205
                                 -- source = acca, dest = acca
2206
                                 -- Do not advance PC
2207
                                 -- Typically 2 cycles 1 bytes
2208
                                 -- 1 opcode fetch
2209
                                 -- 2 post byte fetch / instruction decode
2210
                                 -- Note that there is no post byte
2211
                                 -- so do not advance PC in decode cycle
2212
                                 -- Re-run opcode fetch cycle after decode
2213
                                 -- 
2214
                  when "0100" => -- acca single op
2215
                         left_ctrl  <= acca_left;
2216
                    case op_code(3 downto 0) is
2217
                         when "0000" => -- neg
2218
                                          right_ctrl <= zero_right;
2219
                                          alu_ctrl   <= alu_neg;
2220
                                          acca_ctrl  <= load_acca;
2221
                                          cc_ctrl    <= load_cc;
2222
                    when "0011" => -- com
2223
                           right_ctrl <= zero_right;
2224
                                          alu_ctrl   <= alu_com;
2225
                                          acca_ctrl  <= load_acca;
2226
                                          cc_ctrl    <= load_cc;
2227
                         when "0100" => -- lsr
2228
                           right_ctrl <= zero_right;
2229
                                          alu_ctrl   <= alu_lsr8;
2230
                                          acca_ctrl  <= load_acca;
2231
                                          cc_ctrl    <= load_cc;
2232
                         when "0110" => -- ror
2233
                           right_ctrl <= zero_right;
2234
                                          alu_ctrl   <= alu_ror8;
2235
                                          acca_ctrl  <= load_acca;
2236
                                          cc_ctrl    <= load_cc;
2237
                         when "0111" => -- asr
2238
                           right_ctrl <= zero_right;
2239
                                          alu_ctrl   <= alu_asr8;
2240
                                          acca_ctrl  <= load_acca;
2241
                                          cc_ctrl    <= load_cc;
2242
                         when "1000" => -- asl
2243
                           right_ctrl <= zero_right;
2244
                                          alu_ctrl   <= alu_asl8;
2245
                                          acca_ctrl  <= load_acca;
2246
                                          cc_ctrl    <= load_cc;
2247
                         when "1001" => -- rol
2248
                           right_ctrl <= zero_right;
2249
                                          alu_ctrl   <= alu_rol8;
2250
                                          acca_ctrl  <= load_acca;
2251
                                          cc_ctrl    <= load_cc;
2252
                         when "1010" => -- dec
2253
                           right_ctrl <= one_right;
2254
                                          alu_ctrl   <= alu_dec;
2255
                                          acca_ctrl  <= load_acca;
2256
                                          cc_ctrl    <= load_cc;
2257
                         when "1011" => -- undefined
2258
                           right_ctrl <= zero_right;
2259
                                          alu_ctrl   <= alu_nop;
2260
                                          acca_ctrl  <= latch_acca;
2261
                                          cc_ctrl    <= latch_cc;
2262
                         when "1100" => -- inc
2263
                           right_ctrl <= one_right;
2264
                                          alu_ctrl   <= alu_inc;
2265
                                          acca_ctrl  <= load_acca;
2266
                                          cc_ctrl    <= load_cc;
2267
                         when "1101" => -- tst
2268
                           right_ctrl <= zero_right;
2269
                                          alu_ctrl   <= alu_st8;
2270
                                          acca_ctrl  <= latch_acca;
2271
                                          cc_ctrl    <= load_cc;
2272
                         when "1110" => -- jmp (not defined)
2273
                           right_ctrl <= zero_right;
2274
                                          alu_ctrl   <= alu_nop;
2275
                                          acca_ctrl  <= latch_acca;
2276
                                          cc_ctrl    <= latch_cc;
2277
                         when "1111" => -- clr
2278
                           right_ctrl <= zero_right;
2279
                                          alu_ctrl   <= alu_clr;
2280
                                          acca_ctrl  <= load_acca;
2281
                                          cc_ctrl    <= load_cc;
2282
                         when others =>
2283
                           right_ctrl <= zero_right;
2284
                                          alu_ctrl   <= alu_nop;
2285
                                          acca_ctrl  <= latch_acca;
2286
                                          cc_ctrl    <= latch_cc;
2287
                         end case;
2288
               lic        <= '1';
2289
                                   next_state <= fetch_state;
2290
                                 --
2291
                                 -- Single Operand accb
2292
                                 -- source = accb, dest = accb
2293
                                 -- Typically 2 cycles 1 bytes
2294
                                 -- 1 opcode fetch
2295
                                 -- 2 post byte fetch / instruction decode
2296
                                 -- Note that there is no post byte
2297
                                 -- so do not advance PC in decode cycle
2298
                                 -- Re-run opcode fetch cycle after decode
2299
                                 --
2300
                  when "0101" =>
2301
                         left_ctrl  <= accb_left;
2302
                    case op_code(3 downto 0) is
2303
                         when "0000" => -- neg
2304
                                          right_ctrl <= zero_right;
2305
                                          alu_ctrl   <= alu_neg;
2306
                                          accb_ctrl  <= load_accb;
2307
                                          cc_ctrl    <= load_cc;
2308
                    when "0011" => -- com
2309
                           right_ctrl <= zero_right;
2310
                                          alu_ctrl   <= alu_com;
2311
                                          accb_ctrl  <= load_accb;
2312
                                          cc_ctrl    <= load_cc;
2313
                         when "0100" => -- lsr
2314
                           right_ctrl <= zero_right;
2315
                                          alu_ctrl   <= alu_lsr8;
2316
                                          accb_ctrl  <= load_accb;
2317
                                          cc_ctrl    <= load_cc;
2318
                         when "0110" => -- ror
2319
                           right_ctrl <= zero_right;
2320
                                          alu_ctrl   <= alu_ror8;
2321
                                          accb_ctrl  <= load_accb;
2322
                                          cc_ctrl    <= load_cc;
2323
                         when "0111" => -- asr
2324
                           right_ctrl <= zero_right;
2325
                                          alu_ctrl   <= alu_asr8;
2326
                                          accb_ctrl  <= load_accb;
2327
                                          cc_ctrl    <= load_cc;
2328
                         when "1000" => -- asl
2329
                           right_ctrl <= zero_right;
2330
                                          alu_ctrl   <= alu_asl8;
2331
                                          accb_ctrl  <= load_accb;
2332
                                          cc_ctrl    <= load_cc;
2333
                         when "1001" => -- rol
2334
                           right_ctrl <= zero_right;
2335
                                          alu_ctrl   <= alu_rol8;
2336
                                          accb_ctrl  <= load_accb;
2337
                                          cc_ctrl    <= load_cc;
2338
                         when "1010" => -- dec
2339
                           right_ctrl <= one_right;
2340
                                          alu_ctrl   <= alu_dec;
2341
                                          accb_ctrl  <= load_accb;
2342
                                          cc_ctrl    <= load_cc;
2343
                         when "1011" => -- undefined
2344
                           right_ctrl <= zero_right;
2345
                                          alu_ctrl   <= alu_nop;
2346
                                          accb_ctrl  <= latch_accb;
2347
                                          cc_ctrl    <= latch_cc;
2348
                         when "1100" => -- inc
2349
                           right_ctrl <= one_right;
2350
                                          alu_ctrl   <= alu_inc;
2351
                                          accb_ctrl  <= load_accb;
2352
                                          cc_ctrl    <= load_cc;
2353
                         when "1101" => -- tst
2354
                           right_ctrl <= zero_right;
2355
                                          alu_ctrl   <= alu_st8;
2356
                                          accb_ctrl  <= latch_accb;
2357
                                          cc_ctrl    <= load_cc;
2358
                         when "1110" => -- jmp (undefined)
2359
                           right_ctrl <= zero_right;
2360
                                          alu_ctrl   <= alu_nop;
2361
                                          accb_ctrl  <= latch_accb;
2362
                                          cc_ctrl    <= latch_cc;
2363
                         when "1111" => -- clr
2364
                           right_ctrl <= zero_right;
2365
                                          alu_ctrl   <= alu_clr;
2366
                                          accb_ctrl  <= load_accb;
2367
                                          cc_ctrl    <= load_cc;
2368
                         when others =>
2369
                           right_ctrl <= zero_right;
2370
                                          alu_ctrl   <= alu_nop;
2371
                                          accb_ctrl  <= latch_accb;
2372
                                          cc_ctrl    <= latch_cc;
2373
                         end case;
2374
               lic          <= '1';
2375
                                   next_state   <= fetch_state;
2376
                                 --
2377
                                 -- Single operand indexed
2378
                                 -- Two byte instruction so advance PC
2379
                                 -- EA should hold index offset
2380
                                 --
2381
                  when "0110" => -- indexed single op
2382
                                        -- increment the pc 
2383
               pc_ctrl    <= incr_pc;
2384
                                   st_ctrl    <= push_st;
2385
                                        case op_code(3 downto 0) is
2386
                                   when "1110" => -- jmp
2387
                                     return_state <= jmp_state;
2388
                                        when "1111" => -- clr
2389
                                     return_state <= single_op_exec_state;
2390
                                        when others =>
2391
                                     return_state <= single_op_read_state;
2392
                                        end case;
2393
                                   next_state <= indexed_state;
2394
             --
2395
                                 -- Single operand extended addressing
2396
                                 -- three byte instruction so advance the PC
2397
                                 -- Low order EA holds high order address
2398
                                 --
2399
                  when "0111" => -- extended single op
2400
                                        -- increment PC
2401
               pc_ctrl    <= incr_pc;
2402
                                   st_ctrl    <= push_st;
2403
                                        case op_code(3 downto 0) is
2404
                                   when "1110" => -- jmp
2405
                                     return_state <= jmp_state;
2406
                                        when "1111" => -- clr
2407
                                     return_state <= single_op_exec_state;
2408
                                        when others =>
2409
                                     return_state <= single_op_read_state;
2410
                                        end case;
2411
                                   next_state <= extended_state;
2412
 
2413
                  when "1000" => -- acca immediate
2414
                                   -- increment the pc
2415
               pc_ctrl    <= incr_pc;
2416
                                        case op_code(3 downto 0) is
2417
               when "0011" | -- subd #
2418
                                             "1100" | -- cmpx #
2419
                                             "1110" => -- ldx #
2420
                                     st_ctrl      <= push_st;
2421
                                     return_state <= fetch_state;
2422
                                          next_state   <= imm16_state;
2423
 
2424
                                        --
2425
                                        -- bsr offset - Branch to subroutine (2 bytes)
2426
                                        -- 6809 => 7 cycles
2427
                                        -- cpu09 => 5 cycles
2428
                                        -- 1 op=(pc) / pc=pc+1
2429
                                   -- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
2430
                                        -- 3 (sp)=pc_lo / sp=sp-1
2431
                                        -- 4 (sp)=pc_hi
2432
                                        -- 5 pc=pc+md
2433
                                        --
2434
                                        when "1101" => -- bsr
2435
                                          -- pre decrement SP
2436
                 left_ctrl  <= sp_left;
2437
                 right_ctrl <= one_right;
2438
                 alu_ctrl   <= alu_sub16;
2439
                                     sp_ctrl    <= load_sp;
2440
                                          --
2441
                                     st_ctrl      <= push_st;
2442
                                     return_state <= sbranch_state;
2443
                                          next_state   <= push_return_lo_state;
2444
 
2445
                                        when others =>
2446
                 lic          <= '1';
2447
                                     next_state   <= fetch_state;
2448
               end case;
2449
 
2450
                  when "1001" => -- acca direct
2451
                                        -- increment the pc
2452
               pc_ctrl    <= incr_pc;
2453
                                        case op_code(3 downto 0) is
2454
               when "0011" | -- subd
2455
                                             "1100" | -- cmpx
2456
                                             "1110" => -- ldx
2457
                                     next_state   <= dual_op_read16_state;
2458
 
2459
                                        when "0111" =>  -- sta direct
2460
                                     next_state <= dual_op_write8_state;
2461
 
2462
                                        when "1111" => -- stx direct
2463
                                          -- idle ALU
2464
                 left_ctrl  <= ix_left;
2465
                 right_ctrl <= zero_right;
2466
                 alu_ctrl   <= alu_nop;
2467
                                          cc_ctrl    <= latch_cc;
2468
                                     sp_ctrl    <= latch_sp;
2469
                                     next_state <= dual_op_write16_state;
2470
 
2471
                                        --
2472
                                        -- jsr direct - Jump to subroutine in direct page (2 bytes)
2473
                                        -- 6809 => 7 cycles
2474
                                        -- cpu09 => 5 cycles
2475
                                        -- 1 op=(pc) / pc=pc+1
2476
                                   -- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
2477
                                        -- 3 (sp)=pc_lo / sp=sp-1
2478
                                        -- 4 (sp)=pc_hi
2479
                                        -- 5 pc=ea
2480
                                        --
2481
                                        when "1101" => -- jsr direct
2482
                                          -- pre decrement sp
2483
                 left_ctrl  <= sp_left;
2484
                 right_ctrl <= one_right;
2485
                 alu_ctrl   <= alu_sub16;
2486
                                     sp_ctrl    <= load_sp;
2487
                                          --
2488
                                     st_ctrl      <= push_st;
2489
                                     return_state <= jmp_state;
2490
                                          next_state   <= push_return_lo_state;
2491
 
2492
                                        when others =>
2493
                                     next_state   <= dual_op_read8_state;
2494
               end case;
2495
 
2496
                  when "1010" => -- acca indexed
2497
                                        -- increment the pc
2498
               pc_ctrl    <= incr_pc;
2499
                                        case op_code(3 downto 0) is
2500
               when "0011" | -- subd
2501
                                             "1100" | -- cmpx
2502
                                             "1110" => -- ldx
2503
                                     st_ctrl      <= push_st;
2504
                                     return_state <= dual_op_read16_state;
2505
                                     next_state   <= indexed_state;
2506
 
2507
                                        when "0111" =>  -- staa ,x
2508
                                     st_ctrl      <= push_st;
2509
                                     return_state <= dual_op_write8_state;
2510
                                     next_state   <= indexed_state;
2511
 
2512
                                        when "1111" => -- stx ,x
2513
                                     st_ctrl      <= push_st;
2514
                                     return_state <= dual_op_write16_state;
2515
                                     next_state   <= indexed_state;
2516
 
2517
                                        when "1101" => -- jsr ,x
2518
                                          -- DO NOT pre decrement SP
2519
                                     st_ctrl      <= push_st;
2520
                                     return_state <= jsr_state;
2521
                                          next_state   <= indexed_state;
2522
 
2523
                                        when others =>
2524
                                     st_ctrl      <= push_st;
2525
                                     return_state <= dual_op_read8_state;
2526
                                     next_state   <= indexed_state;
2527
               end case;
2528
 
2529
             when "1011" => -- acca extended
2530
                                        -- increment the pc
2531
               pc_ctrl    <= incr_pc;
2532
                                        case op_code(3 downto 0) is
2533
               when "0011" | -- subd
2534
                                             "1100" | -- cmpx
2535
                                             "1110" => -- ldx
2536
                                     st_ctrl      <= push_st;
2537
                                     return_state <= dual_op_read16_state;
2538
                                     next_state   <= extended_state;
2539
 
2540
                                        when "0111" =>  -- staa >
2541
                                     st_ctrl      <= push_st;
2542
                                     return_state <= dual_op_write8_state;
2543
                                     next_state   <= extended_state;
2544
 
2545
                                        when "1111" => -- stx >
2546
                                     st_ctrl      <= push_st;
2547
                                     return_state <= dual_op_write16_state;
2548
                                     next_state   <= extended_state;
2549
 
2550
                                        when "1101" => -- jsr >extended
2551
                                          -- DO NOT pre decrement sp
2552
                                     st_ctrl      <= push_st;
2553
                                     return_state <= jsr_state;
2554
                                          next_state   <= extended_state;
2555
 
2556
                                        when others =>
2557
                                     st_ctrl      <= push_st;
2558
                                     return_state <= dual_op_read8_state;
2559
                                     next_state   <= extended_state;
2560
               end case;
2561
 
2562
                  when "1100" => -- accb immediate
2563
                                        -- increment the pc
2564
               pc_ctrl    <= incr_pc;
2565
                                        case op_code(3 downto 0) is
2566
               when "0011" | -- addd #
2567
                                             "1100" | -- ldd #
2568
                                             "1110" => -- ldu #
2569
                                     st_ctrl      <= push_st;
2570
                                     return_state <= fetch_state;
2571
                                          next_state   <= imm16_state;
2572
 
2573
                                        when others =>
2574
                 lic          <= '1';
2575
                                     next_state   <= fetch_state;
2576
 
2577
               end case;
2578
 
2579
 
2580
                  when "1101" => -- accb direct
2581
                                        -- increment the pc
2582
               pc_ctrl    <= incr_pc;
2583
                                        case op_code(3 downto 0) is
2584
               when "0011" | -- addd
2585
                                             "1100" | -- ldd
2586
                                             "1110" => -- ldu
2587
                                     next_state   <= dual_op_read16_state;
2588
 
2589
                                        when "0111" =>  -- stab direct
2590
                                     next_state   <= dual_op_write8_state;
2591
 
2592
                                        when "1101" =>  -- std direct
2593
                                     next_state   <= dual_op_write16_state;
2594
 
2595
                                        when "1111" => -- stu direct
2596
                                     next_state   <= dual_op_write16_state;
2597
 
2598
                                        when others =>
2599
                                     next_state   <= dual_op_read8_state;
2600
               end case;
2601
 
2602
                  when "1110" => -- accb indexed
2603
                                        -- increment the pc
2604
               pc_ctrl    <= incr_pc;
2605
                                        case op_code(3 downto 0) is
2606
               when "0011" | -- addd
2607
                                             "1100" | -- ldd
2608
                                             "1110" => -- ldu
2609
                                     st_ctrl      <= push_st;
2610
                                     return_state <= dual_op_read16_state;
2611
                                     next_state   <= indexed_state;
2612
 
2613
                                        when "0111" =>  -- stab indexed
2614
                                     st_ctrl      <= push_st;
2615
                                     return_state <= dual_op_write8_state;
2616
                                     next_state   <= indexed_state;
2617
 
2618
                                        when "1101" =>  -- std indexed
2619
                                     st_ctrl      <= push_st;
2620
                                     return_state <= dual_op_write16_state;
2621
                                     next_state   <= indexed_state;
2622
 
2623
                                        when "1111" => -- stu indexed
2624
                                     st_ctrl      <= push_st;
2625
                                     return_state <= dual_op_write16_state;
2626
                                     next_state   <= indexed_state;
2627
 
2628
                                        when others =>
2629
                                     st_ctrl      <= push_st;
2630
                                     return_state <= dual_op_read8_state;
2631
                                     next_state   <= indexed_state;
2632
               end case;
2633
 
2634
             when "1111" => -- accb extended
2635
                                        -- increment the pc
2636
               pc_ctrl    <= incr_pc;
2637
                                        case op_code(3 downto 0) is
2638
               when "0011" | -- addd
2639
                                             "1100" | -- ldd
2640
                                             "1110" => -- ldu
2641
                                     st_ctrl      <= push_st;
2642
                                     return_state <= dual_op_read16_state;
2643
                                     next_state   <= extended_state;
2644
 
2645
                                        when "0111" =>  -- stab extended
2646
                                     st_ctrl      <= push_st;
2647
                                     return_state <= dual_op_write8_state;
2648
                                     next_state   <= extended_state;
2649
 
2650
                                        when "1101" =>  -- std extended
2651
                                     st_ctrl      <= push_st;
2652
                                     return_state <= dual_op_write16_state;
2653
                                     next_state   <= extended_state;
2654
 
2655
                                        when "1111" => -- stu  extended
2656
                                     st_ctrl      <= push_st;
2657
                                     return_state <= dual_op_write16_state;
2658
                                     next_state   <= extended_state;
2659
 
2660
                                        when others =>
2661
                                     st_ctrl      <= push_st;
2662
                                     return_state <= dual_op_read8_state;
2663
                                     next_state   <= extended_state;
2664
               end case;
2665
 
2666
                  when others =>
2667
                                   null;
2668
             end case;
2669
 
2670
                         --
2671
                         -- Here to decode prefix 2 instruction
2672
                         -- and fetch next byte of intruction
2673
                         -- whether it be necessary or not
2674
                         --
2675
          when decode2_state =>
2676
                                 -- fetch first byte of address or immediate data
2677
             ea_ctrl    <= fetch_first_ea;
2678
                                 md_ctrl    <= fetch_first_md;
2679
             addr_ctrl  <= fetch_ad;
2680
                            case op_code(7 downto 4) is
2681
                                 --
2682
                                 -- lbcc -- long branch conditional
2683
                                 -- 6809 => branch 6 cycles, no branch 5 cycles
2684
                                 -- cpu09 => always 5 cycles
2685
                                 -- 1 pre=(pc) / pc=pc+1
2686
                                 -- 2 op=(pc) / pc=pc+1
2687
                                 -- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
2688
             -- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
2689
                                 -- 5 if cond pc=pc+md else pc=pc
2690
                                 --
2691
                  when "0010" =>
2692
                                        -- increment the pc
2693
               pc_ctrl    <= incr_pc;
2694
                                        next_state <= lbranch_state;
2695
 
2696
                                 --
2697
                                 -- Single byte stack operators
2698
                                 -- Do not advance PC
2699
                                 --
2700
                  when "0011" =>
2701
                    case op_code(3 downto 0) is
2702
                         when "1111" => -- swi 2
2703
                                           -- predecrement sp
2704
                            left_ctrl  <= sp_left;
2705
                            right_ctrl <= one_right;
2706
                                                alu_ctrl   <= alu_sub16;
2707
                                                sp_ctrl    <= load_sp;
2708
                  iv_ctrl    <= swi2_iv;
2709
                                                next_state <= int_entire_state;
2710
 
2711
                         when others =>
2712
                 lic          <= '1';
2713
                                          next_state   <= fetch_state;
2714
                         end case;
2715
 
2716
                  when "1000" => -- acca immediate
2717
                                   -- increment the pc
2718
               pc_ctrl    <= incr_pc;
2719
                                        case op_code(3 downto 0) is
2720
               when "0011" | -- cmpd #
2721
                                             "1100" | -- cmpy #
2722
                                             "1110" => -- ldy #
2723
                                     st_ctrl      <= push_st;
2724
                                     return_state <= fetch_state;
2725
                                          next_state   <= imm16_state;
2726
 
2727
                                        when others =>
2728
                 lic          <= '1';
2729
                                     next_state   <= fetch_state;
2730
 
2731
               end case;
2732
 
2733
                  when "1001" => -- acca direct
2734
                                        -- increment the pc
2735
               pc_ctrl    <= incr_pc;
2736
                                        case op_code(3 downto 0) is
2737
               when "0011" | -- cmpd <
2738
                                             "1100" | -- cmpy <
2739
                                             "1110" => -- ldy <
2740
                                          next_state   <= dual_op_read16_state;
2741
 
2742
                                        when "1111" => -- sty <
2743
                                     next_state   <= dual_op_write16_state;
2744
 
2745
                                        when others =>
2746
                 lic          <= '1';
2747
                                     next_state   <= fetch_state;
2748
 
2749
               end case;
2750
 
2751
                  when "1010" => -- acca indexed
2752
                                        -- increment the pc
2753
               pc_ctrl    <= incr_pc;
2754
                                        case op_code(3 downto 0) is
2755
               when "0011" | -- cmpd ,ind
2756
                                             "1100" | -- cmpy ,ind
2757
                                             "1110" => -- ldy ,ind
2758
                                     st_ctrl      <= push_st;
2759
                                     return_state <= dual_op_read16_state;
2760
                                          next_state   <= indexed_state;
2761
 
2762
                                        when "1111" => -- sty ,ind
2763
                                     st_ctrl      <= push_st;
2764
                                     return_state <= dual_op_write16_state;
2765
                                     next_state   <= indexed_state;
2766
 
2767
                                        when others =>
2768
                 lic          <= '1';
2769
                                     next_state   <= fetch_state;
2770
               end case;
2771
 
2772
             when "1011" => -- acca extended
2773
                                        -- increment the pc
2774
               pc_ctrl    <= incr_pc;
2775
                                        case op_code(3 downto 0) is
2776
               when "0011" | -- cmpd <
2777
                                             "1100" | -- cmpy <
2778
                                             "1110" => -- ldy <
2779
                                     st_ctrl      <= push_st;
2780
                                     return_state <= dual_op_read16_state;
2781
                                          next_state   <= extended_state;
2782
 
2783
                                        when "1111" => -- sty >
2784
                                     st_ctrl      <= push_st;
2785
                                     return_state <= dual_op_write16_state;
2786
                                     next_state   <= extended_state;
2787
 
2788
                                        when others =>
2789
                 lic          <= '1';
2790
                                     next_state   <= fetch_state;
2791
 
2792
               end case;
2793
 
2794
                  when "1100" => -- accb immediate
2795
                                        -- increment the pc
2796
               pc_ctrl    <= incr_pc;
2797
                                        case op_code(3 downto 0) is
2798
               when "0011" | -- undef #
2799
                                             "1100" | -- undef #
2800
                                             "1110" => -- lds #
2801
                                     st_ctrl      <= push_st;
2802
                                     return_state <= fetch_state;
2803
                                          next_state   <= imm16_state;
2804
 
2805
                                        when others =>
2806
                                     next_state   <= fetch_state;
2807
 
2808
               end case;
2809
 
2810
                  when "1101" => -- accb direct
2811
                                        -- increment the pc
2812
               pc_ctrl    <= incr_pc;
2813
                                        case op_code(3 downto 0) is
2814
               when "0011" | -- undef <
2815
                                             "1100" | -- undef <
2816
                                             "1110" => -- lds <
2817
                                          next_state   <= dual_op_read16_state;
2818
 
2819
                                        when "1111" => -- sts <
2820
                                     next_state   <= dual_op_write16_state;
2821
 
2822
                                        when others =>
2823
                 lic          <= '1';
2824
                                     next_state   <= fetch_state;
2825
 
2826
               end case;
2827
 
2828
                  when "1110" => -- accb indexed
2829
                                        -- increment the pc
2830
               pc_ctrl    <= incr_pc;
2831
                                        case op_code(3 downto 0) is
2832
               when "0011" | -- undef ,ind
2833
                                             "1100" | -- undef ,ind
2834
                                             "1110" => -- lds ,ind
2835
                                     st_ctrl      <= push_st;
2836
                                     return_state <= dual_op_read16_state;
2837
                                          next_state   <= indexed_state;
2838
 
2839
                                        when "1111" => -- sts ,ind
2840
                                     st_ctrl      <= push_st;
2841
                                     return_state <= dual_op_write16_state;
2842
                                     next_state   <= indexed_state;
2843
 
2844
                                        when others =>
2845
                 lic          <= '1';
2846
                                     next_state   <= fetch_state;
2847
 
2848
               end case;
2849
 
2850
             when "1111" => -- accb extended
2851
                                        -- increment the pc
2852
               pc_ctrl    <= incr_pc;
2853
                                        case op_code(3 downto 0) is
2854
               when "0011" | -- undef >
2855
                                             "1100" | -- undef >
2856
                                             "1110" => -- lds >
2857
                                     st_ctrl      <= push_st;
2858
                                     return_state <= dual_op_read16_state;
2859
                                          next_state   <= extended_state;
2860
 
2861
                                        when "1111" => -- sts >
2862
                                     st_ctrl      <= push_st;
2863
                                     return_state <= dual_op_write16_state;
2864
                                     next_state   <= extended_state;
2865
 
2866
                                        when others =>
2867
                 lic          <= '1';
2868
                                     next_state   <= fetch_state;
2869
               end case;
2870
 
2871
                  when others =>
2872
               lic          <= '1';
2873
                         next_state   <= fetch_state;
2874
             end case;
2875
                         --
2876
                         -- Here to decode instruction
2877
                         -- and fetch next byte of intruction
2878
                         -- whether it be necessary or not
2879
                         --
2880
          when decode3_state =>
2881
             ea_ctrl    <= fetch_first_ea;
2882
                                 md_ctrl    <= fetch_first_md;
2883
             addr_ctrl  <= fetch_ad;
2884
             dout_ctrl  <= md_lo_dout;
2885
                            case op_code(7 downto 4) is
2886
                                 --
2887
                                 -- Single byte stack operators
2888
                                 -- Do not advance PC
2889
                                 --
2890
                  when "0011" =>
2891
                    case op_code(3 downto 0) is
2892
                         when "1111" => -- swi3
2893
                                           -- predecrement sp
2894
                            left_ctrl  <= sp_left;
2895
                            right_ctrl <= one_right;
2896
                                                alu_ctrl   <= alu_sub16;
2897
                                                sp_ctrl    <= load_sp;
2898
                  iv_ctrl    <= swi3_iv;
2899
                                                next_state <= int_entire_state;
2900
                         when others =>
2901
                 lic          <= '1';
2902
                                          next_state   <= fetch_state;
2903
                         end case;
2904
 
2905
                  when "1000" => -- acca immediate
2906
                                   -- increment the pc
2907
               pc_ctrl    <= incr_pc;
2908
                                        case op_code(3 downto 0) is
2909
               when "0011" | -- cmpu #
2910
                                             "1100" | -- cmps #
2911
                                             "1110" => -- undef #
2912
                                     st_ctrl      <= push_st;
2913
                                     return_state <= fetch_state;
2914
                                          next_state   <= imm16_state;
2915
                                        when others =>
2916
                 lic          <= '1';
2917
                                     next_state   <= fetch_state;
2918
               end case;
2919
 
2920
                  when "1001" => -- acca direct
2921
                                        -- increment the pc
2922
               pc_ctrl    <= incr_pc;
2923
                                        case op_code(3 downto 0) is
2924
               when "0011" | -- cmpu <
2925
                                             "1100" | -- cmps <
2926
                                             "1110" => -- undef <
2927
                                     st_ctrl      <= idle_st;
2928
                                     return_state <= fetch_state;
2929
                                          next_state   <= dual_op_read16_state;
2930
 
2931
                                        when others =>
2932
                 lic          <= '1';
2933
                                     next_state   <= fetch_state;
2934
 
2935
               end case;
2936
 
2937
                  when "1010" => -- acca indexed
2938
                                        -- increment the pc
2939
               pc_ctrl    <= incr_pc;
2940
                                        case op_code(3 downto 0) is
2941
               when "0011" | -- cmpu ,X
2942
                                             "1100" | -- cmps ,X
2943
                                             "1110" => -- undef ,X
2944
                                     st_ctrl      <= push_st;
2945
                                     return_state <= dual_op_read16_state;
2946
                                          next_state   <= indexed_state;
2947
 
2948
                                        when others =>
2949
                 lic          <= '1';
2950
                                     next_state   <= fetch_state;
2951
 
2952
               end case;
2953
 
2954
             when "1011" => -- acca extended
2955
                                        -- increment the pc
2956
               pc_ctrl    <= incr_pc;
2957
                                        case op_code(3 downto 0) is
2958
               when "0011" | -- cmpu >
2959
                                             "1100" | -- cmps >
2960
                                             "1110" => -- undef >
2961
                                     st_ctrl      <= push_st;
2962
                                     return_state <= dual_op_read16_state;
2963
                                          next_state   <= extended_state;
2964
                                        when others =>
2965
                 lic          <= '1';
2966
                                     next_state   <= fetch_state;
2967
               end case;
2968
 
2969
                  when others =>
2970
               lic          <= '1';
2971
                         next_state   <= fetch_state;
2972
             end case;
2973
 
2974
           --
2975
                          -- here if ea holds low byte
2976
                          -- Direct
2977
                          -- Extended
2978
                          -- Indexed
2979
                          -- read memory location
2980
                          --
2981
                          when single_op_read_state =>
2982
                                        -- read memory into md
2983
                                   md_ctrl    <= fetch_first_md;
2984
               addr_ctrl  <= read_ad;
2985
                                        dout_ctrl  <= md_lo_dout;
2986
                                        next_state <= single_op_exec_state;
2987
 
2988
                when single_op_exec_state =>
2989
                    case op_code(3 downto 0) is
2990
                         when "0000" => -- neg
2991
                   left_ctrl  <= md_left;
2992
                                            right_ctrl <= zero_right;
2993
                                            alu_ctrl   <= alu_neg;
2994
                                            cc_ctrl    <= load_cc;
2995
                                       md_ctrl    <= load_md;
2996
                                       next_state <= single_op_write_state;
2997
                    when "0011" => -- com
2998
                   left_ctrl  <= md_left;
2999
                             right_ctrl <= zero_right;
3000
                                            alu_ctrl   <= alu_com;
3001
                                            cc_ctrl    <= load_cc;
3002
                                       md_ctrl    <= load_md;
3003
                                       next_state <= single_op_write_state;
3004
                         when "0100" => -- lsr
3005
                   left_ctrl  <= md_left;
3006
                                                 right_ctrl <= zero_right;
3007
                                            alu_ctrl   <= alu_lsr8;
3008
                                            cc_ctrl    <= load_cc;
3009
                                       md_ctrl    <= load_md;
3010
                                       next_state <= single_op_write_state;
3011
                         when "0110" => -- ror
3012
                   left_ctrl  <= md_left;
3013
                                                 right_ctrl <= zero_right;
3014
                                            alu_ctrl   <= alu_ror8;
3015
                                            cc_ctrl    <= load_cc;
3016
                                       md_ctrl    <= load_md;
3017
                                       next_state <= single_op_write_state;
3018
                         when "0111" => -- asr
3019
                   left_ctrl  <= md_left;
3020
                                                 right_ctrl <= zero_right;
3021
                                            alu_ctrl   <= alu_asr8;
3022
                                            cc_ctrl    <= load_cc;
3023
                                       md_ctrl    <= load_md;
3024
                                       next_state <= single_op_write_state;
3025
                         when "1000" => -- asl
3026
                   left_ctrl  <= md_left;
3027
                                                 right_ctrl <= zero_right;
3028
                                            alu_ctrl   <= alu_asl8;
3029
                                            cc_ctrl    <= load_cc;
3030
                                       md_ctrl    <= load_md;
3031
                                       next_state <= single_op_write_state;
3032
                         when "1001" => -- rol
3033
                   left_ctrl  <= md_left;
3034
                                                 right_ctrl <= zero_right;
3035
                                            alu_ctrl   <= alu_rol8;
3036
                                            cc_ctrl    <= load_cc;
3037
                                       md_ctrl    <= load_md;
3038
                                       next_state <= single_op_write_state;
3039
                         when "1010" => -- dec
3040
                   left_ctrl  <= md_left;
3041
                             right_ctrl <= one_right;
3042
                                            alu_ctrl   <= alu_dec;
3043
                                            cc_ctrl    <= load_cc;
3044
                                       md_ctrl    <= load_md;
3045
                                       next_state <= single_op_write_state;
3046
                         when "1011" => -- undefined
3047
                   lic        <= '1';
3048
                                       next_state <= fetch_state;
3049
                         when "1100" => -- inc
3050
                   left_ctrl  <= md_left;
3051
                             right_ctrl <= one_right;
3052
                                            alu_ctrl   <= alu_inc;
3053
                                            cc_ctrl    <= load_cc;
3054
                                       md_ctrl    <= load_md;
3055
                                       next_state <= single_op_write_state;
3056
                         when "1101" => -- tst
3057
                   left_ctrl  <= md_left;
3058
                             right_ctrl <= zero_right;
3059
                                            alu_ctrl   <= alu_st8;
3060
                                            cc_ctrl    <= load_cc;
3061
                   lic        <= '1';
3062
                                       next_state <= fetch_state;
3063
                         when "1110" => -- jmp
3064
                   left_ctrl  <= md_left;
3065
                                                 right_ctrl <= zero_right;
3066
                                            alu_ctrl   <= alu_ld16;
3067
                   pc_ctrl    <= load_pc;
3068
                   lic          <= '1';
3069
                                       next_state <= fetch_state;
3070
                         when "1111" => -- clr
3071
                   left_ctrl  <= md_left;
3072
                                                 right_ctrl <= zero_right;
3073
                                            alu_ctrl   <= alu_clr;
3074
                                            cc_ctrl    <= load_cc;
3075
                                       md_ctrl    <= load_md;
3076
                                       next_state <= single_op_write_state;
3077
                         when others =>
3078
                 lic        <= '1';
3079
                                     next_state <= fetch_state;
3080
                         end case;
3081
           --
3082
                          -- single operand 8 bit write
3083
                          -- Write low 8 bits of ALU output
3084
                          -- EA holds address
3085
                          -- MD holds data
3086
                          --
3087
                          when single_op_write_state =>
3088
                                 -- write ALU low byte output
3089
             addr_ctrl  <= write_ad;
3090
             dout_ctrl  <= md_lo_dout;
3091
             lic        <= '1';
3092
                                 next_state <= fetch_state;
3093
 
3094
           --
3095
                          -- here if ea holds address of low byte
3096
                          -- read memory location
3097
                          --
3098
                          when dual_op_read8_state =>
3099
                                   -- read first data byte from ea
3100
                                   md_ctrl    <= fetch_first_md;
3101
               addr_ctrl  <= read_ad;
3102
               lic        <= '1';
3103
                                        next_state <= fetch_state;
3104
 
3105
                                --
3106
                                -- Here to read a 16 bit value into MD
3107
                                -- pointed to by the EA register
3108
                                -- The first byte is read
3109
                                -- and the EA is incremented
3110
                                --
3111
                           when dual_op_read16_state =>
3112
                                        -- increment the effective address
3113
               left_ctrl  <= ea_left;
3114
               right_ctrl <= one_right;
3115
               alu_ctrl   <= alu_add16;
3116
               ea_ctrl    <= load_ea;
3117
                                        -- read the high byte of the 16 bit data
3118
                                   md_ctrl    <= fetch_first_md;
3119
               addr_ctrl  <= read_ad;
3120
                                        next_state <= dual_op_read16_2_state;
3121
 
3122
                                --
3123
                                -- here to read the second byte
3124
                           -- pointed to by EA into MD
3125
                                --
3126
                           when dual_op_read16_2_state =>
3127
                                        -- read the low byte of the 16 bit data
3128
                                   md_ctrl    <= fetch_next_md;
3129
               addr_ctrl  <= read_ad;
3130
               lic        <= '1';
3131
                                        next_state <= fetch_state;
3132
 
3133
           --
3134
                          -- 16 bit Write state
3135
                          -- EA hold address of memory to write to
3136
                          -- Advance the effective address in ALU
3137
                          -- decode op_code to determine which
3138
                          -- register to write
3139
                          --
3140
                          when dual_op_write16_state =>
3141
                                 -- increment the effective address
3142
                                 left_ctrl  <= ea_left;
3143
                                 right_ctrl <= one_right;
3144
                                 alu_ctrl   <= alu_add16;
3145
                            ea_ctrl    <= load_ea;
3146
                                 -- write the ALU hi byte at ea
3147
             addr_ctrl  <= write_ad;
3148
                                 if op_code(6) = '0' then
3149
                                   case op_code(3 downto 0) is
3150
                              when "1111" => -- stx / sty
3151
                                          case pre_code is
3152
                                          when "00010000" => -- page 2 -- sty
3153
                        dout_ctrl  <= iy_hi_dout;
3154
                                     when others =>     -- page 1 -- stx
3155
                   dout_ctrl  <= ix_hi_dout;
3156
                                          end case;
3157
                                   when others =>
3158
                 dout_ctrl  <= md_hi_dout;
3159
                                   end case;
3160
             else
3161
                                   case op_code(3 downto 0) is
3162
                              when "1101" => -- std
3163
                 dout_ctrl  <= acca_dout; -- acca is high byte of ACCD
3164
                              when "1111" => -- stu / sts
3165
                                          case pre_code is
3166
                                          when "00010000" => -- page 2 -- sts
3167
                        dout_ctrl  <= sp_hi_dout;
3168
                                          when others =>     -- page 1 -- stu
3169
                        dout_ctrl  <= up_hi_dout;
3170
                                          end case;
3171
                                   when others =>
3172
                 dout_ctrl  <= md_hi_dout;
3173
                                   end case;
3174
             end if;
3175
                                 next_state   <= dual_op_write8_state;
3176
 
3177
           --
3178
                          -- Dual operand 8 bit write
3179
           -- Write 8 bit accumulator
3180
                          -- or low byte of 16 bit register
3181
                          -- EA holds address
3182
                          -- decode opcode to determine
3183
                          -- which register to apply to the bus
3184
                          -- Also set the condition codes here
3185
                          --
3186
                          when dual_op_write8_state =>
3187
                            if op_code(6) = '0' then
3188
                                   case op_code(3 downto 0) is
3189
                                        when "0111" => -- sta
3190
                 dout_ctrl  <= acca_dout;
3191
                                        when "1111" => -- stx / sty
3192
                                          case pre_code is
3193
                                          when "00010000" => -- page 2 -- sty
3194
                        dout_ctrl  <= iy_lo_dout;
3195
                                     when others =>     -- page 1 -- stx
3196
                   dout_ctrl  <= ix_lo_dout;
3197
                                          end case;
3198
                                        when others =>
3199
                 dout_ctrl  <= md_lo_dout;
3200
                                        end case;
3201
             else
3202
                                   case op_code(3 downto 0) is
3203
                                        when "0111" => -- stb
3204
                 dout_ctrl  <= accb_dout;
3205
                                        when "1101" => -- std
3206
                 dout_ctrl  <= accb_dout; -- accb is low byte of accd
3207
                                        when "1111" => -- stu / sts
3208
                                          case pre_code is
3209
                                          when "00010000" => -- page 2 -- sts
3210
                        dout_ctrl  <= sp_lo_dout;
3211
                                          when others =>     -- page 1 -- stu
3212
                        dout_ctrl  <= up_lo_dout;
3213
                                          end case;
3214
                                        when others =>
3215
                 dout_ctrl  <= md_lo_dout;
3216
                                        end case;
3217
             end if;
3218
                                 -- write ALU low byte output
3219
             addr_ctrl    <= write_ad;
3220
             lic          <= '1';
3221
                                 next_state   <= fetch_state;
3222
 
3223
                          --
3224
                          -- 16 bit immediate addressing mode
3225
                          --
3226
                          when imm16_state =>
3227
                                   -- increment pc
3228
               pc_ctrl    <= incr_pc;
3229
                                   -- fetch next immediate byte
3230
                              md_ctrl    <= fetch_next_md;
3231
               addr_ctrl  <= fetch_ad;
3232
                                        st_ctrl    <= pull_st;
3233
               lic        <= '1';
3234
                                        next_state <= saved_state;
3235
 
3236
           --
3237
                          -- md & ea holds 8 bit index offset
3238
                          -- calculate the effective memory address
3239
                          -- using the alu
3240
                          --
3241
           when indexed_state =>
3242
                                 --
3243
                                 -- decode indexing mode
3244
                                 --
3245
                                 if md(7) = '0' then
3246
                                   case md(6 downto 5) is
3247
                                        when "00" =>
3248
                                left_ctrl  <= ix_left;
3249
                                        when "01" =>
3250
                                left_ctrl  <= iy_left;
3251
                                        when "10" =>
3252
                                left_ctrl  <= up_left;
3253
                                        when others =>
3254
                                        -- when "11" =>
3255
                                left_ctrl  <= sp_left;
3256
                                        end case;
3257
                                   right_ctrl   <= md_sign5_right;
3258
                                   alu_ctrl     <= alu_add16;
3259
               ea_ctrl      <= load_ea;
3260
                                        st_ctrl      <= pull_st;
3261
                                        next_state   <= saved_state;
3262
 
3263
                                 else
3264
                                   case md(3 downto 0) is
3265
                                        when "0000" =>     -- ,R+
3266
                                     case md(6 downto 5) is
3267
                                          when "00" =>
3268
                                  left_ctrl  <= ix_left;
3269
                                          when "01" =>
3270
                                  left_ctrl  <= iy_left;
3271
                                          when "10" =>
3272
                                  left_ctrl  <= up_left;
3273
                                          when others =>
3274
                                  left_ctrl  <= sp_left;
3275
                                          end case;
3276
                                          --
3277
                                     right_ctrl <= zero_right;
3278
                                     alu_ctrl   <= alu_add16;
3279
                 ea_ctrl    <= load_ea;
3280
                 next_state <= postincr1_state;
3281
 
3282
                                        when "0001" =>     -- ,R++
3283
                                     case md(6 downto 5) is
3284
                                          when "00" =>
3285
                                  left_ctrl  <= ix_left;
3286
                                          when "01" =>
3287
                                  left_ctrl  <= iy_left;
3288
                                          when "10" =>
3289
                                  left_ctrl  <= up_left;
3290
                                          when others =>
3291
                                          -- when "11" =>
3292
                                  left_ctrl  <= sp_left;
3293
                                          end case;
3294
                                     right_ctrl <= zero_right;
3295
                                     alu_ctrl   <= alu_add16;
3296
                 ea_ctrl    <= load_ea;
3297
                 next_state <= postincr2_state;
3298
 
3299
                                        when "0010" =>     -- ,-R
3300
                                     case md(6 downto 5) is
3301
                                          when "00" =>
3302
                                  left_ctrl  <= ix_left;
3303
                   ix_ctrl    <= load_ix;
3304
                                          when "01" =>
3305
                                  left_ctrl  <= iy_left;
3306
                   iy_ctrl    <= load_iy;
3307
                                          when "10" =>
3308
                                  left_ctrl  <= up_left;
3309
                   up_ctrl    <= load_up;
3310
                                          when others =>
3311
                                          -- when "11" =>
3312
                                  left_ctrl  <= sp_left;
3313
                   sp_ctrl    <= load_sp;
3314
                                          end case;
3315
                                     right_ctrl   <= one_right;
3316
                                     alu_ctrl     <= alu_sub16;
3317
                 ea_ctrl      <= load_ea;
3318
                                          st_ctrl      <= pull_st;
3319
                                          next_state   <= saved_state;
3320
 
3321
                                        when "0011" =>     -- ,--R
3322
                                     case md(6 downto 5) is
3323
                                          when "00" =>
3324
                                  left_ctrl  <= ix_left;
3325
                   ix_ctrl    <= load_ix;
3326
                                          when "01" =>
3327
                                  left_ctrl  <= iy_left;
3328
                   iy_ctrl    <= load_iy;
3329
                                          when "10" =>
3330
                                  left_ctrl  <= up_left;
3331
                   up_ctrl    <= load_up;
3332
                                          when others =>
3333
                                          -- when "11" =>
3334
                                  left_ctrl  <= sp_left;
3335
                   sp_ctrl    <= load_sp;
3336
                                          end case;
3337
                                     right_ctrl <= two_right;
3338
                                     alu_ctrl   <= alu_sub16;
3339
                 ea_ctrl    <= load_ea;
3340
                                          if md(4) = '0' then
3341
                                            st_ctrl      <= pull_st;
3342
                                            next_state   <= saved_state;
3343
                                          else
3344
                                            next_state   <= indirect_state;
3345
                                          end if;
3346
 
3347
                                        when "0100" =>     -- ,R (zero offset)
3348
                                     case md(6 downto 5) is
3349
                                          when "00" =>
3350
                                  left_ctrl  <= ix_left;
3351
                                          when "01" =>
3352
                                  left_ctrl  <= iy_left;
3353
                                          when "10" =>
3354
                                  left_ctrl  <= up_left;
3355
                                          when others =>
3356
                                          -- when "11" =>
3357
                                  left_ctrl  <= sp_left;
3358
                                          end case;
3359
                                     right_ctrl <= zero_right;
3360
                                     alu_ctrl   <= alu_add16;
3361
                 ea_ctrl    <= load_ea;
3362
                                          if md(4) = '0' then
3363
                                            st_ctrl      <= pull_st;
3364
                                            next_state   <= saved_state;
3365
                                          else
3366
                                            next_state   <= indirect_state;
3367
                                          end if;
3368
 
3369
                                        when "0101" =>     -- ACCB,R
3370
                                     case md(6 downto 5) is
3371
                                          when "00" =>
3372
                                  left_ctrl  <= ix_left;
3373
                                          when "01" =>
3374
                                  left_ctrl  <= iy_left;
3375
                                          when "10" =>
3376
                                  left_ctrl  <= up_left;
3377
                                          when others =>
3378
                                          -- when "11" =>
3379
                                  left_ctrl  <= sp_left;
3380
                                          end case;
3381
                                     right_ctrl <= accb_right;
3382
                                     alu_ctrl   <= alu_add16;
3383
                 ea_ctrl    <= load_ea;
3384
                                          if md(4) = '0' then
3385
                                            st_ctrl      <= pull_st;
3386
                                            next_state   <= saved_state;
3387
                                          else
3388
                                            next_state   <= indirect_state;
3389
                                          end if;
3390
 
3391
                                        when "0110" =>     -- ACCA,R
3392
                                     case md(6 downto 5) is
3393
                                          when "00" =>
3394
                                  left_ctrl  <= ix_left;
3395
                                          when "01" =>
3396
                                  left_ctrl  <= iy_left;
3397
                                          when "10" =>
3398
                                  left_ctrl  <= up_left;
3399
                                          when others =>
3400
                                          -- when "11" =>
3401
                                  left_ctrl  <= sp_left;
3402
                                          end case;
3403
                                     right_ctrl <= acca_right;
3404
                                     alu_ctrl   <= alu_add16;
3405
                 ea_ctrl    <= load_ea;
3406
                                          if md(4) = '0' then
3407
                                            st_ctrl      <= pull_st;
3408
                                            next_state   <= saved_state;
3409
                                          else
3410
                                            next_state   <= indirect_state;
3411
                                          end if;
3412
 
3413
                                        when "0111" =>     -- undefined
3414
                                     case md(6 downto 5) is
3415
                                          when "00" =>
3416
                                  left_ctrl  <= ix_left;
3417
                                          when "01" =>
3418
                                  left_ctrl  <= iy_left;
3419
                                          when "10" =>
3420
                                  left_ctrl  <= up_left;
3421
                                          when others =>
3422
                                          -- when "11" =>
3423
                                  left_ctrl  <= sp_left;
3424
                                          end case;
3425
                                     right_ctrl <= zero_right;
3426
                                     alu_ctrl   <= alu_add16;
3427
                 ea_ctrl    <= load_ea;
3428
                                          if md(4) = '0' then
3429
                                            st_ctrl      <= pull_st;
3430
                                            next_state   <= saved_state;
3431
                                          else
3432
                                            next_state   <= indirect_state;
3433
                                          end if;
3434
 
3435
                                        when "1000" =>     -- offset8,R
3436
                 md_ctrl    <= fetch_first_md; -- pick up 8 bit offset
3437
                 addr_ctrl  <= fetch_ad;
3438
                 pc_ctrl    <= incr_pc;
3439
                 next_state <= index8_state;
3440
 
3441
                                        when "1001" =>     -- offset16,R
3442
                 md_ctrl    <= fetch_first_md; -- pick up first byte of 16 bit offset
3443
                 addr_ctrl  <= fetch_ad;
3444
                 pc_ctrl    <= incr_pc;
3445
                 next_state <= index16_state;
3446
 
3447
                                        when "1010" =>     -- undefined
3448
                                     case md(6 downto 5) is
3449
                                          when "00" =>
3450
                                  left_ctrl  <= ix_left;
3451
                                          when "01" =>
3452
                                  left_ctrl  <= iy_left;
3453
                                          when "10" =>
3454
                                  left_ctrl  <= up_left;
3455
                                          when others =>
3456
                                          -- when "11" =>
3457
                                  left_ctrl  <= sp_left;
3458
                                          end case;
3459
                                     right_ctrl <= zero_right;
3460
                                     alu_ctrl   <= alu_add16;
3461
                 ea_ctrl    <= load_ea;
3462
                                          --
3463
                                          if md(4) = '0' then
3464
                                            st_ctrl      <= pull_st;
3465
                                            next_state   <= saved_state;
3466
                                          else
3467
                                            next_state   <= indirect_state;
3468
                                          end if;
3469
 
3470
                                        when "1011" =>     -- ACCD,R
3471
                                     case md(6 downto 5) is
3472
                                          when "00" =>
3473
                                  left_ctrl  <= ix_left;
3474
                                          when "01" =>
3475
                                  left_ctrl  <= iy_left;
3476
                                          when "10" =>
3477
                                  left_ctrl  <= up_left;
3478
                                          when others =>
3479
                                          -- when "11" =>
3480
                                  left_ctrl  <= sp_left;
3481
                                          end case;
3482
                                     right_ctrl <= accd_right;
3483
                                     alu_ctrl   <= alu_add16;
3484
                 ea_ctrl    <= load_ea;
3485
                                          if md(4) = '0' then
3486
                                            st_ctrl      <= pull_st;
3487
                                            next_state   <= saved_state;
3488
                                          else
3489
                                            next_state   <= indirect_state;
3490
                                          end if;
3491
 
3492
                                        when "1100" =>     -- offset8,PC
3493
                                          -- fetch 8 bit offset
3494
                 md_ctrl    <= fetch_first_md;
3495
                 addr_ctrl  <= fetch_ad;
3496
                 pc_ctrl    <= incr_pc;
3497
                 next_state <= pcrel8_state;
3498
 
3499
                                        when "1101" =>     -- offset16,PC
3500
                                          -- fetch offset
3501
                 md_ctrl    <= fetch_first_md;
3502
                 addr_ctrl  <= fetch_ad;
3503
                 pc_ctrl    <= incr_pc;
3504
                 next_state <= pcrel16_state;
3505
 
3506
                                        when "1110" =>     -- undefined
3507
                                     case md(6 downto 5) is
3508
                                          when "00" =>
3509
                                  left_ctrl  <= ix_left;
3510
                                          when "01" =>
3511
                                  left_ctrl  <= iy_left;
3512
                                          when "10" =>
3513
                                  left_ctrl  <= up_left;
3514
                                          when others =>
3515
                                          -- when "11" =>
3516
                                  left_ctrl  <= sp_left;
3517
                                          end case;
3518
                                     right_ctrl <= zero_right;
3519
                                     alu_ctrl   <= alu_add16;
3520
                 ea_ctrl    <= load_ea;
3521
                                          if md(4) = '0' then
3522
                                            st_ctrl      <= pull_st;
3523
                                            next_state   <= saved_state;
3524
                                          else
3525
                                            next_state   <= indirect_state;
3526
                                          end if;
3527
 
3528
               when others =>
3529
--                      when "1111" =>     -- [,address]
3530
                                          -- advance PC to pick up address
3531
                 md_ctrl    <= fetch_first_md;
3532
                 addr_ctrl  <= fetch_ad;
3533
                                          pc_ctrl    <= incr_pc;
3534
                 next_state <= indexaddr_state;
3535
                                        end case;
3536
                                 end if;
3537
 
3538
                          -- load index register with ea plus one
3539
                          when postincr1_state =>
3540
                            left_ctrl  <= ea_left;
3541
                            right_ctrl <= one_right;
3542
                            alu_ctrl   <= alu_add16;
3543
                                 case md(6 downto 5) is
3544
                            when "00" =>
3545
               ix_ctrl    <= load_ix;
3546
                                 when "01" =>
3547
               iy_ctrl    <= load_iy;
3548
                                 when "10" =>
3549
               up_ctrl    <= load_up;
3550
                                 when others =>
3551
                                 -- when "11" =>
3552
               sp_ctrl    <= load_sp;
3553
                            end case;
3554
                                 -- return to previous state
3555
                            if md(4) = '0' then
3556
                                         st_ctrl      <= pull_st;
3557
                                         next_state   <= saved_state;
3558
                                 else
3559
                                         next_state   <= indirect_state;
3560
                                 end if;
3561
 
3562
                          -- load index register with ea plus two
3563
                          when postincr2_state =>
3564
                                 -- increment register by two (address)
3565
                            left_ctrl  <= ea_left;
3566
                            right_ctrl <= two_right;
3567
                            alu_ctrl   <= alu_add16;
3568
                                 case md(6 downto 5) is
3569
                            when "00" =>
3570
               ix_ctrl    <= load_ix;
3571
                                 when "01" =>
3572
               iy_ctrl    <= load_iy;
3573
                                 when "10" =>
3574
               up_ctrl    <= load_up;
3575
                                 when others =>
3576
                                 -- when "11" =>
3577
               sp_ctrl    <= load_sp;
3578
                            end case;
3579
                                 -- return to previous state
3580
                            if md(4) = '0' then
3581
                                         st_ctrl      <= pull_st;
3582
                                         next_state   <= saved_state;
3583
                                 else
3584
                                         next_state   <= indirect_state;
3585
                                 end if;
3586
           --
3587
                          -- ea = index register + md (8 bit signed offset)
3588
                          -- ea holds post byte
3589
                          --
3590
                          when index8_state =>
3591
                                 case ea(6 downto 5) is
3592
                            when "00" =>
3593
                              left_ctrl  <= ix_left;
3594
                            when "01" =>
3595
                              left_ctrl  <= iy_left;
3596
                                 when "10" =>
3597
                              left_ctrl  <= up_left;
3598
                                 when others =>
3599
                                 -- when "11" =>
3600
                              left_ctrl  <= sp_left;
3601
                                 end case;
3602
                                 -- ea = index reg + md
3603
                            right_ctrl <= md_sign8_right;
3604
                            alu_ctrl   <= alu_add16;
3605
             ea_ctrl    <= load_ea;
3606
                                 -- return to previous state
3607
                            if ea(4) = '0' then
3608
                                         st_ctrl      <= pull_st;
3609
                                         next_state   <= saved_state;
3610
                                 else
3611
                                         next_state   <= indirect_state;
3612
                                 end if;
3613
 
3614
                          -- fetch low byte of 16 bit indexed offset
3615
                          when index16_state =>
3616
                                 -- advance pc
3617
             pc_ctrl    <= incr_pc;
3618
                                 -- fetch low byte
3619
             md_ctrl    <= fetch_next_md;
3620
             addr_ctrl  <= fetch_ad;
3621
                                 next_state <= index16_2_state;
3622
 
3623
                          -- ea = index register + md (16 bit offset)
3624
                          -- ea holds post byte
3625
                          when index16_2_state =>
3626
                                 case ea(6 downto 5) is
3627
                            when "00" =>
3628
                              left_ctrl  <= ix_left;
3629
                            when "01" =>
3630
                              left_ctrl  <= iy_left;
3631
                                 when "10" =>
3632
                              left_ctrl  <= up_left;
3633
                                 when others =>
3634
                                 -- when "11" =>
3635
                              left_ctrl  <= sp_left;
3636
                                 end case;
3637
                                 -- ea = index reg + md
3638
                            right_ctrl <= md_right;
3639
                            alu_ctrl   <= alu_add16;
3640
             ea_ctrl    <= load_ea;
3641
                                 -- return to previous state
3642
                            if ea(4) = '0' then
3643
                                         st_ctrl      <= pull_st;
3644
                                         next_state   <= saved_state;
3645
                                 else
3646
                                         next_state   <= indirect_state;
3647
                                 end if;
3648
           --
3649
                          -- pc relative with 8 bit signed offest
3650
                          -- md holds signed offset
3651
                          --
3652
                          when pcrel8_state =>
3653
                                 -- ea = pc + signed md
3654
                            left_ctrl  <= pc_left;
3655
                            right_ctrl <= md_sign8_right;
3656
                            alu_ctrl   <= alu_add16;
3657
             ea_ctrl    <= load_ea;
3658
                                 -- return to previous state
3659
                            if ea(4) = '0' then
3660
                                         st_ctrl      <= pull_st;
3661
                                         next_state   <= saved_state;
3662
                                 else
3663
                                         next_state   <= indirect_state;
3664
                                 end if;
3665
 
3666
                          -- pc relative addressing with 16 bit offset
3667
                          -- pick up the low byte of the offset in md
3668
                          -- advance the pc
3669
                          when pcrel16_state =>
3670
                                 -- advance pc
3671
             pc_ctrl    <= incr_pc;
3672
                                 -- fetch low byte
3673
             md_ctrl    <= fetch_next_md;
3674
             addr_ctrl  <= fetch_ad;
3675
                                 next_state <= pcrel16_2_state;
3676
 
3677
                          -- pc relative with16 bit signed offest
3678
                          -- md holds signed offset
3679
                          when pcrel16_2_state =>
3680
                                 -- ea = pc +  md
3681
                            left_ctrl  <= pc_left;
3682
                            right_ctrl <= md_right;
3683
                            alu_ctrl   <= alu_add16;
3684
             ea_ctrl    <= load_ea;
3685
                                 -- return to previous state
3686
                            if ea(4) = '0' then
3687
                                         st_ctrl      <= pull_st;
3688
                                         next_state   <= saved_state;
3689
                                 else
3690
                                         next_state   <= indirect_state;
3691
                                 end if;
3692
 
3693
                          -- indexed to address
3694
                          -- pick up the low byte of the address
3695
                          -- advance the pc
3696
                          when indexaddr_state =>
3697
                                 -- advance pc
3698
             pc_ctrl    <= incr_pc;
3699
                                 -- fetch low byte
3700
             md_ctrl    <= fetch_next_md;
3701
             addr_ctrl  <= fetch_ad;
3702
                                 next_state <= indexaddr2_state;
3703
 
3704
                          -- indexed to absolute address
3705
                          -- md holds address
3706
                          -- ea hold indexing mode byte
3707
                          when indexaddr2_state =>
3708
                                 -- ea = md
3709
                            left_ctrl  <= pc_left;
3710
                            right_ctrl <= md_right;
3711
                            alu_ctrl   <= alu_ld16;
3712
             ea_ctrl    <= load_ea;
3713
                                 -- return to previous state
3714
                            if ea(4) = '0' then
3715
                                         st_ctrl      <= pull_st;
3716
                                         next_state   <= saved_state;
3717
                                 else
3718
                                         next_state   <= indirect_state;
3719
                                 end if;
3720
 
3721
           --
3722
                          -- load md with high byte of indirect address
3723
                          -- pointed to by ea
3724
                          -- increment ea
3725
                          --
3726
                          when indirect_state =>
3727
                                 -- increment ea
3728
                            left_ctrl  <= ea_left;
3729
                            right_ctrl <= one_right;
3730
                            alu_ctrl   <= alu_add16;
3731
             ea_ctrl    <= load_ea;
3732
                                 -- fetch high byte
3733
             md_ctrl    <= fetch_first_md;
3734
             addr_ctrl  <= read_ad;
3735
                                 next_state <= indirect2_state;
3736
           --
3737
                          -- load md with low byte of indirect address
3738
                          -- pointed to by ea
3739
                          -- ea has previously been incremented
3740
                          --
3741
                          when indirect2_state =>
3742
                                 -- fetch high byte
3743
             md_ctrl    <= fetch_next_md;
3744
             addr_ctrl  <= read_ad;
3745
             dout_ctrl  <= md_lo_dout;
3746
                                 next_state <= indirect3_state;
3747
                          --
3748
                          -- complete idirect addressing
3749
                          -- by loading ea with md
3750
                          --
3751
                          when indirect3_state =>
3752
                                 -- load ea with md
3753
                            left_ctrl  <= ea_left;
3754
                            right_ctrl <= md_right;
3755
                            alu_ctrl   <= alu_ld16;
3756
             ea_ctrl    <= load_ea;
3757
                                 -- return to previous state
3758
                                 st_ctrl      <= pull_st;
3759
                                 next_state   <= saved_state;
3760
 
3761
           --
3762
                          -- ea holds the low byte of the absolute address
3763
                          -- Move ea low byte into ea high byte
3764
                          -- load new ea low byte to for absolute 16 bit address
3765
                          -- advance the program counter
3766
                          --
3767
                          when extended_state => -- fetch ea low byte
3768
                                        -- increment pc
3769
               pc_ctrl      <= incr_pc;
3770
                                        -- fetch next effective address bytes
3771
                                        ea_ctrl      <= fetch_next_ea;
3772
               addr_ctrl    <= fetch_ad;
3773
                                   -- return to previous state
3774
                                   st_ctrl      <= pull_st;
3775
                                   next_state   <= saved_state;
3776
 
3777
                                when lea_state => -- here on load effective address
3778
                                        -- load index register with effective address
3779
               left_ctrl  <= pc_left;
3780
                                        right_ctrl <= ea_right;
3781
                                   alu_ctrl   <= alu_lea;
3782
                                        case op_code(3 downto 0) is
3783
                                        when "0000" => -- leax
3784
                   cc_ctrl    <= load_cc;
3785
                   ix_ctrl    <= load_ix;
3786
                                        when "0001" => -- leay
3787
                   cc_ctrl    <= load_cc;
3788
                   iy_ctrl    <= load_iy;
3789
                                        when "0010" => -- leas
3790
                   sp_ctrl    <= load_sp;
3791
                                        when "0011" => -- leau
3792
                   up_ctrl    <= load_up;
3793
                                        when others =>
3794
                                            null;
3795
                                        end case;
3796
               lic          <= '1';
3797
               next_state   <= fetch_state;
3798
 
3799
                                --
3800
                                -- jump to subroutine
3801
                                -- sp=sp-1
3802
                                -- call push_return_lo_state to save pc
3803
                                -- return to jmp_state
3804
                                --
3805
                                when jsr_state =>
3806
                                        -- decrement sp
3807
               left_ctrl    <= sp_left;
3808
                                        right_ctrl   <= one_right;
3809
                                   alu_ctrl     <= alu_sub16;
3810
               sp_ctrl      <= load_sp;
3811
                                        -- call push_return_state
3812
                                        st_ctrl      <= push_st;
3813
                                        return_state <= jmp_state;
3814
               next_state   <= push_return_lo_state;
3815
 
3816
                                --
3817
                                -- Load pc with ea
3818
                                -- (JMP)
3819
                                --
3820
                                when jmp_state =>
3821
                                        -- load PC with effective address
3822
               left_ctrl  <= pc_left;
3823
                                        right_ctrl <= ea_right;
3824
                                   alu_ctrl   <= alu_ld16;
3825
                                        pc_ctrl    <= load_pc;
3826
               lic        <= '1';
3827
               next_state <= fetch_state;
3828
 
3829
                                --
3830
                                -- long branch or branch to subroutine
3831
                                -- pick up next md byte
3832
                                -- md_hi = md_lo
3833
                                -- md_lo = (pc)
3834
                                -- pc=pc+1
3835
                                -- if a lbsr push return address
3836
                                -- continue to sbranch_state
3837
                                -- to evaluate conditional branches
3838
                                --
3839
                                when lbranch_state =>
3840
                                        pc_ctrl    <= incr_pc;
3841
                                        -- fetch the next byte into md_lo
3842
               md_ctrl    <= fetch_next_md;
3843
               addr_ctrl  <= fetch_ad;
3844
                                        -- if lbsr - push return address
3845
                                        -- then continue on to short branch
3846
                                        if op_code = "00010111" then
3847
                                          st_ctrl      <= push_st;
3848
                                          return_state <= sbranch_state;
3849
                 next_state   <= push_return_lo_state;
3850
                                        else
3851
                 next_state   <= sbranch_state;
3852
                                        end if;
3853
 
3854
                                 --
3855
                                 -- here to execute conditional branch
3856
                                 -- short conditional branch md = signed 8 bit offset
3857
                                 -- long branch md = 16 bit offset
3858
                                 -- 
3859
                  when sbranch_state =>
3860
               left_ctrl  <= pc_left;
3861
                                        right_ctrl <= md_right;
3862
                                   alu_ctrl   <= alu_add16;
3863
                                        -- Test condition for branch
3864
                              if op_code(7 downto 4) = "0010" then -- conditional branch
3865
                 case op_code(3 downto 0) is
3866
                           when "0000" => -- bra
3867
                                            cond_true := (1 = 1);
3868
                           when "0001" => -- brn
3869
                                            cond_true := (1 = 0);
3870
                           when "0010" => -- bhi
3871
                                            cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
3872
                           when "0011" => -- bls
3873
                                            cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
3874
                           when "0100" => -- bcc/bhs
3875
                                            cond_true := (cc(CBIT) = '0');
3876
                           when "0101" => -- bcs/blo
3877
                                            cond_true := (cc(CBIT) = '1');
3878
                           when "0110" => -- bne
3879
                             cond_true := (cc(ZBIT) = '0');
3880
                           when "0111" => -- beq
3881
                                            cond_true := (cc(ZBIT) = '1');
3882
                           when "1000" => -- bvc
3883
                                            cond_true := (cc(VBIT) = '0');
3884
                           when "1001" => -- bvs
3885
                                            cond_true := (cc(VBIT) = '1');
3886
                           when "1010" => -- bpl
3887
                                            cond_true := (cc(NBIT) = '0');
3888
                           when "1011" => -- bmi
3889
                                            cond_true := (cc(NBIT) = '1');
3890
                           when "1100" => -- bge
3891
                                            cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
3892
                           when "1101" => -- blt
3893
                                            cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
3894
                           when "1110" => -- bgt
3895
                                            cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
3896
                           when "1111" => -- ble
3897
                                            cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
3898
                           when others =>
3899
                                            null;
3900
                           end case;
3901
                                        else
3902
                                          cond_true := (1 = 1); -- lbra, lbsr, bsr
3903
                                   end if;
3904
                                        if cond_true then
3905
                                          pc_ctrl    <= load_pc;
3906
               end if;
3907
               lic          <= '1';
3908
                                        next_state   <= fetch_state;
3909
 
3910
                                 --
3911
                                 -- push return address onto the S stack
3912
                                 --
3913
                                 -- (sp) = pc_lo
3914
                                 -- sp = sp - 1
3915
                                 --
3916
                                 when push_return_lo_state =>
3917
                                          -- decrement the sp
3918
                 left_ctrl  <= sp_left;
3919
                 right_ctrl <= one_right;
3920
                 alu_ctrl   <= alu_sub16;
3921
                 sp_ctrl    <= load_sp;
3922
                 -- write PC low
3923
                 addr_ctrl  <= pushs_ad;
3924
                 dout_ctrl  <= pc_lo_dout;
3925
                 next_state <= push_return_hi_state;
3926
 
3927
                                --
3928
                                -- push program counter hi byte onto the stack
3929
                                -- (sp) = pc_hi
3930
                                -- sp = sp
3931
                                -- return to originating state
3932
                                --
3933
                                when push_return_hi_state =>
3934
                                          -- write pc hi bytes
3935
                 addr_ctrl    <= pushs_ad;
3936
                 dout_ctrl    <= pc_hi_dout;
3937
                                          st_ctrl      <= pull_st;
3938
                 next_state   <= saved_state;
3939
 
3940
                                 when pull_return_hi_state =>
3941
                                          -- increment the sp
3942
                 left_ctrl  <= sp_left;
3943
                 right_ctrl <= one_right;
3944
                 alu_ctrl   <= alu_add16;
3945
                 sp_ctrl    <= load_sp;
3946
                 -- read pc hi
3947
                                          pc_ctrl    <= pull_hi_pc;
3948
                 addr_ctrl  <= pulls_ad;
3949
                 next_state <= pull_return_lo_state;
3950
 
3951
                                when pull_return_lo_state =>
3952
                                          -- increment the SP
3953
                 left_ctrl  <= sp_left;
3954
                 right_ctrl <= one_right;
3955
                 alu_ctrl   <= alu_add16;
3956
                 sp_ctrl    <= load_sp;
3957
                                          -- read pc low
3958
                                          pc_ctrl    <= pull_lo_pc;
3959
                 addr_ctrl  <= pulls_ad;
3960
                 dout_ctrl  <= pc_lo_dout;
3961
                                          --
3962
                                          st_ctrl      <= pull_st;
3963
                 lic          <= '1';
3964
                 next_state   <= saved_state;
3965
 
3966
                                 when andcc_state =>
3967
                                          -- AND CC with md
3968
                 left_ctrl  <= md_left;
3969
                 right_ctrl <= zero_right;
3970
                 alu_ctrl   <= alu_andcc;
3971
                 cc_ctrl    <= load_cc;
3972
                                          --
3973
                                          st_ctrl    <= pull_st;
3974
                 lic        <= '1';
3975
                                     next_state <= saved_state;
3976
 
3977
                                 when orcc_state =>
3978
                                          -- OR CC with md
3979
                 left_ctrl  <= md_left;
3980
                 right_ctrl <= zero_right;
3981
                 alu_ctrl   <= alu_orcc;
3982
                 cc_ctrl    <= load_cc;
3983
                                          --
3984
                                          st_ctrl    <= pull_st;
3985
                 lic        <= '1';
3986
                                     next_state <= saved_state;
3987
 
3988
                                 when tfr_state =>
3989
                                          -- select source register
3990
                                          case md(7 downto 4) is
3991
                                          when "0000" =>
3992
                                            left_ctrl <= accd_left;
3993
                                          when "0001" =>
3994
                                            left_ctrl <= ix_left;
3995
                                          when "0010" =>
3996
                                            left_ctrl <= iy_left;
3997
                                          when "0011" =>
3998
                                            left_ctrl <= up_left;
3999
                                          when "0100" =>
4000
                                            left_ctrl <= sp_left;
4001
                                          when "0101" =>
4002
                                            left_ctrl <= pc_left;
4003
                                          when "1000" =>
4004
                                            left_ctrl <= acca_left;
4005
                                          when "1001" =>
4006
                                            left_ctrl <= accb_left;
4007
                                          when "1010" =>
4008
                                            left_ctrl <= cc_left;
4009
                                          when "1011" =>
4010
                                            left_ctrl <= dp_left;
4011
                                          when others =>
4012
                   left_ctrl  <= md_left;
4013
                                          end case;
4014
                 right_ctrl <= zero_right;
4015
                 alu_ctrl   <= alu_tfr;
4016
                                          -- select destination register
4017
                                          case md(3 downto 0) is
4018
                                          when "0000" => -- accd
4019
                   acca_ctrl  <= load_hi_acca;
4020
                   accb_ctrl  <= load_accb;
4021
                                          when "0001" => -- ix
4022
                   ix_ctrl    <= load_ix;
4023
                                          when "0010" => -- iy
4024
                   iy_ctrl    <= load_iy;
4025
                                          when "0011" => -- up
4026
                   up_ctrl    <= load_up;
4027
                                          when "0100" => -- sp
4028
                   sp_ctrl    <= load_sp;
4029
                                          when "0101" => -- pc
4030
                   pc_ctrl    <= load_pc;
4031
                                          when "1000" => -- acca
4032
                   acca_ctrl  <= load_acca;
4033
                                          when "1001" => -- accb
4034
                   accb_ctrl  <= load_accb;
4035
                                          when "1010" => -- cc
4036
                   cc_ctrl    <= load_cc;
4037
                                          when "1011" => --dp
4038
                   dp_ctrl    <= load_dp;
4039
                                          when others =>
4040
                                            null;
4041
                                          end case;
4042
                                          --
4043
                                          st_ctrl      <= pull_st;
4044
                 lic          <= '1';
4045
                                     next_state   <= saved_state;
4046
 
4047
                                 when exg_state =>
4048
                                          -- save destination register
4049
                                          case md(3 downto 0) is
4050
                                          when "0000" =>
4051
                                            left_ctrl <= accd_left;
4052
                                          when "0001" =>
4053
                                            left_ctrl <= ix_left;
4054
                                          when "0010" =>
4055
                                            left_ctrl <= iy_left;
4056
                                          when "0011" =>
4057
                                            left_ctrl <= up_left;
4058
                                          when "0100" =>
4059
                                            left_ctrl <= sp_left;
4060
                                          when "0101" =>
4061
                                            left_ctrl <= pc_left;
4062
                                          when "1000" =>
4063
                                            left_ctrl <= acca_left;
4064
                                          when "1001" =>
4065
                                            left_ctrl <= accb_left;
4066
                                          when "1010" =>
4067
                                            left_ctrl <= cc_left;
4068
                                          when "1011" =>
4069
                                            left_ctrl <= dp_left;
4070
                                          when others =>
4071
                   left_ctrl  <= md_left;
4072
                                          end case;
4073
                 right_ctrl <= zero_right;
4074
                 alu_ctrl   <= alu_tfr;
4075
                 ea_ctrl    <= load_ea;
4076
                                          -- call tranfer microcode
4077
                                          st_ctrl      <= push_st;
4078
                                          return_state <= exg1_state;
4079
                                     next_state   <= tfr_state;
4080
 
4081
                                 when exg1_state =>
4082
                                          -- restore destination
4083
                 left_ctrl  <= ea_left;
4084
                 right_ctrl <= zero_right;
4085
                 alu_ctrl   <= alu_tfr;
4086
                                          -- save as source register
4087
                                          case md(7 downto 4) is
4088
                                          when "0000" => -- accd
4089
                   acca_ctrl  <= load_hi_acca;
4090
                   accb_ctrl  <= load_accb;
4091
                                          when "0001" => -- ix
4092
                   ix_ctrl    <= load_ix;
4093
                                          when "0010" => -- iy
4094
                   iy_ctrl    <= load_iy;
4095
                                          when "0011" => -- up
4096
                   up_ctrl    <= load_up;
4097
                                          when "0100" => -- sp
4098
                   sp_ctrl    <= load_sp;
4099
                                          when "0101" => -- pc
4100
                   pc_ctrl    <= load_pc;
4101
                                          when "1000" => -- acca
4102
                   acca_ctrl  <= load_acca;
4103
                                          when "1001" => -- accb
4104
                   accb_ctrl  <= load_accb;
4105
                                          when "1010" => -- cc
4106
                   cc_ctrl    <= load_cc;
4107
                                          when "1011" => --dp
4108
                   dp_ctrl    <= load_dp;
4109
                                          when others =>
4110
                                            null;
4111
                                          end case;
4112
                 lic          <= '1';
4113
                                     next_state   <= fetch_state;
4114
 
4115
                                 when mul_state =>
4116
                                          -- move acca to md
4117
                 left_ctrl  <= acca_left;
4118
                 right_ctrl <= zero_right;
4119
                 alu_ctrl   <= alu_st16;
4120
                 md_ctrl    <= load_md;
4121
                                     next_state <= mulea_state;
4122
 
4123
                                 when mulea_state =>
4124
                                          -- move accb to ea
4125
                 left_ctrl  <= accb_left;
4126
                 right_ctrl <= zero_right;
4127
                 alu_ctrl   <= alu_st16;
4128
                 ea_ctrl    <= load_ea;
4129
                                     next_state <= muld_state;
4130
 
4131
                                 when muld_state =>
4132
                                          -- clear accd
4133
                 left_ctrl  <= acca_left;
4134
                 right_ctrl <= zero_right;
4135
                 alu_ctrl   <= alu_ld8;
4136
                 acca_ctrl  <= load_hi_acca;
4137
                 accb_ctrl  <= load_accb;
4138
                                     next_state <= mul0_state;
4139
 
4140
                                 when mul0_state =>
4141
                                          -- if bit 0 of ea set, add accd to md
4142
                 left_ctrl  <= accd_left;
4143
                                          if ea(0) = '1' then
4144
                   right_ctrl <= md_right;
4145
                                          else
4146
                   right_ctrl <= zero_right;
4147
                                          end if;
4148
                 alu_ctrl   <= alu_mul;
4149
                 cc_ctrl    <= load_cc;
4150
                 acca_ctrl  <= load_hi_acca;
4151
                 accb_ctrl  <= load_accb;
4152
                 md_ctrl    <= shiftl_md;
4153
                                     next_state <= mul1_state;
4154
 
4155
                                 when mul1_state =>
4156
                                          -- if bit 1 of ea set, add accd to md
4157
                 left_ctrl  <= accd_left;
4158
                                          if ea(1) = '1' then
4159
                   right_ctrl <= md_right;
4160
                                          else
4161
                   right_ctrl <= zero_right;
4162
                                          end if;
4163
                 alu_ctrl   <= alu_mul;
4164
                 cc_ctrl    <= load_cc;
4165
                 acca_ctrl  <= load_hi_acca;
4166
                 accb_ctrl  <= load_accb;
4167
                 md_ctrl    <= shiftl_md;
4168
                                     next_state <= mul2_state;
4169
 
4170
                                 when mul2_state =>
4171
                                          -- if bit 2 of ea set, add accd to md
4172
                 left_ctrl  <= accd_left;
4173
                                          if ea(2) = '1' then
4174
                   right_ctrl <= md_right;
4175
                                          else
4176
                   right_ctrl <= zero_right;
4177
                                          end if;
4178
                 alu_ctrl   <= alu_mul;
4179
                 cc_ctrl    <= load_cc;
4180
                 acca_ctrl  <= load_hi_acca;
4181
                 accb_ctrl  <= load_accb;
4182
                 md_ctrl    <= shiftl_md;
4183
                                     next_state <= mul3_state;
4184
 
4185
                                 when mul3_state =>
4186
                                          -- if bit 3 of ea set, add accd to md
4187
                 left_ctrl  <= accd_left;
4188
                                          if ea(3) = '1' then
4189
                   right_ctrl <= md_right;
4190
                                          else
4191
                   right_ctrl <= zero_right;
4192
                                          end if;
4193
                 alu_ctrl   <= alu_mul;
4194
                 cc_ctrl    <= load_cc;
4195
                 acca_ctrl  <= load_hi_acca;
4196
                 accb_ctrl  <= load_accb;
4197
                 md_ctrl    <= shiftl_md;
4198
                                     next_state <= mul4_state;
4199
 
4200
                                 when mul4_state =>
4201
                                          -- if bit 4 of ea set, add accd to md
4202
                 left_ctrl  <= accd_left;
4203
                                          if ea(4) = '1' then
4204
                   right_ctrl <= md_right;
4205
                                          else
4206
                   right_ctrl <= zero_right;
4207
                                          end if;
4208
                 alu_ctrl   <= alu_mul;
4209
                 cc_ctrl    <= load_cc;
4210
                 acca_ctrl  <= load_hi_acca;
4211
                 accb_ctrl  <= load_accb;
4212
                 md_ctrl    <= shiftl_md;
4213
                                     next_state <= mul5_state;
4214
 
4215
                                 when mul5_state =>
4216
                                          -- if bit 5 of ea set, add accd to md
4217
                 left_ctrl  <= accd_left;
4218
                                          if ea(5) = '1' then
4219
                   right_ctrl <= md_right;
4220
                                          else
4221
                   right_ctrl <= zero_right;
4222
                                          end if;
4223
                 alu_ctrl   <= alu_mul;
4224
                 cc_ctrl    <= load_cc;
4225
                 acca_ctrl  <= load_hi_acca;
4226
                 accb_ctrl  <= load_accb;
4227
                 md_ctrl    <= shiftl_md;
4228
                                     next_state <= mul6_state;
4229
 
4230
                                 when mul6_state =>
4231
                                          -- if bit 6 of ea set, add accd to md
4232
                 left_ctrl  <= accd_left;
4233
                                          if ea(6) = '1' then
4234
                   right_ctrl <= md_right;
4235
                                          else
4236
                   right_ctrl <= zero_right;
4237
                                          end if;
4238
                 alu_ctrl   <= alu_mul;
4239
                 cc_ctrl    <= load_cc;
4240
                 acca_ctrl  <= load_hi_acca;
4241
                 accb_ctrl  <= load_accb;
4242
                 md_ctrl    <= shiftl_md;
4243
                                     next_state <= mul7_state;
4244
 
4245
                                 when mul7_state =>
4246
                                          -- if bit 7 of ea set, add accd to md
4247
                 left_ctrl  <= accd_left;
4248
                                          if ea(7) = '1' then
4249
                   right_ctrl <= md_right;
4250
                                          else
4251
                   right_ctrl <= zero_right;
4252
                                          end if;
4253
                 alu_ctrl   <= alu_mul;
4254
                 cc_ctrl    <= load_cc;
4255
                 acca_ctrl  <= load_hi_acca;
4256
                 accb_ctrl  <= load_accb;
4257
                 md_ctrl    <= shiftl_md;
4258
                 lic          <= '1';
4259
                                     next_state <= fetch_state;
4260
 
4261
                          --
4262
                          -- Enter here on pushs
4263
                          -- ea holds post byte
4264
                          --
4265
                          when pshs_state =>
4266
             -- decrement sp if any registers to be pushed
4267
             left_ctrl  <= sp_left;
4268
             right_ctrl <= one_right;
4269
             alu_ctrl   <= alu_sub16;
4270
                                 -- idle        address
4271
             addr_ctrl  <= idle_ad;
4272
                            dout_ctrl  <= cc_dout;
4273
                                 if ea(7 downto 0) = "00000000" then
4274
               sp_ctrl    <= latch_sp;
4275
                                 else
4276
               sp_ctrl    <= load_sp;
4277
                                 end if;
4278
                                 if ea(7) = '1' then
4279
               next_state <= pshs_pcl_state;
4280
                                 elsif ea(6) = '1' then
4281
               next_state <= pshs_upl_state;
4282
                                 elsif ea(5) = '1' then
4283
                                   next_state <= pshs_iyl_state;
4284
                                 elsif ea(4) = '1' then
4285
                                   next_state <= pshs_ixl_state;
4286
                                 elsif ea(3) = '1' then
4287
                                   next_state <= pshs_dp_state;
4288
                                 elsif ea(2) = '1' then
4289
                                   next_state <= pshs_accb_state;
4290
                                 elsif ea(1) = '1' then
4291
                                   next_state <= pshs_acca_state;
4292
                                 elsif ea(0) = '1' then
4293
                                   next_state <= pshs_cc_state;
4294
                                 else
4295
               lic        <= '1';
4296
                                   next_state <= fetch_state;
4297
                                 end if;
4298
 
4299
                          when pshs_pcl_state =>
4300
             -- decrement sp
4301
             left_ctrl  <= sp_left;
4302
             right_ctrl <= one_right;
4303
             alu_ctrl   <= alu_sub16;
4304
             sp_ctrl    <= load_sp;
4305
                                 -- write pc low
4306
             addr_ctrl  <= pushs_ad;
4307
                            dout_ctrl  <= pc_lo_dout;
4308
             next_state <= pshs_pch_state;
4309
 
4310
                          when pshs_pch_state =>
4311
             -- decrement sp
4312
             left_ctrl  <= sp_left;
4313
             right_ctrl <= one_right;
4314
             alu_ctrl   <= alu_sub16;
4315
                                 if ea(6 downto 0) = "0000000" then
4316
               sp_ctrl    <= latch_sp;
4317
                                 else
4318
               sp_ctrl    <= load_sp;
4319
                                 end if;
4320
                                 -- write pc hi
4321
             addr_ctrl  <= pushs_ad;
4322
                            dout_ctrl  <= pc_hi_dout;
4323
                                 if ea(6) = '1' then
4324
               next_state <= pshs_upl_state;
4325
                                 elsif ea(5) = '1' then
4326
                                   next_state <= pshs_iyl_state;
4327
                                 elsif ea(4) = '1' then
4328
                                   next_state <= pshs_ixl_state;
4329
                                 elsif ea(3) = '1' then
4330
                                   next_state <= pshs_dp_state;
4331
                                 elsif ea(2) = '1' then
4332
                                   next_state <= pshs_accb_state;
4333
                                 elsif ea(1) = '1' then
4334
                                   next_state <= pshs_acca_state;
4335
                                 elsif ea(0) = '1' then
4336
                                   next_state <= pshs_cc_state;
4337
                                 else
4338
               lic        <= '1';
4339
                                   next_state <= fetch_state;
4340
                                 end if;
4341
 
4342
 
4343
                          when pshs_upl_state =>
4344
             -- decrement sp
4345
             left_ctrl  <= sp_left;
4346
             right_ctrl <= one_right;
4347
             alu_ctrl   <= alu_sub16;
4348
             sp_ctrl    <= load_sp;
4349
                                 -- write pc low
4350
             addr_ctrl  <= pushs_ad;
4351
                            dout_ctrl  <= up_lo_dout;
4352
             next_state <= pshs_uph_state;
4353
 
4354
                          when pshs_uph_state =>
4355
             -- decrement sp
4356
             left_ctrl  <= sp_left;
4357
             right_ctrl <= one_right;
4358
             alu_ctrl   <= alu_sub16;
4359
                                 if ea(5 downto 0) = "000000" then
4360
               sp_ctrl    <= latch_sp;
4361
                                 else
4362
               sp_ctrl    <= load_sp;
4363
                                 end if;
4364
                                 -- write pc hi
4365
             addr_ctrl  <= pushs_ad;
4366
                            dout_ctrl  <= up_hi_dout;
4367
                                 if ea(5) = '1' then
4368
                                   next_state   <= pshs_iyl_state;
4369
                                 elsif ea(4) = '1' then
4370
                                   next_state   <= pshs_ixl_state;
4371
                                 elsif ea(3) = '1' then
4372
                                   next_state   <= pshs_dp_state;
4373
                                 elsif ea(2) = '1' then
4374
                                   next_state   <= pshs_accb_state;
4375
                                 elsif ea(1) = '1' then
4376
                                   next_state   <= pshs_acca_state;
4377
                                 elsif ea(0) = '1' then
4378
                                   next_state   <= pshs_cc_state;
4379
                                 else
4380
               lic          <= '1';
4381
                                   next_state   <= fetch_state;
4382
                                 end if;
4383
 
4384
                          when pshs_iyl_state =>
4385
             -- decrement sp
4386
             left_ctrl  <= sp_left;
4387
             right_ctrl <= one_right;
4388
             alu_ctrl   <= alu_sub16;
4389
             sp_ctrl    <= load_sp;
4390
                                 -- write iy low
4391
             addr_ctrl  <= pushs_ad;
4392
                            dout_ctrl  <= iy_lo_dout;
4393
             next_state <= pshs_iyh_state;
4394
 
4395
                          when pshs_iyh_state =>
4396
             -- decrement sp
4397
             left_ctrl  <= sp_left;
4398
             right_ctrl <= one_right;
4399
             alu_ctrl   <= alu_sub16;
4400
                                 if ea(4 downto 0) = "00000" then
4401
               sp_ctrl    <= latch_sp;
4402
                                 else
4403
               sp_ctrl    <= load_sp;
4404
                                 end if;
4405
                                 -- write iy hi
4406
             addr_ctrl  <= pushs_ad;
4407
                            dout_ctrl  <= iy_hi_dout;
4408
                                 if ea(4) = '1' then
4409
                                   next_state   <= pshs_ixl_state;
4410
                                 elsif ea(3) = '1' then
4411
                                   next_state   <= pshs_dp_state;
4412
                                 elsif ea(2) = '1' then
4413
                                   next_state   <= pshs_accb_state;
4414
                                 elsif ea(1) = '1' then
4415
                                   next_state   <= pshs_acca_state;
4416
                                 elsif ea(0) = '1' then
4417
                                   next_state   <= pshs_cc_state;
4418
                                 else
4419
               lic          <= '1';
4420
                                   next_state   <= fetch_state;
4421
                                 end if;
4422
 
4423
                          when pshs_ixl_state =>
4424
             -- decrement sp
4425
             left_ctrl  <= sp_left;
4426
             right_ctrl <= one_right;
4427
             alu_ctrl   <= alu_sub16;
4428
             sp_ctrl    <= load_sp;
4429
                                 -- write ix low
4430
             addr_ctrl  <= pushs_ad;
4431
                            dout_ctrl  <= ix_lo_dout;
4432
             next_state <= pshs_ixh_state;
4433
 
4434
                          when pshs_ixh_state =>
4435
             -- decrement sp
4436
             left_ctrl  <= sp_left;
4437
             right_ctrl <= one_right;
4438
             alu_ctrl   <= alu_sub16;
4439
                                 if ea(3 downto 0) = "0000" then
4440
               sp_ctrl    <= latch_sp;
4441
                                 else
4442
               sp_ctrl    <= load_sp;
4443
                                 end if;
4444
                                 -- write ix hi
4445
             addr_ctrl  <= pushs_ad;
4446
                            dout_ctrl  <= ix_hi_dout;
4447
                                 if ea(3) = '1' then
4448
                                   next_state   <= pshs_dp_state;
4449
                                 elsif ea(2) = '1' then
4450
                                   next_state   <= pshs_accb_state;
4451
                                 elsif ea(1) = '1' then
4452
                                   next_state   <= pshs_acca_state;
4453
                                 elsif ea(0) = '1' then
4454
                                   next_state   <= pshs_cc_state;
4455
                                 else
4456
               lic          <= '1';
4457
                                   next_state   <= fetch_state;
4458
                                 end if;
4459
 
4460
                          when pshs_dp_state =>
4461
             -- decrement sp
4462
             left_ctrl  <= sp_left;
4463
             right_ctrl <= one_right;
4464
             alu_ctrl   <= alu_sub16;
4465
                                 if ea(2 downto 0) = "000" then
4466
               sp_ctrl    <= latch_sp;
4467
                                 else
4468
               sp_ctrl    <= load_sp;
4469
                                 end if;
4470
                                 -- write dp
4471
             addr_ctrl  <= pushs_ad;
4472
                            dout_ctrl  <= dp_dout;
4473
                                 if ea(2) = '1' then
4474
                                   next_state   <= pshs_accb_state;
4475
                                 elsif ea(1) = '1' then
4476
                                   next_state   <= pshs_acca_state;
4477
                                 elsif ea(0) = '1' then
4478
                                   next_state   <= pshs_cc_state;
4479
                                 else
4480
               lic          <= '1';
4481
                                   next_state   <= fetch_state;
4482
                                 end if;
4483
 
4484
                          when pshs_accb_state =>
4485
             -- decrement sp
4486
             left_ctrl  <= sp_left;
4487
             right_ctrl <= one_right;
4488
             alu_ctrl   <= alu_sub16;
4489
                                 if ea(1 downto 0) = "00" then
4490
               sp_ctrl    <= latch_sp;
4491
                                 else
4492
               sp_ctrl    <= load_sp;
4493
                                 end if;
4494
                                 -- write accb
4495
             addr_ctrl  <= pushs_ad;
4496
                            dout_ctrl  <= accb_dout;
4497
                                 if ea(1) = '1' then
4498
                                   next_state   <= pshs_acca_state;
4499
                                 elsif ea(0) = '1' then
4500
                                   next_state   <= pshs_cc_state;
4501
                                 else
4502
               lic          <= '1';
4503
                                   next_state   <= fetch_state;
4504
                                 end if;
4505
 
4506
                          when pshs_acca_state =>
4507
             -- decrement sp
4508
             left_ctrl  <= sp_left;
4509
             right_ctrl <= one_right;
4510
             alu_ctrl   <= alu_sub16;
4511
                                 if ea(0) = '1' then
4512
               sp_ctrl    <= load_sp;
4513
                                 else
4514
               sp_ctrl    <= latch_sp;
4515
                                 end if;
4516
                                 -- write acca
4517
             addr_ctrl  <= pushs_ad;
4518
                            dout_ctrl  <= acca_dout;
4519
                                 if ea(0) = '1' then
4520
                                   next_state   <= pshs_cc_state;
4521
                                 else
4522
               lic          <= '1';
4523
                                   next_state   <= fetch_state;
4524
                                 end if;
4525
 
4526
                          when pshs_cc_state =>
4527
             -- idle sp
4528
                                 -- write cc
4529
             addr_ctrl  <= pushs_ad;
4530
                            dout_ctrl  <= cc_dout;
4531
             lic          <= '1';
4532
             next_state <= fetch_state;
4533
 
4534
                          --
4535
                          -- enter here on PULS
4536
                          -- ea hold register mask
4537
                          --
4538
                          when puls_state =>
4539
                                 if ea(0) = '1' then
4540
                                   next_state <= puls_cc_state;
4541
                                 elsif ea(1) = '1' then
4542
                                   next_state <= puls_acca_state;
4543
                                 elsif ea(2) = '1' then
4544
                                   next_state <= puls_accb_state;
4545
                                 elsif ea(3) = '1' then
4546
                                   next_state <= puls_dp_state;
4547
                                 elsif ea(4) = '1' then
4548
                                   next_state <= puls_ixh_state;
4549
                                 elsif ea(5) = '1' then
4550
                                   next_state <= puls_iyh_state;
4551
                                 elsif ea(6) = '1' then
4552
               next_state <= puls_uph_state;
4553
                                 elsif ea(7) = '1' then
4554
               next_state <= puls_pch_state;
4555
                                 else
4556
               lic        <= '1';
4557
                                   next_state <= fetch_state;
4558
                                 end if;
4559
 
4560
                          when puls_cc_state =>
4561
                                 -- increment sp
4562
             left_ctrl  <= sp_left;
4563
             right_ctrl <= one_right;
4564
             alu_ctrl   <= alu_add16;
4565
             sp_ctrl    <= load_sp;
4566
                                 -- read cc
4567
             cc_ctrl    <= pull_cc;
4568
             addr_ctrl  <= pulls_ad;
4569
                                 if ea(1) = '1' then
4570
                                   next_state <= puls_acca_state;
4571
                                 elsif ea(2) = '1' then
4572
                                   next_state <= puls_accb_state;
4573
                                 elsif ea(3) = '1' then
4574
                                   next_state <= puls_dp_state;
4575
                                 elsif ea(4) = '1' then
4576
                                   next_state <= puls_ixh_state;
4577
                                 elsif ea(5) = '1' then
4578
                                   next_state <= puls_iyh_state;
4579
                                 elsif ea(6) = '1' then
4580
               next_state <= puls_uph_state;
4581
                                 elsif ea(7) = '1' then
4582
               next_state <= puls_pch_state;
4583
                                 else
4584
               lic        <= '1';
4585
                                   next_state <= fetch_state;
4586
                                 end if;
4587
 
4588
                          when puls_acca_state =>
4589
                                 -- increment sp
4590
             left_ctrl  <= sp_left;
4591
             right_ctrl <= one_right;
4592
             alu_ctrl   <= alu_add16;
4593
             sp_ctrl    <= load_sp;
4594
                                 -- read acca
4595
                                 acca_ctrl  <= pull_acca;
4596
             addr_ctrl  <= pulls_ad;
4597
                                 if ea(2) = '1' then
4598
                                   next_state <= puls_accb_state;
4599
                                 elsif ea(3) = '1' then
4600
                                   next_state <= puls_dp_state;
4601
                                 elsif ea(4) = '1' then
4602
                                   next_state <= puls_ixh_state;
4603
                                 elsif ea(5) = '1' then
4604
                                   next_state <= puls_iyh_state;
4605
                                 elsif ea(6) = '1' then
4606
               next_state <= puls_uph_state;
4607
                                 elsif ea(7) = '1' then
4608
               next_state <= puls_pch_state;
4609
                                 else
4610
               lic          <= '1';
4611
                                   next_state <= fetch_state;
4612
                                 end if;
4613
 
4614
                          when puls_accb_state =>
4615
                                 -- increment sp
4616
             left_ctrl  <= sp_left;
4617
             right_ctrl <= one_right;
4618
             alu_ctrl   <= alu_add16;
4619
             sp_ctrl    <= load_sp;
4620
                                 -- read accb
4621
                                 accb_ctrl  <= pull_accb;
4622
             addr_ctrl  <= pulls_ad;
4623
                                 if ea(3) = '1' then
4624
                                   next_state <= puls_dp_state;
4625
                                 elsif ea(4) = '1' then
4626
                                   next_state <= puls_ixh_state;
4627
                                 elsif ea(5) = '1' then
4628
                                   next_state <= puls_iyh_state;
4629
                                 elsif ea(6) = '1' then
4630
               next_state <= puls_uph_state;
4631
                                 elsif ea(7) = '1' then
4632
               next_state <= puls_pch_state;
4633
                                 else
4634
               lic        <= '1';
4635
                                   next_state <= fetch_state;
4636
                                 end if;
4637
 
4638
                          when puls_dp_state =>
4639
                                 -- increment sp
4640
             left_ctrl  <= sp_left;
4641
             right_ctrl <= one_right;
4642
             alu_ctrl   <= alu_add16;
4643
             sp_ctrl    <= load_sp;
4644
                                 -- read dp
4645
                                 dp_ctrl    <= pull_dp;
4646
             addr_ctrl  <= pulls_ad;
4647
                                 if ea(4) = '1' then
4648
                                   next_state <= puls_ixh_state;
4649
                                 elsif ea(5) = '1' then
4650
                                   next_state <= puls_iyh_state;
4651
                                 elsif ea(6) = '1' then
4652
               next_state <= puls_uph_state;
4653
                                 elsif ea(7) = '1' then
4654
               next_state <= puls_pch_state;
4655
                                 else
4656
               lic        <= '1';
4657
                                   next_state <= fetch_state;
4658
                                 end if;
4659
 
4660
                          when puls_ixh_state =>
4661
             -- increment sp
4662
             left_ctrl  <= sp_left;
4663
             right_ctrl <= one_right;
4664
             alu_ctrl   <= alu_add16;
4665
             sp_ctrl    <= load_sp;
4666
                                 -- pull ix hi
4667
                                 ix_ctrl    <= pull_hi_ix;
4668
             addr_ctrl  <= pulls_ad;
4669
             next_state <= puls_ixl_state;
4670
 
4671
                          when puls_ixl_state =>
4672
                                 -- increment sp
4673
             left_ctrl  <= sp_left;
4674
             right_ctrl <= one_right;
4675
             alu_ctrl   <= alu_add16;
4676
             sp_ctrl    <= load_sp;
4677
                                 -- read ix low
4678
                                 ix_ctrl    <= pull_lo_ix;
4679
             addr_ctrl  <= pulls_ad;
4680
                                 if ea(5) = '1' then
4681
                                   next_state <= puls_iyh_state;
4682
                                 elsif ea(6) = '1' then
4683
               next_state <= puls_uph_state;
4684
                                 elsif ea(7) = '1' then
4685
               next_state <= puls_pch_state;
4686
                                 else
4687
               lic        <= '1';
4688
                                   next_state <= fetch_state;
4689
                                 end if;
4690
 
4691
                          when puls_iyh_state =>
4692
             -- increment sp
4693
             left_ctrl  <= sp_left;
4694
             right_ctrl <= one_right;
4695
             alu_ctrl   <= alu_add16;
4696
             sp_ctrl    <= load_sp;
4697
                                 -- pull iy hi
4698
                                 iy_ctrl    <= pull_hi_iy;
4699
             addr_ctrl  <= pulls_ad;
4700
             next_state   <= puls_iyl_state;
4701
 
4702
                          when puls_iyl_state =>
4703
             -- increment sp
4704
             left_ctrl  <= sp_left;
4705
             right_ctrl <= one_right;
4706
             alu_ctrl   <= alu_add16;
4707
             sp_ctrl    <= load_sp;
4708
                                 -- read iy low
4709
                                 iy_ctrl    <= pull_lo_iy;
4710
             addr_ctrl  <= pulls_ad;
4711
                                 if ea(6) = '1' then
4712
               next_state <= puls_uph_state;
4713
                                 elsif ea(7) = '1' then
4714
               next_state <= puls_pch_state;
4715
                                 else
4716
               lic        <= '1';
4717
                                   next_state <= fetch_state;
4718
                                 end if;
4719
 
4720
                          when puls_uph_state =>
4721
             -- increment sp
4722
             left_ctrl  <= sp_left;
4723
             right_ctrl <= one_right;
4724
             alu_ctrl   <= alu_add16;
4725
             sp_ctrl    <= load_sp;
4726
                                 -- pull up hi
4727
                                 up_ctrl    <= pull_hi_up;
4728
             addr_ctrl  <= pulls_ad;
4729
             next_state <= puls_upl_state;
4730
 
4731
                          when puls_upl_state =>
4732
                                 -- increment sp
4733
             left_ctrl  <= sp_left;
4734
             right_ctrl <= one_right;
4735
             alu_ctrl   <= alu_add16;
4736
             sp_ctrl    <= load_sp;
4737
                                 -- read up low
4738
                                 up_ctrl    <= pull_lo_up;
4739
             addr_ctrl  <= pulls_ad;
4740
                                 if ea(7) = '1' then
4741
               next_state <= puls_pch_state;
4742
                                 else
4743
               lic        <= '1';
4744
                                   next_state <= fetch_state;
4745
                                 end if;
4746
 
4747
                          when puls_pch_state =>
4748
             -- increment sp
4749
             left_ctrl  <= sp_left;
4750
             right_ctrl <= one_right;
4751
             alu_ctrl   <= alu_add16;
4752
             sp_ctrl    <= load_sp;
4753
                                 -- pull pc hi
4754
                                 pc_ctrl    <= pull_hi_pc;
4755
             addr_ctrl  <= pulls_ad;
4756
             next_state <= puls_pcl_state;
4757
 
4758
                          when puls_pcl_state =>
4759
                                 -- increment sp
4760
             left_ctrl  <= sp_left;
4761
             right_ctrl <= one_right;
4762
             alu_ctrl   <= alu_add16;
4763
             sp_ctrl    <= load_sp;
4764
                                 -- read pc low
4765
                                 pc_ctrl    <= pull_lo_pc;
4766
             addr_ctrl  <= pulls_ad;
4767
             lic        <= '1';
4768
             next_state <= fetch_state;
4769
 
4770
                          --
4771
                          -- Enter here on pshu
4772
                          -- ea holds post byte
4773
                          --
4774
                          when pshu_state =>
4775
             -- decrement up if any registers to be pushed
4776
             left_ctrl  <= up_left;
4777
             right_ctrl <= one_right;
4778
             alu_ctrl   <= alu_sub16;
4779
                                 if ea(7 downto 0) = "00000000" then
4780
               up_ctrl    <= latch_up;
4781
                                 else
4782
               up_ctrl    <= load_up;
4783
                                 end if;
4784
                                 -- write idle bus
4785
                                 if ea(7) = '1' then
4786
               next_state   <= pshu_pcl_state;
4787
                                 elsif ea(6) = '1' then
4788
               next_state   <= pshu_spl_state;
4789
                                 elsif ea(5) = '1' then
4790
                                   next_state   <= pshu_iyl_state;
4791
                                 elsif ea(4) = '1' then
4792
                                   next_state   <= pshu_ixl_state;
4793
                                 elsif ea(3) = '1' then
4794
                                   next_state   <= pshu_dp_state;
4795
                                 elsif ea(2) = '1' then
4796
                                   next_state   <= pshu_accb_state;
4797
                                 elsif ea(1) = '1' then
4798
                                   next_state   <= pshu_acca_state;
4799
                                 elsif ea(0) = '1' then
4800
                                   next_state   <= pshu_cc_state;
4801
                                 else
4802
               lic          <= '1';
4803
                                   next_state   <= fetch_state;
4804
                                 end if;
4805
                          --
4806
                          -- push PC onto U stack
4807
                          --
4808
                          when pshu_pcl_state =>
4809
             -- decrement up
4810
             left_ctrl  <= up_left;
4811
             right_ctrl <= one_right;
4812
             alu_ctrl   <= alu_sub16;
4813
             up_ctrl    <= load_up;
4814
                                 -- write pc low
4815
             addr_ctrl  <= pushu_ad;
4816
                            dout_ctrl  <= pc_lo_dout;
4817
             next_state <= pshu_pch_state;
4818
 
4819
                          when pshu_pch_state =>
4820
             -- decrement up
4821
             left_ctrl  <= up_left;
4822
             right_ctrl <= one_right;
4823
             alu_ctrl   <= alu_sub16;
4824
                                 if ea(6 downto 0) = "0000000" then
4825
               up_ctrl    <= latch_up;
4826
                                 else
4827
               up_ctrl    <= load_up;
4828
                                 end if;
4829
                                 -- write pc hi
4830
             addr_ctrl  <= pushu_ad;
4831
                            dout_ctrl  <= pc_hi_dout;
4832
                                 if ea(6) = '1' then
4833
               next_state   <= pshu_spl_state;
4834
                                 elsif ea(5) = '1' then
4835
                                   next_state   <= pshu_iyl_state;
4836
                                 elsif ea(4) = '1' then
4837
                                   next_state   <= pshu_ixl_state;
4838
                                 elsif ea(3) = '1' then
4839
                                   next_state   <= pshu_dp_state;
4840
                                 elsif ea(2) = '1' then
4841
                                   next_state   <= pshu_accb_state;
4842
                                 elsif ea(1) = '1' then
4843
                                   next_state   <= pshu_acca_state;
4844
                                 elsif ea(0) = '1' then
4845
                                   next_state   <= pshu_cc_state;
4846
                                 else
4847
               lic          <= '1';
4848
                                   next_state   <= fetch_state;
4849
                                 end if;
4850
 
4851
                          when pshu_spl_state =>
4852
             -- decrement up
4853
             left_ctrl  <= up_left;
4854
             right_ctrl <= one_right;
4855
             alu_ctrl   <= alu_sub16;
4856
             up_ctrl    <= load_up;
4857
                                 -- write sp low
4858
             addr_ctrl  <= pushu_ad;
4859
                            dout_ctrl  <= sp_lo_dout;
4860
             next_state <= pshu_sph_state;
4861
 
4862
                          when pshu_sph_state =>
4863
             -- decrement up
4864
             left_ctrl  <= up_left;
4865
             right_ctrl <= one_right;
4866
             alu_ctrl   <= alu_sub16;
4867
                                 if ea(5 downto 0) = "000000" then
4868
               up_ctrl    <= latch_up;
4869
                                 else
4870
               up_ctrl    <= load_up;
4871
                                 end if;
4872
                                 -- write sp hi
4873
             addr_ctrl  <= pushu_ad;
4874
                            dout_ctrl  <= sp_hi_dout;
4875
                                 if ea(5) = '1' then
4876
                                   next_state   <= pshu_iyl_state;
4877
                                 elsif ea(4) = '1' then
4878
                                   next_state   <= pshu_ixl_state;
4879
                                 elsif ea(3) = '1' then
4880
                                   next_state   <= pshu_dp_state;
4881
                                 elsif ea(2) = '1' then
4882
                                   next_state   <= pshu_accb_state;
4883
                                 elsif ea(1) = '1' then
4884
                                   next_state   <= pshu_acca_state;
4885
                                 elsif ea(0) = '1' then
4886
                                   next_state   <= pshu_cc_state;
4887
                                 else
4888
               lic          <= '1';
4889
                                   next_state   <= fetch_state;
4890
                                 end if;
4891
 
4892
                          when pshu_iyl_state =>
4893
             -- decrement up
4894
             left_ctrl  <= up_left;
4895
             right_ctrl <= one_right;
4896
             alu_ctrl   <= alu_sub16;
4897
             up_ctrl    <= load_up;
4898
                                 -- write iy low
4899
             addr_ctrl  <= pushu_ad;
4900
                            dout_ctrl  <= iy_lo_dout;
4901
             next_state <= pshu_iyh_state;
4902
 
4903
                          when pshu_iyh_state =>
4904
             -- decrement up
4905
             left_ctrl  <= up_left;
4906
             right_ctrl <= one_right;
4907
             alu_ctrl   <= alu_sub16;
4908
                                 if ea(4 downto 0) = "00000" then
4909
               up_ctrl    <= latch_up;
4910
                                 else
4911
               up_ctrl    <= load_up;
4912
                                 end if;
4913
                                 -- write iy hi
4914
             addr_ctrl  <= pushu_ad;
4915
                            dout_ctrl  <= iy_hi_dout;
4916
                                 if ea(4) = '1' then
4917
                                   next_state   <= pshu_ixl_state;
4918
                                 elsif ea(3) = '1' then
4919
                                   next_state   <= pshu_dp_state;
4920
                                 elsif ea(2) = '1' then
4921
                                   next_state   <= pshu_accb_state;
4922
                                 elsif ea(1) = '1' then
4923
                                   next_state   <= pshu_acca_state;
4924
                                 elsif ea(0) = '1' then
4925
                                   next_state   <= pshu_cc_state;
4926
                                 else
4927
               lic          <= '1';
4928
                                   next_state   <= fetch_state;
4929
                                 end if;
4930
 
4931
                          when pshu_ixl_state =>
4932
             -- decrement up
4933
             left_ctrl  <= up_left;
4934
             right_ctrl <= one_right;
4935
             alu_ctrl   <= alu_sub16;
4936
             up_ctrl    <= load_up;
4937
                                 -- write ix low
4938
             addr_ctrl  <= pushu_ad;
4939
                            dout_ctrl  <= ix_lo_dout;
4940
             next_state <= pshu_ixh_state;
4941
 
4942
                          when pshu_ixh_state =>
4943
             -- decrement up
4944
             left_ctrl  <= up_left;
4945
             right_ctrl <= one_right;
4946
             alu_ctrl   <= alu_sub16;
4947
                                 if ea(3 downto 0) = "0000" then
4948
               up_ctrl    <= latch_up;
4949
                                 else
4950
               up_ctrl    <= load_up;
4951
                                 end if;
4952
                                 -- write ix hi
4953
             addr_ctrl  <= pushu_ad;
4954
                            dout_ctrl  <= ix_hi_dout;
4955
                                 if ea(3) = '1' then
4956
                                   next_state   <= pshu_dp_state;
4957
                                 elsif ea(2) = '1' then
4958
                                   next_state   <= pshu_accb_state;
4959
                                 elsif ea(1) = '1' then
4960
                                   next_state   <= pshu_acca_state;
4961
                                 elsif ea(0) = '1' then
4962
                                   next_state   <= pshu_cc_state;
4963
                                 else
4964
               lic          <= '1';
4965
                                   next_state   <= fetch_state;
4966
                                 end if;
4967
 
4968
                          when pshu_dp_state =>
4969
             -- decrement up
4970
             left_ctrl  <= up_left;
4971
             right_ctrl <= one_right;
4972
             alu_ctrl   <= alu_sub16;
4973
                                 if ea(2 downto 0) = "000" then
4974
               up_ctrl    <= latch_up;
4975
                                 else
4976
               up_ctrl    <= load_up;
4977
                                 end if;
4978
                                 -- write dp
4979
             addr_ctrl  <= pushu_ad;
4980
                            dout_ctrl  <= dp_dout;
4981
                                 if ea(2) = '1' then
4982
                                   next_state   <= pshu_accb_state;
4983
                                 elsif ea(1) = '1' then
4984
                                   next_state   <= pshu_acca_state;
4985
                                 elsif ea(0) = '1' then
4986
                                   next_state   <= pshu_cc_state;
4987
                                 else
4988
               lic          <= '1';
4989
                                   next_state   <= fetch_state;
4990
                                 end if;
4991
 
4992
                          when pshu_accb_state =>
4993
             -- decrement up
4994
             left_ctrl  <= up_left;
4995
             right_ctrl <= one_right;
4996
             alu_ctrl   <= alu_sub16;
4997
                                 if ea(1 downto 0) = "00" then
4998
               up_ctrl    <= latch_up;
4999
                                 else
5000
               up_ctrl    <= load_up;
5001
                                 end if;
5002
                                 -- write accb
5003
             addr_ctrl  <= pushu_ad;
5004
                            dout_ctrl  <= accb_dout;
5005
                                 if ea(1) = '1' then
5006
                                   next_state   <= pshu_acca_state;
5007
                                 elsif ea(0) = '1' then
5008
                                   next_state   <= pshu_cc_state;
5009
                                 else
5010
               lic          <= '1';
5011
                                   next_state   <= fetch_state;
5012
                                 end if;
5013
 
5014
                          when pshu_acca_state =>
5015
             -- decrement up
5016
             left_ctrl  <= up_left;
5017
             right_ctrl <= one_right;
5018
             alu_ctrl   <= alu_sub16;
5019
                                 if ea(0) = '0' then
5020
               up_ctrl    <= latch_up;
5021
                                 else
5022
               up_ctrl    <= load_up;
5023
                                 end if;
5024
                                 -- write acca
5025
             addr_ctrl  <= pushu_ad;
5026
                            dout_ctrl  <= acca_dout;
5027
                                 if ea(0) = '1' then
5028
                                   next_state   <= pshu_cc_state;
5029
                                 else
5030
               lic          <= '1';
5031
                                   next_state   <= fetch_state;
5032
                                 end if;
5033
 
5034
                          when pshu_cc_state =>
5035
             -- idle up
5036
                                 -- write cc
5037
             addr_ctrl  <= pushu_ad;
5038
                            dout_ctrl  <= cc_dout;
5039
             lic        <= '1';
5040
             next_state <= fetch_state;
5041
 
5042
                          --
5043
                          -- enter here on PULU
5044
                          -- ea hold register mask
5045
                          --
5046
                          when pulu_state =>
5047
                                 -- idle UP
5048
                                 -- idle bus
5049
                                 if ea(0) = '1' then
5050
                                   next_state <= pulu_cc_state;
5051
                                 elsif ea(1) = '1' then
5052
                                   next_state <= pulu_acca_state;
5053
                                 elsif ea(2) = '1' then
5054
                                   next_state <= pulu_accb_state;
5055
                                 elsif ea(3) = '1' then
5056
                                   next_state <= pulu_dp_state;
5057
                                 elsif ea(4) = '1' then
5058
                                   next_state <= pulu_ixh_state;
5059
                                 elsif ea(5) = '1' then
5060
                                   next_state <= pulu_iyh_state;
5061
                                 elsif ea(6) = '1' then
5062
               next_state <= pulu_sph_state;
5063
                                 elsif ea(7) = '1' then
5064
               next_state <= pulu_pch_state;
5065
                                 else
5066
               lic        <= '1';
5067
                                   next_state <= fetch_state;
5068
                                 end if;
5069
 
5070
                          when pulu_cc_state =>
5071
                                 -- increment up
5072
             left_ctrl  <= up_left;
5073
             right_ctrl <= one_right;
5074
             alu_ctrl   <= alu_add16;
5075
             up_ctrl    <= load_up;
5076
                                 -- read cc
5077
             cc_ctrl    <= pull_cc;
5078
             addr_ctrl  <= pullu_ad;
5079
                                 if ea(1) = '1' then
5080
                                   next_state <= pulu_acca_state;
5081
                                 elsif ea(2) = '1' then
5082
                                   next_state <= pulu_accb_state;
5083
                                 elsif ea(3) = '1' then
5084
                                   next_state <= pulu_dp_state;
5085
                                 elsif ea(4) = '1' then
5086
                                   next_state <= pulu_ixh_state;
5087
                                 elsif ea(5) = '1' then
5088
                                   next_state <= pulu_iyh_state;
5089
                                 elsif ea(6) = '1' then
5090
               next_state <= pulu_sph_state;
5091
                                 elsif ea(7) = '1' then
5092
               next_state <= pulu_pch_state;
5093
                                 else
5094
               lic        <= '1';
5095
                                   next_state <= fetch_state;
5096
                                 end if;
5097
 
5098
                          when pulu_acca_state =>
5099
                                 -- increment up
5100
             left_ctrl  <= up_left;
5101
             right_ctrl <= one_right;
5102
             alu_ctrl   <= alu_add16;
5103
             up_ctrl    <= load_up;
5104
                                 -- read acca
5105
                                 acca_ctrl  <= pull_acca;
5106
             addr_ctrl  <= pullu_ad;
5107
                                 if ea(2) = '1' then
5108
                                   next_state <= pulu_accb_state;
5109
                                 elsif ea(3) = '1' then
5110
                                   next_state <= pulu_dp_state;
5111
                                 elsif ea(4) = '1' then
5112
                                   next_state <= pulu_ixh_state;
5113
                                 elsif ea(5) = '1' then
5114
                                   next_state <= pulu_iyh_state;
5115
                                 elsif ea(6) = '1' then
5116
               next_state <= pulu_sph_state;
5117
                                 elsif ea(7) = '1' then
5118
               next_state <= pulu_pch_state;
5119
                                 else
5120
               lic        <= '1';
5121
                                   next_state <= fetch_state;
5122
                                 end if;
5123
 
5124
                          when pulu_accb_state =>
5125
                                 -- increment up
5126
             left_ctrl  <= up_left;
5127
             right_ctrl <= one_right;
5128
             alu_ctrl   <= alu_add16;
5129
             up_ctrl    <= load_up;
5130
                                 -- read accb
5131
                                 accb_ctrl  <= pull_accb;
5132
             addr_ctrl  <= pullu_ad;
5133
                                 if ea(3) = '1' then
5134
                                   next_state <= pulu_dp_state;
5135
                                 elsif ea(4) = '1' then
5136
                                   next_state <= pulu_ixh_state;
5137
                                 elsif ea(5) = '1' then
5138
                                   next_state <= pulu_iyh_state;
5139
                                 elsif ea(6) = '1' then
5140
               next_state <= pulu_sph_state;
5141
                                 elsif ea(7) = '1' then
5142
               next_state <= pulu_pch_state;
5143
                                 else
5144
               lic        <= '1';
5145
                                   next_state <= fetch_state;
5146
                                 end if;
5147
 
5148
                          when pulu_dp_state =>
5149
                                 -- increment up
5150
             left_ctrl  <= up_left;
5151
             right_ctrl <= one_right;
5152
             alu_ctrl   <= alu_add16;
5153
             up_ctrl    <= load_up;
5154
                                 -- read dp
5155
                                 dp_ctrl    <= pull_dp;
5156
             addr_ctrl  <= pullu_ad;
5157
                                 if ea(4) = '1' then
5158
                                   next_state <= pulu_ixh_state;
5159
                                 elsif ea(5) = '1' then
5160
                                   next_state <= pulu_iyh_state;
5161
                                 elsif ea(6) = '1' then
5162
               next_state <= pulu_sph_state;
5163
                                 elsif ea(7) = '1' then
5164
               next_state <= pulu_pch_state;
5165
                                 else
5166
               lic        <= '1';
5167
                                   next_state <= fetch_state;
5168
                                 end if;
5169
 
5170
                          when pulu_ixh_state =>
5171
             -- increment up
5172
             left_ctrl  <= up_left;
5173
             right_ctrl <= one_right;
5174
             alu_ctrl   <= alu_add16;
5175
             up_ctrl    <= load_up;
5176
                                 -- read ix hi
5177
                                 ix_ctrl    <= pull_hi_ix;
5178
             addr_ctrl  <= pullu_ad;
5179
             next_state <= pulu_ixl_state;
5180
 
5181
                          when pulu_ixl_state =>
5182
                                 -- increment up
5183
             left_ctrl  <= up_left;
5184
             right_ctrl <= one_right;
5185
             alu_ctrl   <= alu_add16;
5186
             up_ctrl    <= load_up;
5187
                                 -- read ix low
5188
                                 ix_ctrl    <= pull_lo_ix;
5189
             addr_ctrl  <= pullu_ad;
5190
                                 if ea(5) = '1' then
5191
                                   next_state <= pulu_iyh_state;
5192
                                 elsif ea(6) = '1' then
5193
               next_state <= pulu_sph_state;
5194
                                 elsif ea(7) = '1' then
5195
               next_state <= pulu_pch_state;
5196
                                 else
5197
               lic        <= '1';
5198
                                   next_state <= fetch_state;
5199
                                 end if;
5200
 
5201
                          when pulu_iyh_state =>
5202
             -- increment up
5203
             left_ctrl  <= up_left;
5204
             right_ctrl <= one_right;
5205
             alu_ctrl   <= alu_add16;
5206
             up_ctrl    <= load_up;
5207
                                 -- read iy hi
5208
                                 iy_ctrl    <= pull_hi_iy;
5209
             addr_ctrl  <= pullu_ad;
5210
             next_state <= pulu_iyl_state;
5211
 
5212
                          when pulu_iyl_state =>
5213
             -- increment up
5214
             left_ctrl  <= up_left;
5215
             right_ctrl <= one_right;
5216
             alu_ctrl   <= alu_add16;
5217
             up_ctrl    <= load_up;
5218
                                 -- read iy low
5219
                                 iy_ctrl    <= pull_lo_iy;
5220
             addr_ctrl  <= pullu_ad;
5221
                                 if ea(6) = '1' then
5222
               next_state <= pulu_sph_state;
5223
                                 elsif ea(7) = '1' then
5224
               next_state <= pulu_pch_state;
5225
                                 else
5226
               lic        <= '1';
5227
                                   next_state <= fetch_state;
5228
                                 end if;
5229
 
5230
                          when pulu_sph_state =>
5231
             -- increment up
5232
             left_ctrl  <= up_left;
5233
             right_ctrl <= one_right;
5234
             alu_ctrl   <= alu_add16;
5235
             up_ctrl    <= load_up;
5236
                                 -- read sp hi
5237
                                 sp_ctrl    <= pull_hi_sp;
5238
             addr_ctrl  <= pullu_ad;
5239
             next_state <= pulu_spl_state;
5240
 
5241
                          when pulu_spl_state =>
5242
                                 -- increment up
5243
             left_ctrl  <= up_left;
5244
             right_ctrl <= one_right;
5245
             alu_ctrl   <= alu_add16;
5246
             up_ctrl    <= load_up;
5247
                                 -- read sp low
5248
                                 sp_ctrl    <= pull_lo_sp;
5249
             addr_ctrl  <= pullu_ad;
5250
                                 if ea(7) = '1' then
5251
               next_state <= pulu_pch_state;
5252
                                 else
5253
               lic        <= '1';
5254
                                   next_state <= fetch_state;
5255
                                 end if;
5256
 
5257
                          when pulu_pch_state =>
5258
             -- increment up
5259
             left_ctrl  <= up_left;
5260
             right_ctrl <= one_right;
5261
             alu_ctrl   <= alu_add16;
5262
             up_ctrl    <= load_up;
5263
                                 -- pull pc hi
5264
                                 pc_ctrl    <= pull_hi_pc;
5265
             addr_ctrl  <= pullu_ad;
5266
             next_state <= pulu_pcl_state;
5267
 
5268
                          when pulu_pcl_state =>
5269
                                 -- increment up
5270
             left_ctrl  <= up_left;
5271
             right_ctrl <= one_right;
5272
             alu_ctrl   <= alu_add16;
5273
             up_ctrl    <= load_up;
5274
                                 -- read pc low
5275
                                 pc_ctrl    <= pull_lo_pc;
5276
             addr_ctrl  <= pullu_ad;
5277
             lic        <= '1';
5278
             next_state <= fetch_state;
5279
 
5280
                          --
5281
                          -- pop the Condition codes
5282
                          --
5283
                          when rti_cc_state =>
5284
                                 -- increment sp
5285
             left_ctrl  <= sp_left;
5286
             right_ctrl <= one_right;
5287
             alu_ctrl   <= alu_add16;
5288
             sp_ctrl    <= load_sp;
5289
                                 -- read cc
5290
             cc_ctrl    <= pull_cc;
5291
             addr_ctrl  <= pulls_ad;
5292
             next_state <= rti_entire_state;
5293
 
5294
                          --
5295
                          -- Added RTI cycle 11th July 2006 John Kent.
5296
                          -- test the "Entire" Flag
5297
                          -- that has just been popped off the stack
5298
                          --
5299
                          when rti_entire_state =>
5300
                                 --
5301
                                 -- The Entire flag must be recovered from the stack
5302
                                 -- before testing.
5303
                                 --
5304
                                 if cc(EBIT) = '1' then
5305
               next_state   <= rti_acca_state;
5306
                                 else
5307
               next_state   <= rti_pch_state;
5308
                                 end if;
5309
 
5310
                          when rti_acca_state =>
5311
                                 -- increment sp
5312
             left_ctrl  <= sp_left;
5313
             right_ctrl <= one_right;
5314
             alu_ctrl   <= alu_add16;
5315
             sp_ctrl    <= load_sp;
5316
                                 -- read acca
5317
                                 acca_ctrl  <= pull_acca;
5318
             addr_ctrl  <= pulls_ad;
5319
             next_state <= rti_accb_state;
5320
 
5321
                          when rti_accb_state =>
5322
                                 -- increment sp
5323
             left_ctrl  <= sp_left;
5324
             right_ctrl <= one_right;
5325
             alu_ctrl   <= alu_add16;
5326
             sp_ctrl    <= load_sp;
5327
                                 -- read accb
5328
                                 accb_ctrl  <= pull_accb;
5329
             addr_ctrl  <= pulls_ad;
5330
             next_state <= rti_dp_state;
5331
 
5332
                          when rti_dp_state =>
5333
                                 -- increment sp
5334
             left_ctrl  <= sp_left;
5335
             right_ctrl <= one_right;
5336
             alu_ctrl   <= alu_add16;
5337
             sp_ctrl    <= load_sp;
5338
                                 -- read dp
5339
                                 dp_ctrl    <= pull_dp;
5340
             addr_ctrl  <= pulls_ad;
5341
             next_state <= rti_ixh_state;
5342
 
5343
                          when rti_ixh_state =>
5344
                                 -- increment sp
5345
             left_ctrl  <= sp_left;
5346
             right_ctrl <= one_right;
5347
             alu_ctrl   <= alu_add16;
5348
             sp_ctrl    <= load_sp;
5349
                                 -- read ix hi
5350
                                 ix_ctrl    <= pull_hi_ix;
5351
             addr_ctrl  <= pulls_ad;
5352
             next_state <= rti_ixl_state;
5353
 
5354
                          when rti_ixl_state =>
5355
                                 -- increment sp
5356
             left_ctrl  <= sp_left;
5357
             right_ctrl <= one_right;
5358
             alu_ctrl   <= alu_add16;
5359
             sp_ctrl    <= load_sp;
5360
                                 -- read ix low
5361
                                 ix_ctrl    <= pull_lo_ix;
5362
             addr_ctrl  <= pulls_ad;
5363
             next_state <= rti_iyh_state;
5364
 
5365
                          when rti_iyh_state =>
5366
                                 -- increment sp
5367
             left_ctrl  <= sp_left;
5368
             right_ctrl <= one_right;
5369
             alu_ctrl   <= alu_add16;
5370
             sp_ctrl    <= load_sp;
5371
                                 -- read iy hi
5372
                                 iy_ctrl    <= pull_hi_iy;
5373
             addr_ctrl  <= pulls_ad;
5374
             next_state <= rti_iyl_state;
5375
 
5376
                          when rti_iyl_state =>
5377
                                 -- increment sp
5378
             left_ctrl  <= sp_left;
5379
             right_ctrl <= one_right;
5380
             alu_ctrl   <= alu_add16;
5381
             sp_ctrl    <= load_sp;
5382
                                 -- read iy low
5383
                                 iy_ctrl    <= pull_lo_iy;
5384
             addr_ctrl  <= pulls_ad;
5385
             next_state <= rti_uph_state;
5386
 
5387
 
5388
                          when rti_uph_state =>
5389
                                 -- increment sp
5390
             left_ctrl  <= sp_left;
5391
             right_ctrl <= one_right;
5392
             alu_ctrl   <= alu_add16;
5393
             sp_ctrl    <= load_sp;
5394
                                 -- read up hi
5395
                                 up_ctrl    <= pull_hi_up;
5396
             addr_ctrl  <= pulls_ad;
5397
             next_state <= rti_upl_state;
5398
 
5399
                          when rti_upl_state =>
5400
                                 -- increment sp
5401
             left_ctrl  <= sp_left;
5402
             right_ctrl <= one_right;
5403
             alu_ctrl   <= alu_add16;
5404
             sp_ctrl    <= load_sp;
5405
                                 -- read up low
5406
             up_ctrl    <= pull_lo_up;
5407
             addr_ctrl  <= pulls_ad;
5408
             next_state <= rti_pch_state;
5409
 
5410
                          when rti_pch_state =>
5411
                  -- increment sp
5412
             left_ctrl  <= sp_left;
5413
             right_ctrl <= one_right;
5414
             alu_ctrl   <= alu_add16;
5415
             sp_ctrl    <= load_sp;
5416
                                 -- pull pc hi
5417
                                 pc_ctrl    <= pull_hi_pc;
5418
             addr_ctrl  <= pulls_ad;
5419
             next_state <= rti_pcl_state;
5420
 
5421
                          when rti_pcl_state =>
5422
                                 -- increment sp
5423
             left_ctrl  <= sp_left;
5424
             right_ctrl <= one_right;
5425
             alu_ctrl   <= alu_add16;
5426
             sp_ctrl    <= load_sp;
5427
                  -- pull pc low
5428
                                 pc_ctrl    <= pull_lo_pc;
5429
             addr_ctrl  <= pulls_ad;
5430
             lic        <= '1';
5431
             next_state <= fetch_state;
5432
 
5433
                          --
5434
                          -- here on IRQ or NMI interrupt
5435
                          -- pre decrement the sp
5436
                          -- Idle bus cycle
5437
                          --
5438
                          when int_nmiirq_state =>
5439
             -- decrement sp
5440
             left_ctrl  <= sp_left;
5441
             right_ctrl <= one_right;
5442
             alu_ctrl   <= alu_sub16;
5443
             sp_ctrl    <= load_sp;
5444
             next_state <= int_entire_state;
5445
 
5446
                          --
5447
                          -- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
5448
                          -- clear Entire Flag on FIRQ
5449
                          -- before stacking all registers
5450
                          --
5451
                          when int_entire_state =>
5452
             -- set entire flag
5453
             alu_ctrl   <= alu_see;
5454
             cc_ctrl    <= load_cc;
5455
             next_state <= int_pcl_state;
5456
 
5457
                          --
5458
                          -- here on FIRQ interrupt
5459
                          -- pre decrement the sp
5460
                          -- Idle bus cycle
5461
                          --
5462
                          when int_firq_state =>
5463
             -- decrement sp
5464
             left_ctrl  <= sp_left;
5465
             right_ctrl <= one_right;
5466
             alu_ctrl   <= alu_sub16;
5467
             sp_ctrl    <= load_sp;
5468
             next_state <= int_fast_state;
5469
                          --
5470
                          -- clear Entire Flag on FIRQ
5471
                          -- before stacking all registers
5472
                          --
5473
                          when int_fast_state =>
5474
             -- clear entire flag
5475
             alu_ctrl   <= alu_cle;
5476
             cc_ctrl    <= load_cc;
5477
             next_state <= int_pcl_state;
5478
 
5479
                          when int_pcl_state =>
5480
             -- decrement sp
5481
             left_ctrl  <= sp_left;
5482
             right_ctrl <= one_right;
5483
             alu_ctrl   <= alu_sub16;
5484
             sp_ctrl    <= load_sp;
5485
                                 -- write pc low
5486
             addr_ctrl  <= pushs_ad;
5487
                            dout_ctrl  <= pc_lo_dout;
5488
             next_state <= int_pch_state;
5489
 
5490
                          when int_pch_state =>
5491
             -- decrement sp
5492
             left_ctrl  <= sp_left;
5493
             right_ctrl <= one_right;
5494
             alu_ctrl   <= alu_sub16;
5495
             sp_ctrl    <= load_sp;
5496
                                 -- write pc hi
5497
             addr_ctrl  <= pushs_ad;
5498
                            dout_ctrl  <= pc_hi_dout;
5499
                                 if cc(EBIT) = '1' then
5500
               next_state   <= int_upl_state;
5501
                                 else
5502
               next_state   <= int_cc_state;
5503
                                 end if;
5504
 
5505
                          when int_upl_state =>
5506
             -- decrement sp
5507
             left_ctrl  <= sp_left;
5508
             right_ctrl <= one_right;
5509
             alu_ctrl   <= alu_sub16;
5510
             sp_ctrl    <= load_sp;
5511
                                 -- write up low
5512
             addr_ctrl  <= pushs_ad;
5513
                            dout_ctrl  <= up_lo_dout;
5514
             next_state <= int_uph_state;
5515
 
5516
                          when int_uph_state =>
5517
             -- decrement sp
5518
             left_ctrl  <= sp_left;
5519
             right_ctrl <= one_right;
5520
             alu_ctrl   <= alu_sub16;
5521
             sp_ctrl    <= load_sp;
5522
                                 -- write ix hi
5523
             addr_ctrl  <= pushs_ad;
5524
                            dout_ctrl  <= up_hi_dout;
5525
             next_state <= int_iyl_state;
5526
 
5527
                          when int_iyl_state =>
5528
             -- decrement sp
5529
             left_ctrl  <= sp_left;
5530
             right_ctrl <= one_right;
5531
             alu_ctrl   <= alu_sub16;
5532
             sp_ctrl    <= load_sp;
5533
                                 -- write ix low
5534
             addr_ctrl  <= pushs_ad;
5535
                            dout_ctrl  <= iy_lo_dout;
5536
             next_state <= int_iyh_state;
5537
 
5538
                          when int_iyh_state =>
5539
             -- decrement sp
5540
             left_ctrl  <= sp_left;
5541
             right_ctrl <= one_right;
5542
             alu_ctrl   <= alu_sub16;
5543
             sp_ctrl    <= load_sp;
5544
                                 -- write ix hi
5545
             addr_ctrl  <= pushs_ad;
5546
                            dout_ctrl  <= iy_hi_dout;
5547
             next_state <= int_ixl_state;
5548
 
5549
                          when int_ixl_state =>
5550
             -- decrement sp
5551
             left_ctrl  <= sp_left;
5552
             right_ctrl <= one_right;
5553
             alu_ctrl   <= alu_sub16;
5554
             sp_ctrl    <= load_sp;
5555
                                 -- write ix low
5556
             addr_ctrl  <= pushs_ad;
5557
                            dout_ctrl  <= ix_lo_dout;
5558
             next_state <= int_ixh_state;
5559
 
5560
                          when int_ixh_state =>
5561
             -- decrement sp
5562
             left_ctrl  <= sp_left;
5563
             right_ctrl <= one_right;
5564
             alu_ctrl   <= alu_sub16;
5565
             sp_ctrl    <= load_sp;
5566
                                 -- write ix hi
5567
             addr_ctrl  <= pushs_ad;
5568
                            dout_ctrl  <= ix_hi_dout;
5569
             next_state <= int_dp_state;
5570
 
5571
                          when int_dp_state =>
5572
             -- decrement sp
5573
             left_ctrl  <= sp_left;
5574
             right_ctrl <= one_right;
5575
             alu_ctrl   <= alu_sub16;
5576
             sp_ctrl    <= load_sp;
5577
                                 -- write accb
5578
             addr_ctrl  <= pushs_ad;
5579
                            dout_ctrl  <= dp_dout;
5580
             next_state <= int_accb_state;
5581
 
5582
                          when int_accb_state =>
5583
             -- decrement sp
5584
             left_ctrl  <= sp_left;
5585
             right_ctrl <= one_right;
5586
             alu_ctrl   <= alu_sub16;
5587
             sp_ctrl    <= load_sp;
5588
                                 -- write accb
5589
             addr_ctrl  <= pushs_ad;
5590
                            dout_ctrl  <= accb_dout;
5591
             next_state <= int_acca_state;
5592
 
5593
                          when int_acca_state =>
5594
             -- decrement sp
5595
             left_ctrl  <= sp_left;
5596
             right_ctrl <= one_right;
5597
             alu_ctrl   <= alu_sub16;
5598
             sp_ctrl    <= load_sp;
5599
                                 -- write acca
5600
             addr_ctrl  <= pushs_ad;
5601
                            dout_ctrl  <= acca_dout;
5602
             next_state <= int_cc_state;
5603
 
5604
                          when int_cc_state =>
5605
                                 -- write cc
5606
             addr_ctrl  <= pushs_ad;
5607
                            dout_ctrl  <= cc_dout;
5608
                                 case iv is
5609
                                 when NMI_VEC =>
5610
                              next_state <= int_maskif_state;
5611
                                 when SWI_VEC =>
5612
                              next_state <= int_maskif_state;
5613
                                 when FIRQ_VEC =>
5614
                              next_state <= int_maskif_state;
5615
                                 when IRQ_VEC =>
5616
                              next_state <= int_maski_state;
5617
                                 when SWI2_VEC =>
5618
                    next_state <= vect_hi_state;
5619
                                 when SWI3_VEC =>
5620
                    next_state <= vect_hi_state;
5621
                                 when others =>
5622
                                   if op_code = "00111100" then -- CWAI
5623
                                          next_state <= int_cwai_state;
5624
                                        else
5625
                      next_state <= rti_cc_state; -- spurious interrupt, do a RTI
5626
                                        end if;
5627
                                 end case;
5628
 
5629
                          --
5630
                          -- wait here for an inteerupt
5631
                          --
5632
                          when int_cwai_state =>
5633
                            if (nmi_req = '1') and (nmi_ack='0') then
5634
                                        iv_ctrl    <= nmi_iv;
5635
                                   nmi_ctrl   <= set_nmi;
5636
                              next_state <= int_maskif_state;
5637
                            else
5638
                                   --
5639
                                        -- nmi request is not cleared until nmi input goes low
5640
                                        --
5641
                                   if (nmi_req = '0') and (nmi_ack='1') then
5642
                                     nmi_ctrl <= reset_nmi;
5643
                                        end if;
5644
                                        --
5645
                                        -- FIRQ is level sensitive
5646
                                        --
5647
               if (firq = '1') and (cc(FBIT) = '0') then
5648
                                          iv_ctrl    <= firq_iv;
5649
                                next_state <= int_maskif_state;
5650
                                        --
5651
                                        -- IRQ is level sensitive
5652
                                        --
5653
                                   elsif (irq = '1') and (cc(IBIT) = '0') then
5654
                                          iv_ctrl    <= irq_iv;
5655
                                next_state <= int_maski_state;
5656
               else
5657
                 iv_ctrl    <= reset_iv;
5658
                      next_state <= int_cwai_state;
5659
                                        end if;
5660
                                 end if;
5661
 
5662
                          when int_maski_state =>
5663
                                 alu_ctrl   <= alu_sei;
5664
                                 cc_ctrl    <= load_cc;
5665
             next_state <= vect_hi_state;
5666
 
5667
                          when int_maskif_state =>
5668
                            alu_ctrl   <= alu_seif;
5669
                                 cc_ctrl    <= load_cc;
5670
             next_state <= vect_hi_state;
5671
 
5672
                          --
5673
                          -- According to the 6809 programming manual:
5674
                          -- If an interrupt is received and is masked 
5675
                          -- or lasts for less than three cycles, the PC 
5676
                          -- will advance to the next instruction.
5677
                          -- If an interrupt is unmasked and lasts
5678
                          -- for more than three cycles, an interrupt
5679
                          -- will be generated.
5680
                          -- Note that I don't wait 3 clock cycles.
5681
                          -- John Kent 11th July 2006
5682
                          --
5683
                          when sync_state =>
5684
                            if (nmi_req = '1') and (nmi_ack='0') then
5685
                                        iv_ctrl    <= nmi_iv;
5686
                                   nmi_ctrl   <= set_nmi;
5687
               next_state <= int_nmiirq_state;
5688
                            else
5689
                                   --
5690
                                        -- nmi request is not cleared until nmi input goes low
5691
                                        --
5692
                                   if (nmi_req = '0') and (nmi_ack='1') then
5693
                                          iv_ctrl  <= reset_iv;
5694
                                     nmi_ctrl <= reset_nmi;
5695
                                        end if;
5696
                                        --
5697
                                        -- FIRQ is level sensitive
5698
                                        --
5699
               if (firq = '1') then
5700
                                          if (cc(FBIT) = '0') then
5701
                   iv_ctrl    <= firq_iv;
5702
                   next_state <= int_firq_state;
5703
                                          else
5704
                   iv_ctrl    <= reset_iv;
5705
                   lic        <= '1';
5706
                                  next_state <= fetch_state;
5707
                                          end if;
5708
                                        --
5709
                                        -- IRQ is level sensitive
5710
                                        --
5711
                                   elsif (irq = '1') then
5712
                                          if (cc(IBIT) = '0') then
5713
                   iv_ctrl    <= irq_iv;
5714
                   next_state <= int_nmiirq_state;
5715
                                          else
5716
                   iv_ctrl    <= reset_iv;
5717
                   lic        <= '1';
5718
                                  next_state <= fetch_state;
5719
                                          end if;
5720
               else
5721
                 iv_ctrl    <= reset_iv;
5722
                 ba         <= '1';
5723
                      next_state <= sync_state;
5724
                                        end if;
5725
                                 end if;
5726
 
5727
 
5728
                          when halt_state =>
5729
                                 if halt = '1' then
5730
               ba           <= '1';
5731
               bs           <= '1';
5732
               next_state   <= halt_state;
5733
                                 else
5734
               lic          <= '1';
5735
                                   next_state   <= fetch_state;
5736
                                 end if;
5737
 
5738
                          when others => -- halt on undefine states
5739
                            next_state <= error_state;
5740
                  end case;
5741
end process;
5742
 
5743
end rtl;
5744
 

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