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--===========================================================================--

--                                                                           --

--        Synthesizable 6809 instruction compatible VHDL CPU core            --

--                                                                           --

--===========================================================================--

--

-- File name      : cpu09n.vhd

--

-- Entity name    : cpu09

--

-- Purpose        : 6809 instruction compatible CPU core written in VHDL

--                  with Last Instruction Cycle, bus available, bus status,

--                  and instruction fetch signals.

--                  Not cycle compatible with the original 6809 CPU

--

-- Dependencies   : ieee.std_logic_1164

--                  ieee.std_logic_unsigned

--

-- Author         : John E. Kent

--

-- Email          : dilbert57@opencores.org      

--

-- Web            : http://opencores.org/project,system09

--

-- Description    : VMA (valid memory address) is hight whenever a valid memory

--                  access is made by an instruction fetch, interrupt vector fetch

--                  or a data read or write otherwise it is low indicating an idle

--                  bus cycle.

--                  IFETCH (instruction fetch output) is high whenever an

--                  instruction byte is read i.e. the program counter is applied 

--                  to the address bus.

--                  LIC (last instruction cycle output) is normally low

--                  but goes high on the last cycle of an instruction.

--                  BA (bus available output) is normally low but goes high while

--                  waiting in a Sync instruction state or the CPU is halted

--                  i.e. a DMA grant.

--                  BS (bus status output) is normally low but goes high during an

--                  interrupt or reset vector fetch or the processor is halted

--                  i.e. a DMA grant.

-- 

--  Copyright (C) 2003 - 2010 John Kent

--

--  This program is free software: you can redistribute it and/or modify

--  it under the terms of the GNU General Public License as published by

--  the Free Software Foundation, either version 3 of the License, or

--  (at your option) any later version.

--

--  This program is distributed in the hope that it will be useful,

--  but WITHOUT ANY WARRANTY; without even the implied warranty of

--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--  GNU General Public License for more details.

--

--  You should have received a copy of the GNU General Public License

--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

--

--===========================================================================--

--                                                                           --

--                                Revision History                           --

--                                                                           --

--===========================================================================--

--

-- Version 0.1 - 26 June 2003 - John Kent

-- Added extra level in state stack

-- fixed some calls to the extended addressing state

--

-- Version 0.2 - 5 Sept 2003 - John Kent

-- Fixed 16 bit indexed offset (was doing read rather than fetch)

-- Added/Fixed STY and STS instructions.

-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed

-- CMPX Loaded ACCA and ACCB - Now fixed 

--

-- Version 1.0 - 6 Sep 2003 - John Kent 

-- Initial release to Open Cores

-- reversed clock edge

--

-- Version 1.1 - 29 November 2003 John kent

--      ACCA and ACCB indexed offsets are 2's complement.

-- ALU Right Mux now sign extends ACCA & ACCB offsets

-- Absolute Indirect addressing performed a read on the

-- second byte of the address rather than a fetch

-- so it formed an incorrect address. Now fixed. 

--

-- Version 1.2 - 29 November 2003 John Kent

-- LEAX and LEAY affect the Z bit only

--      LEAS and LEAU do not affect any condition codes

-- added an extra ALU control for LEA.

--

-- Version 1.3 - 12 December 2003 John Kent

-- CWAI did not work, was missed a PUSH_ST on calling

-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for

-- finding this fault.

--

-- Version 1.4 - 12 December 2003 John Kent

-- Missing cc_ctrl assignment in otherwise case of 

-- lea_state resulted in cc_ctrl being latched in

-- that state.  

-- The otherwise statement should never be reached,

-- and has been fixed simply to resolve synthesis warnings.

--

-- Version 1.5 - 17 january 2004 John kent

-- The clear instruction used "alu_ld8" to control the ALU

-- rather than "alu_clr". This mean the Carry was not being

-- cleared correctly.

--

-- Version 1.6 - 24 January 2004 John Kent

-- Fixed problems in PSHU instruction

--

-- Version 1.7 - 25 January 2004 John Kent

-- removed redundant "alu_inx" and "alu_dex'

-- Removed "test_alu" and "test_cc"

-- STD instruction did not set condition codes

-- JMP direct was not decoded properly

-- CLR direct performed an unwanted read cycle

-- Bogus "latch_md" in Page2 indexed addressing

--

-- Version 1.8 - 27 January 2004 John Kent

-- CWAI in decode1_state should increment the PC.

-- ABX is supposed to be an unsigned addition.

-- Added extra ALU function

-- ASR8 slightly changed in the ALU.

--

--      Version 1.9 - 20 August 2005

-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,

-- rather than LSR16. There was a problem with single 

-- operand instructions using the MD register which is

-- sign extended on the first 8 bit fetch.

--

-- Version 1.10 - 13 September 2005

-- TFR & EXG instructions did not work for the Condition Code Register

-- An extra case has been added to the ALU for the alu_tfr control 

-- to assign the left ALU input (alu_left) to the condition code

-- outputs (cc_out). 

--

-- Version 1.11 - 16 September 2005

-- JSR ,X should not predecrement S before calculating the jump address.

-- The reason is that JSR [0,S] needs S to point to the top of the stack

-- to fetch a valid vector address. The solution is to have the addressing

-- mode microcode called before decrementing S and then decrementing S in

-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than

-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are

-- pushed on the stack. This adds one extra bus cycle, but resolves the

-- addressing conflict. I've also removed the pre-decement S in 

-- JSR EXTENDED as it also calls JSR_STATE.

--

-- Version 1.12 - 6th June 2006

-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR

-- This is different to the 6800. CLR should reset the V bit.

--

-- Version 1.13 - 7th July 2006

-- Disable NMI on reset until S Stack pointer has been loaded.

-- Added nmi_enable signal in sp_reg process and nmi_handler process.

--

-- Version 1.14 - 11th July 2006

-- 1. Added new state to RTI called rti_entire_state.

-- This state tests the CC register after it has been loaded

-- from the stack. Previously the current CC was tested which

-- was incorrect. The Entire Flag should be set before the

-- interrupt stacks the CC.

-- 2. On bogus Interrupts, int_cc_state went to rti_state,

-- which was an enumerated state, but not defined anywhere.

-- rti_state has been changed to rti_cc_state so that bogus interrupt

-- will perform an RTI after entering that state.

-- 3. Sync should generate an interrupt if the interrupt masks

-- are cleared. If the interrupt masks are set, then an interrupt

-- will cause the the PC to advance to the next instruction.

-- Note that I don't wait for an interrupt to be asserted for

-- three clock cycles.

-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in

-- the Multiply instruction replacing "alu_add16". This is similar 

-- to "alu_add16" except it sets the Carry bit to B7 of the result

-- in ACCB, sets the Zero bit if the 16 bit result is zero, but

-- does not affect The Half carry (H), Negative (N) or Overflow (V)

-- flags. The logic was re-arranged so that it adds md or zero so 

-- that the Carry condition code is set on zero multiplicands.

-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)

-- and Zero Flags. It will also affect the Overflow (V) flag although

-- the operation is undefined. It's anyones guess what DAA does to V.

--

-- Version 1.15 - 25th Feb 2007 - John Kent

-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"

-- Changed sensitivity lists.

--

-- Version 1.16 - 5th February 2008 - John Kent

-- FIRQ interrupts should take priority over IRQ Interrupts.

-- This presumably means they should be tested for before IRQ

-- when they happen concurrently.

--

-- Version 1.17 - 18th February 2008 - John Kent

-- NMI in CWAI should mask IRQ and FIRQ interrupts

--

-- Version 1.18 - 21st February 2008 - John Kent

-- Removed default register settings in each case statement

-- and placed them at the beginning of the state sequencer.

-- Modified the SYNC instruction so that the interrupt vector(iv)

-- is not set unless an unmasked FIRQ or IRQ is received.

--

-- Version 1.19 - 25th February 2008 - John Kent

-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE

-- Enumerated separate states for MASKI and MASKIF states

-- Removed code on BSR/JSR in fetch cycle

--

-- Version 1.20 - 8th October 2011 - John Kent

-- added fetch output which should go high during the fetch cycle

--

-- Version 1.21 - 8th October 2011 - John Kent

-- added Last Instruction Cycle signal

-- replaced fetch with ifetch (instruction fetch) signal

-- added ba & bs (bus available & bus status) signals

--

-- Version 1.22 - 2011-10-29 John Kent

-- The halt state isn't correct. 

-- The halt state is entered into from the fetch_state

-- It returned to the fetch state which may re-run an execute cycle

-- on the accumulator and it won't necessarily be the last instruction cycle

-- I've changed the halt state to return to the decode1_state

--

-- Version 1.23 - 2011-10-30 John Kent

-- sample halt in the change_state process if lic is high (last instruction cycle)

--

-- Version 1.24 - 2011-11-01 John Kent

-- Handle interrupts in change_state process

-- Sample interrupt inputs on last instruction cycle

-- Remove iv_ctrl and implement iv (interrupt vector) in change_state process.

-- Generate fic (first instruction cycle) from lic (last instruction cycle)

-- and use it to complete the dual operand execute cycle before servicing

-- halt or interrupts requests.

-- rename lic to lic_out on the entity declaration so that lic can be tested internally.

-- add int_firq1_state and int_nmirq1_state to allow for the dual operand execute cycle

-- integrated nmi_ctrl into change_state process

-- Reduces the microcode state stack to one entry (saved_state)

-- imm16_state jumps directly to the fetch_state

-- pull_return_lo states jumps directly to the fetch_state

-- duplicate andcc_state as cwai_state

-- rename exg1_state as exg2 state and duplicate tfr_state as exg1_state

--

-- Version 1.25 - 2011-11-27 John Kent

-- Changed the microcode for saving registers on an interrupt into a microcode subroutine.

-- Removed SWI servicing from the change state process and made SWI, SWI2 & SWI3

-- call the interrupt microcode subroutine.

-- Added additional states for nmi, and irq for interrupt servicing.

-- Added additional states for nmi/irq, firq, and swi interrupts to mask I & F flags.

--

-- Version 1.26 - 2013-03-18 John Kent

-- pre-initialized cond_true variable to true in state sequencer

-- re-arranged change_state process slightly

--

-- Version 1.27 - 2015-05-30 John Kent

-- Added test in state machine for masked IRQ and FIRQ in Sync_state.

--

-- Version 1.28 - 2015-05-30 John Kent.

-- Moved IRQ and FIRQ test from state machine to the state sequencer Sync_state.

--

-- Version 1.29 - 2017-02-11 John Kent

-- Make MUL 11 cycles long rather than 13 cycles.

-- 1 fetch_state, 2 decode1_state, 

-- 3 mul_state, 4 mulea_state, 5 muld_state

-- 6 mul0_state, 7 mul1_state, 8 mul2_state, 9 mul3_state,

-- 10 mul4_state, 11 mul5_state, 12 mul6_state, 13 mul7_state,

-- move mul_state into decode1_state

-- move mul7_state into fetch_state

--

-- Version 1.29 - 2017-03-08 John Kent.

-- Moved LIC in ABX ?

--

-- Version 1.30 -2018-01-13 John Kent

-- cpu09n.vhd

-- replace decode1_state, decode2_state and decode3_state

-- with the one decode_state.

-- $10 $4F = $4F = CLRA on a real MC6809.

-- $10 4F = CLRD on a HD6309

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity cpu09 is

        port (

                clk      :      in std_logic;                     -- E clock input (falling edge)

                rst      :  in std_logic;                     -- reset input (active high)

                vma      : out std_logic;                     -- valid memory address (active high)

      lic_out  : out std_logic;                     -- last instruction cycle (active high)

      ifetch   : out std_logic;                     -- instruction fetch cycle (active high)

      opfetch  : out std_logic;                     -- opcode fetch (active high)

      ba       : out std_logic;                     -- bus available (high on sync wait or DMA grant)

      bs       : out std_logic;                     -- bus status (high on interrupt or reset vector fetch or DMA grant)

                addr     : out std_logic_vector(15 downto 0); -- address bus output

                rw       : out std_logic;                     -- read not write output

           data_out : out std_logic_vector(7 downto 0);  -- data bus output

           data_in  :  in std_logic_vector(7 downto 0);  -- data bus input

                irq      :  in std_logic;                     -- interrupt request input (active high)

                firq     :  in std_logic;                     -- fast interrupt request input (active high)

                nmi      :  in std_logic;                     -- non maskable interrupt request input (active high)

                halt     :  in std_logic;                     -- halt input (active high) grants DMA

                hold     :  in std_logic                      -- hold input (active high) extend bus cycle

                );

end cpu09;

architecture rtl of cpu09 is

  constant EBIT : integer := 7;

  constant FBIT : integer := 6;

  constant HBIT : integer := 5;

  constant IBIT : integer := 4;

  constant NBIT : integer := 3;

  constant ZBIT : integer := 2;

  constant VBIT : integer := 1;

  constant CBIT : integer := 0;

  --

  -- Interrupt vector modifiers

  --

  constant RST_VEC  : std_logic_vector(2 downto 0) := "111";

  constant NMI_VEC  : std_logic_vector(2 downto 0) := "110";

  constant SWI_VEC  : std_logic_vector(2 downto 0) := "101";

  constant IRQ_VEC  : std_logic_vector(2 downto 0) := "100";

  constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";

  constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";

  constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";

  constant RESV_VEC : std_logic_vector(2 downto 0) := "000";

        type state_type is (-- Start off in Reset

                            reset_state,

                                                          -- Fetch Interrupt Vectors (including reset)

                                                          vect_lo_state, vect_hi_state, vect_idle_state,

                       -- Fetch Instruction Cycle

                       fetch_state,

                                                          -- Decode Instruction Cycles

                       decode_state,

                                                          -- Calculate Effective Address

                                                     imm16_state,

                                 indexed_state, index8_state, index16_state, index16_2_state,

                                                          pcrel8_state, pcrel16_state, pcrel16_2_state,

                                                          indexaddr_state, indexaddr2_state,

                                                     postincr1_state, postincr2_state,

                                                          indirect_state, indirect2_state, indirect3_state,

                       extended_state,

                                                          -- single ops

                                                          single_op_read_state,

                                                     single_op_exec_state,

                            single_op_write_state,

                                                          -- Dual op states

                                                          dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,

                                                     dual_op_write8_state, dual_op_write16_state,

                       -- 

                                                     sync_state, halt_state, cwai_state,

                                                          --

                                                          andcc_state, orcc_state,

                                                          tfr_state,

                       exg_state, exg1_state, exg2_state,

                                                          lea_state,

                                                          -- Multiplication

                                                     mulea_state, muld_state,

                                                     mul0_state, mul1_state, mul2_state, mul3_state,

                                                     mul4_state, mul5_state, mul6_state,

                                                          --  Branches

                                                          lbranch_state, sbranch_state,

                                                          -- Jumps, Subroutine Calls and Returns

                       jsr_state, jmp_state,

                       push_return_hi_state, push_return_lo_state,

                       pull_return_hi_state, pull_return_lo_state,

                                                          -- Interrupt cycles

                                                          int_nmi_state, int_nmi1_state,

                                                          int_irq_state, int_irq1_state,

                       int_firq_state,  int_firq1_state,

                                                          int_entire_state, int_fast_state,

                                                          int_pcl_state,  int_pch_state,

                                                     int_upl_state,  int_uph_state,

                                                     int_iyl_state,  int_iyh_state,

                                                     int_ixl_state,  int_ixh_state,

                                                     int_dp_state,

                                           int_accb_state, int_acca_state,

                                                     int_cc_state,

                                                     int_cwai_state,

                                                          int_nmimask_state, int_firqmask_state, int_swimask_state, int_irqmask_state,

                                                          -- Return From Interrupt

                                                     rti_cc_state,   rti_entire_state,

                                                          rti_acca_state, rti_accb_state,

                                                     rti_dp_state,

                                                     rti_ixl_state,  rti_ixh_state,

                                                     rti_iyl_state,  rti_iyh_state,

                                                     rti_upl_state,  rti_uph_state,

                                                     rti_pcl_state,  rti_pch_state,

                                                          -- Push Registers using SP

                                                          pshs_state,

                                                     pshs_pcl_state,  pshs_pch_state,

                                                     pshs_upl_state,  pshs_uph_state,

                                                     pshs_iyl_state,  pshs_iyh_state,

                                                     pshs_ixl_state,  pshs_ixh_state,

                                                     pshs_dp_state,

                                                     pshs_acca_state, pshs_accb_state,

                                                     pshs_cc_state,

                                                          -- Pull Registers using SP

                                                          puls_state,

                                                          puls_cc_state,

                                                          puls_acca_state, puls_accb_state,

                                                          puls_dp_state,

                                                     puls_ixl_state,  puls_ixh_state,

                                                     puls_iyl_state,  puls_iyh_state,

                                                     puls_upl_state,  puls_uph_state,

                                                     puls_pcl_state,  puls_pch_state,

                                                          -- Push Registers using UP

                                                          pshu_state,

                                                     pshu_pcl_state,  pshu_pch_state,

                                                     pshu_spl_state,  pshu_sph_state,

                                                     pshu_iyl_state,  pshu_iyh_state,

                                                     pshu_ixl_state,  pshu_ixh_state,

                                                     pshu_dp_state,

                                                     pshu_acca_state, pshu_accb_state,

                                                     pshu_cc_state,

                                                          -- Pull Registers using UP

                                                          pulu_state,

                                                          pulu_cc_state,

                                                          pulu_acca_state, pulu_accb_state,

                                                          pulu_dp_state,

                                                     pulu_ixl_state,  pulu_ixh_state,

                                                     pulu_iyl_state,  pulu_iyh_state,

                                                     pulu_spl_state,  pulu_sph_state,

                                                     pulu_pcl_state,  pulu_pch_state );

        type st_type    is (reset_st, push_st, idle_st );

        type iv_type    is (latch_iv, swi3_iv, swi2_iv, firq_iv, irq_iv, swi_iv, nmi_iv, reset_iv);

        type addr_type  is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );

        type dout_type  is (cc_dout, acca_dout, accb_dout, dp_dout,

                       ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,

                       up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,

                       pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );

   type op_type    is (reset_op, fetch_op, latch_op );

   type pre_type   is (reset_pre, fetch_pre, load_pre, latch_pre );

   type cc_type    is (reset_cc, load_cc, pull_cc, latch_cc );

   type acca_type  is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );

   type accb_type  is (reset_accb, load_accb, pull_accb, latch_accb );

   type dp_type    is (reset_dp, load_dp, pull_dp, latch_dp );

        type ix_type    is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );

        type iy_type    is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );

        type sp_type    is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );

        type up_type    is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );

        type pc_type    is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );

   type md_type    is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );

   type ea_type    is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );

        type left_type  is (cc_left, acca_left, accb_left, dp_left,

                                                          ix_left, iy_left, up_left, sp_left,

                       accd_left, md_left, pc_left, ea_left );

        type right_type is (ea_right, zero_right, one_right, two_right,

                       acca_right, accb_right, accd_right,

                                                          md_right, md_sign5_right, md_sign8_right );

   type alu_type   is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,

                       alu_and, alu_ora, alu_eor,

                       alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,

                                                     alu_lsr16, alu_lsl16,

                                                     alu_ror8, alu_rol8, alu_mul,

                                                     alu_asr8, alu_asl8, alu_lsr8,

                                                     alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,

                                                          alu_seif, alu_sei, alu_see, alu_cle,

                                                     alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );

        signal op_code:     std_logic_vector(7 downto 0);

        signal pre_code:    std_logic_vector(7 downto 0);

        signal acca:        std_logic_vector(7 downto 0);

        signal accb:        std_logic_vector(7 downto 0);

   signal cc:          std_logic_vector(7 downto 0);

        signal cc_out:      std_logic_vector(7 downto 0);

        signal dp:          std_logic_vector(7 downto 0);

        signal xreg:        std_logic_vector(15 downto 0);

        signal yreg:        std_logic_vector(15 downto 0);

        signal sp:          std_logic_vector(15 downto 0);

        signal up:          std_logic_vector(15 downto 0);

        signal ea:          std_logic_vector(15 downto 0);

        signal pc:              std_logic_vector(15 downto 0);

        signal md:          std_logic_vector(15 downto 0);

   signal left:        std_logic_vector(15 downto 0);

   signal right:       std_logic_vector(15 downto 0);

        signal out_alu:     std_logic_vector(15 downto 0);

        signal iv:          std_logic_vector(2 downto 0);

        signal nmi_req:     std_logic;

        signal nmi_ack:     std_logic;

        signal nmi_enable:  std_logic;

   signal fic:         std_logic; -- first instruction cycle

   signal lic:         std_logic; -- last instruction cycle

        signal state:        state_type;

        signal next_state:   state_type;

        signal return_state: state_type;

        signal saved_state:  state_type;

        signal st_ctrl:      st_type;

        signal iv_ctrl:      iv_type;

   signal pc_ctrl:      pc_type;

   signal ea_ctrl:      ea_type;

   signal op_ctrl:      op_type;

        signal pre_ctrl:     pre_type;

        signal md_ctrl:      md_type;

        signal acca_ctrl:    acca_type;

        signal accb_ctrl:    accb_type;

        signal ix_ctrl:      ix_type;

        signal iy_ctrl:      iy_type;

        signal cc_ctrl:      cc_type;

        signal dp_ctrl:      dp_type;

        signal sp_ctrl:      sp_type;

        signal up_ctrl:      up_type;

        signal left_ctrl:    left_type;

        signal right_ctrl:   right_type;

   signal alu_ctrl:     alu_type;

   signal addr_ctrl:    addr_type;

   signal dout_ctrl:    dout_type;

begin

----------------------------------

--

-- State machine stack

--

----------------------------------

--state_stack_proc: process( clk, hold, state_stack, st_ctrl, 

--                           return_state, fetch_state  )

state_stack_proc: process( clk, st_ctrl, return_state )

begin

  if clk'event and clk = '0' then

    if hold = '0' then

           case st_ctrl is

      when reset_st =>

        saved_state <= fetch_state;

      when push_st =>

                  saved_state <= return_state;

                when others =>

        null;

           end case;

    end if;

  end if;

end process;

----------------------------------

--

-- Interrupt Vector control

--

----------------------------------

--

int_vec_proc: process( clk, iv_ctrl )

begin

  if clk'event and clk = '0' then

    if hold = '0' then

      case iv_ctrl is

      when reset_iv =>

        iv <= RST_VEC;

      when nmi_iv =>

        iv <= NMI_VEC;

      when swi_iv =>

        iv <= SWI_VEC;

      when irq_iv =>

        iv <= IRQ_VEC;

      when firq_iv =>

        iv <= FIRQ_VEC;

      when swi2_iv =>

        iv <= SWI2_VEC;

      when swi3_iv =>

        iv <= SWI3_VEC;

                when others =>

                  null;

      end case;

    end if; -- hold

  end if; -- clk

end process;

----------------------------------

--

-- Program Counter Control

--

----------------------------------

--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )

pc_reg: process( clk )

begin

  if clk'event and clk = '0' then

    if hold = '0' then

    case pc_ctrl is

         when reset_pc =>

           pc <= (others=>'0');

         when load_pc =>

           pc <= out_alu(15 downto 0);

         when pull_lo_pc =>

           pc(7 downto 0) <= data_in;

         when pull_hi_pc =>

           pc(15 downto 8) <= data_in;

         when incr_pc =>

           pc <= pc + 1;

         when others =>

      null;

    end case;

         end if;

  end if;

end process;

----------------------------------

--

-- Effective Address  Control

--

----------------------------------

--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )

ea_reg: process( clk )

begin

  if clk'event and clk = '0' then

    if hold= '0' then

    case ea_ctrl is

         when reset_ea =>

           ea <= (others=>'0');

         when fetch_first_ea =>

           ea(7 downto 0) <= data_in;

      ea(15 downto 8) <= dp;

         when fetch_next_ea =>

           ea(15 downto 8) <= ea(7 downto 0);

      ea(7 downto 0)  <= data_in;

         when load_ea =>

           ea <= out_alu(15 downto 0);

         when others =>

      null;

    end case;

         end if;

  end if;

end process;

--------------------------------

--

-- Accumulator A

--

--------------------------------

--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )

acca_reg : process( clk )

begin

  if clk'event and clk = '0' then

    if hold = '0' then

    case acca_ctrl is

    when reset_acca =>

           acca <= (others=>'0');

         when load_acca =>

           acca <= out_alu(7 downto 0);

         when load_hi_acca =>

           acca <= out_alu(15 downto 8);

         when pull_acca =>

           acca <= data_in;

         when others =>

      null;

    end case;

         end if;

  end if;

end process;

--------------------------------

--

-- Accumulator B

--

--------------------------------

--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )

accb_reg : process( clk )

begin

  if clk'event and clk = '0' then

    if hold = '0' then

    case accb_ctrl is

    when reset_accb =>

           accb <= (others=>'0');

         when load_accb =>

           accb <= out_alu(7 downto 0);

         when pull_accb =>

           accb <= data_in;

         when others =>

      null;

    end case;

         end if;

  end if;

end process;

--------------------------------

--

-- X Index register

--

--------------------------------

--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )

ix_reg : process( clk )

begin

  if clk'event and clk = '0' then

    if hold = '0' then

    case ix_ctrl is

    when reset_ix =>

           xreg <= (others=>'0');

         when load_ix =>

           xreg <= out_alu(15 downto 0);

         when pull_hi_ix =>

           xreg(15 downto 8) <= data_in;

         when pull_lo_ix =>

           xreg(7 downto 0) <= data_in;

         when others =>

      null;

    end case;

         end if;

  end if;

end process;

--------------------------------

--

-- Y Index register

--

--------------------------------

--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )

iy_reg : process( clk )

begin

  if clk'event and clk = '0' then

    if hold = '0' then

    case iy_ctrl is

    when reset_iy =>

           yreg <= (others=>'0');

         when load_iy =>

           yreg <= out_alu(15 downto 0);

         when pull_hi_iy =>

           yreg(15 downto 8) <= data_in;

         when pull_lo_iy =>

           yreg(7 downto 0) <= data_in;

         when others =>

      null;

    end case;

         end if;

  end if;

end process;

--------------------------------

--