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davidgb |
--===========================================================================--
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-- --
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-- Synthesizable SWTPc 6809 Dynamic Address Translation Table --
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-- --
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--===========================================================================--
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19 |
dilbert57 |
--
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99 |
davidgb |
-- File name : datram.vhd
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--
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-- Entity name : dat_ram
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19 |
dilbert57 |
--
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99 |
davidgb |
-- Purpose : Implements a Dynamic Address Translation RAM module
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-- as found in the SWTPc MP-09 CPU card.
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-- Maps the high order 4 address bits to 8 address lines
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-- extending the memory addressing range from 64K to 1MByte
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-- Memory segments are mapped on 4 KByte boundaries
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-- The DAT registers are mapped at the the top of memory
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-- ($FFF0 - $FFFF) and are write only so can map behind ROM.
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-- Since the DAT is not supported by SWTBUG for the 6800,
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-- the resgisters reset state map the bottom 64K of RAM.
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19 |
dilbert57 |
--
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99 |
davidgb |
-- Dependencies : ieee.std_logic_1164
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-- ieee.std_logic_unsigned
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-- unisim.vcomponents
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--
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-- Author : John E. Kent
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--
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-- Email : dilbert57@opencores.org
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--
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-- Web : http://opencores.org/project,system09
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--
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-- Description :
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--
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-- DAT is initializedas follows:
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19 |
dilbert57 |
--
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99 |
davidgb |
-- DAT Dat Logical Physical
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-- Reg Val Addr Addr
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-- fff0 - 0f - page 0 - $0xxx = $00xxx (RAM)
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-- fff1 - 0e - page 1 - $1xxx = $01xxx (RAM)
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dilbert57 |
-- fff2 - 0d - page 2 - $2xxx = $02xxx (RAM)
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-- fff3 - 0c - page 3 - $3xxx = $03xxx (RAM)
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-- fff4 - 0b - page 4 - $4xxx = $04xxx (RAM)
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-- fff5 - 0a - page 5 - $5xxx = $05xxx (RAM)
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-- fff6 - 09 - page 6 - $6xxx = $06xxx (RAM)
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-- fff7 - 08 - page 7 - $7xxx = $07xxx (RAM)
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-- fff8 - 07 - page 8 - $8xxx = $08xxx (RAM)
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-- fff9 - 06 - page 9 - $9xxx = $09xxx (RAM)
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-- fffa - 05 - page A - $axxx = $0axxx (RAM)
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-- fffb - 04 - page B - $bxxx = $0bxxx (RAM)
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-- fffc - 03 - page C - $cxxx = $0cxxx (RAM)
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-- fffd - 02 - page D - $dxxx = $0dxxx (RAM)
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-- fffe - f1 - page E - $exxx = $fexxx (I/O)
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-- ffff - f0 - page F - $fxxx = $ffxxx (ROM/DMFA2)
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99 |
davidgb |
--
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-- Copyright (C) 2003 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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-- Version Date Author Changes
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--
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-- 0.1 2002-11-10 John Kent Initial version
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19 |
dilbert57 |
--
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99 |
davidgb |
-- 0.2 2006-11-21 John Kent Inverted bottom 4 bits of dat_addr
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-- so that it is compatible with SWTPc MP-09 card.
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dilbert57 |
--
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davidgb |
-- 0.3 2007-02-25 John Kent Modify the sensitivity lists
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--
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-- 0.4 2010-06-17 John Kent Update header and added GPL
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dilbert57 |
--
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-- 0.5 2010-12-10 John Kent Correction of pages in header documentation
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--
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19 |
dilbert57 |
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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118 |
dilbert57 |
--library unisim;
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-- use unisim.vcomponents.all;
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dilbert57 |
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entity dat_ram is
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port (
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clk : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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addr_hi : in std_logic_vector(3 downto 0);
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addr_lo : in std_logic_vector(3 downto 0);
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davidgb |
rw : in std_logic;
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dilbert57 |
data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0));
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end dat_ram;
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architecture rtl of dat_ram is
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99 |
davidgb |
signal dat_reg0 : std_logic_vector(7 downto 0);
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signal dat_reg1 : std_logic_vector(7 downto 0);
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signal dat_reg2 : std_logic_vector(7 downto 0);
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signal dat_reg3 : std_logic_vector(7 downto 0);
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signal dat_reg4 : std_logic_vector(7 downto 0);
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signal dat_reg5 : std_logic_vector(7 downto 0);
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signal dat_reg6 : std_logic_vector(7 downto 0);
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signal dat_reg7 : std_logic_vector(7 downto 0);
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signal dat_reg8 : std_logic_vector(7 downto 0);
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signal dat_reg9 : std_logic_vector(7 downto 0);
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dilbert57 |
signal dat_reg10 : std_logic_vector(7 downto 0);
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signal dat_reg11 : std_logic_vector(7 downto 0);
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signal dat_reg12 : std_logic_vector(7 downto 0);
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signal dat_reg13 : std_logic_vector(7 downto 0);
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signal dat_reg14 : std_logic_vector(7 downto 0);
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signal dat_reg15 : std_logic_vector(7 downto 0);
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begin
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---------------------------------
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--
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-- Write DAT RAM
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--
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---------------------------------
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--dat_write : process( clk, rst, addr_lo, cs, rw, data_in )
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dat_write : process( clk )
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begin
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if clk'event and clk = '0' then
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if rst = '1' then
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dat_reg0 <= "00001111";
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dat_reg1 <= "00001110";
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dat_reg2 <= "00001101";
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dat_reg3 <= "00001100";
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dat_reg4 <= "00001011";
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dat_reg5 <= "00001010";
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dat_reg6 <= "00001001";
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dat_reg7 <= "00001000";
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dat_reg8 <= "00000111";
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dat_reg9 <= "00000110";
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dat_reg10 <= "00000101";
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dat_reg11 <= "00000100";
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dat_reg12 <= "00000011";
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dat_reg13 <= "00000010";
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dat_reg14 <= "11110001";
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dat_reg15 <= "11110000";
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else
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if cs = '1' and rw = '0' then
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case addr_lo is
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when "0000" =>
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dat_reg0 <= data_in;
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when "0001" =>
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dat_reg1 <= data_in;
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when "0010" =>
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dat_reg2 <= data_in;
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when "0011" =>
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dat_reg3 <= data_in;
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when "0100" =>
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dat_reg4 <= data_in;
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when "0101" =>
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dat_reg5 <= data_in;
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when "0110" =>
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dat_reg6 <= data_in;
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when "0111" =>
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dat_reg7 <= data_in;
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when "1000" =>
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dat_reg8 <= data_in;
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when "1001" =>
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dat_reg9 <= data_in;
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when "1010" =>
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dat_reg10 <= data_in;
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when "1011" =>
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dat_reg11 <= data_in;
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when "1100" =>
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dat_reg12 <= data_in;
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when "1101" =>
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dat_reg13 <= data_in;
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when "1110" =>
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dat_reg14 <= data_in;
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when "1111" =>
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dat_reg15 <= data_in;
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when others =>
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null;
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end case;
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end if;
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end if;
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end if;
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end process;
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dat_read : process( addr_hi,
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dat_reg0, dat_reg1, dat_reg2, dat_reg3,
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dat_reg4, dat_reg5, dat_reg6, dat_reg7,
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dat_reg8, dat_reg9, dat_reg10, dat_reg11,
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dat_reg12, dat_reg13, dat_reg14, dat_reg15 )
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variable phy_addr : std_logic_vector( 7 downto 0 );
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begin
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case addr_hi is
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when "0000" =>
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phy_addr := dat_reg0;
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when "0001" =>
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phy_addr := dat_reg1;
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when "0010" =>
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phy_addr := dat_reg2;
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when "0011" =>
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phy_addr := dat_reg3;
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when "0100" =>
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phy_addr := dat_reg4;
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when "0101" =>
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phy_addr := dat_reg5;
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when "0110" =>
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phy_addr := dat_reg6;
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when "0111" =>
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phy_addr := dat_reg7;
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when "1000" =>
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phy_addr := dat_reg8;
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when "1001" =>
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phy_addr := dat_reg9;
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when "1010" =>
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phy_addr := dat_reg10;
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when "1011" =>
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phy_addr := dat_reg11;
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when "1100" =>
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phy_addr := dat_reg12;
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when "1101" =>
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phy_addr := dat_reg13;
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when "1110" =>
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phy_addr := dat_reg14;
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when "1111" =>
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phy_addr := dat_reg15;
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when others =>
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null;
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end case;
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data_out( 7 downto 4 ) <= phy_addr( 7 downto 4 );
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data_out( 3 downto 0 ) <= not( phy_addr( 3 downto 0 ) );
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end process;
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end rtl;
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