OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [VHDL/] [datram.vhd] - Blame information for rev 66

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 dilbert57
--===========================================================================--
2
--
3
--  S Y N T H E Z I A B L E    Dynamic Address Translation Registers
4
--
5
--  www.OpenCores.Org - December 2002
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : datram.vhd
9
--
10
-- entity name    : dat_ram
11
--
12
-- Purpose        : Implements a Dynamic Address Translation RAM module
13
--                  Maps the high order 4 address bits to 8 address lines
14
--                  extending the memory addressing range to 1 Mbytes
15
--                  Memory segments are mapped on 4 KByte boundaries
16
--                  The DAT registers map to the top of memory 
17
--                  ($FFF0 - $FFFF) and are write only so can map behind ROM.
18
--                  Since the DAT is not supported by SWTBUG for the 6800,
19
--                  the resgisters reset state map the bottom 64K of RAM. 
20
--                  
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--
24
-- Author         : John E. Kent      
25
--
26
--===========================================================================----
27
--
28
-- Revision History:
29
--
30
-- Date          Revision  Author 
31
-- 10 Nov 2002   0.1       John Kent
32
--
33
-- 21 Nov 2006   0.2       John Kent
34
-- Inverted bottom 4 bits of dat_addr
35
-- so that it is compatible with SWTPc MP-09 card.
36
-- DAT is initializedas follows:
37
--
38
-- DAT    Dat           Logical Physical
39
-- Reg    Val           Addr    Addr
40
--      fff0 - 0f - page 0 - $0xxx = $00xxx (RAM)
41
--      fff1 - 0e - page 1 - $1xxx = $01xxx (RAM) 
42
--      fff2 - 0d - page 0 - $2xxx = $02xxx (RAM)
43
--      fff3 - 0c - page 0 - $3xxx = $03xxx (RAM)
44
--      fff4 - 0b - page 0 - $4xxx = $04xxx (RAM)
45
--      fff5 - 0a - page 0 - $5xxx = $05xxx (RAM)
46
--      fff6 - 09 - page 0 - $6xxx = $06xxx (RAM)
47
--      fff7 - 08 - page 0 - $7xxx = $07xxx (RAM)
48
--      fff8 - 07 - page 0 - $8xxx = $08xxx (RAM)
49
--      fff9 - 06 - page 0 - $9xxx = $09xxx (RAM)
50
--      fffa - 05 - page 0 - $axxx = $0axxx (RAM)
51
--      fffb - 04 - page 0 - $bxxx = $0bxxx (RAM)
52
--      fffc - 03 - page 0 - $cxxx = $0cxxx (RAM)
53
--      fffd - 02 - page 0 - $dxxx = $0dxxx (RAM)
54
--      fffe - f1 - page 0 - $exxx = $fexxx (I/O)
55
--      ffff - f0 - page 0 - $fxxx = $ffxxx (ROM/DMFA2)
56
 
57
-- 25 Feb 2007   0.3      John Kent
58
-- modify the sensitivity lists
59
--
60
 
61
library ieee;
62
  use ieee.std_logic_1164.all;
63
  use ieee.std_logic_unsigned.all;
64
library unisim;
65
  use unisim.vcomponents.all;
66
 
67
entity dat_ram is
68
        port (
69
         clk       : in  std_logic;
70
    rst       : in  std_logic;
71
    cs        : in  std_logic;
72
    rw        : in  std_logic;
73
    addr_hi   : in  std_logic_vector(3 downto 0);
74
    addr_lo   : in  std_logic_vector(3 downto 0);
75
    data_in   : in  std_logic_vector(7 downto 0);
76
         data_out  : out std_logic_vector(7 downto 0));
77
end dat_ram;
78
 
79
architecture rtl of dat_ram is
80
signal dat_reg0 : std_logic_vector(7 downto 0);
81
signal dat_reg1 : std_logic_vector(7 downto 0);
82
signal dat_reg2 : std_logic_vector(7 downto 0);
83
signal dat_reg3 : std_logic_vector(7 downto 0);
84
signal dat_reg4 : std_logic_vector(7 downto 0);
85
signal dat_reg5 : std_logic_vector(7 downto 0);
86
signal dat_reg6 : std_logic_vector(7 downto 0);
87
signal dat_reg7 : std_logic_vector(7 downto 0);
88
signal dat_reg8 : std_logic_vector(7 downto 0);
89
signal dat_reg9 : std_logic_vector(7 downto 0);
90
signal dat_reg10 : std_logic_vector(7 downto 0);
91
signal dat_reg11 : std_logic_vector(7 downto 0);
92
signal dat_reg12 : std_logic_vector(7 downto 0);
93
signal dat_reg13 : std_logic_vector(7 downto 0);
94
signal dat_reg14 : std_logic_vector(7 downto 0);
95
signal dat_reg15 : std_logic_vector(7 downto 0);
96
 
97
begin
98
 
99
---------------------------------
100
--
101
-- Write DAT RAM
102
--
103
---------------------------------
104
 
105
--dat_write : process( clk, rst, addr_lo, cs, rw, data_in )
106
dat_write : process( clk )
107
begin
108
  if clk'event and clk = '0' then
109
    if rst = '1' then
110
      dat_reg0  <= "00001111";
111
      dat_reg1  <= "00001110";
112
      dat_reg2  <= "00001101";
113
      dat_reg3  <= "00001100";
114
      dat_reg4  <= "00001011";
115
      dat_reg5  <= "00001010";
116
      dat_reg6  <= "00001001";
117
      dat_reg7  <= "00001000";
118
      dat_reg8  <= "00000111";
119
      dat_reg9  <= "00000110";
120
      dat_reg10 <= "00000101";
121
      dat_reg11 <= "00000100";
122
      dat_reg12 <= "00000011";
123
      dat_reg13 <= "00000010";
124
      dat_reg14 <= "11110001";
125
      dat_reg15 <= "11110000";
126
    else
127
           if cs = '1' and rw = '0' then
128
        case addr_lo is
129
             when "0000" =>
130
                    dat_reg0 <= data_in;
131
             when "0001" =>
132
                    dat_reg1 <= data_in;
133
             when "0010" =>
134
                    dat_reg2 <= data_in;
135
             when "0011" =>
136
                    dat_reg3 <= data_in;
137
             when "0100" =>
138
                    dat_reg4 <= data_in;
139
             when "0101" =>
140
                    dat_reg5 <= data_in;
141
             when "0110" =>
142
                    dat_reg6 <= data_in;
143
             when "0111" =>
144
                    dat_reg7 <= data_in;
145
             when "1000" =>
146
                    dat_reg8 <= data_in;
147
             when "1001" =>
148
                    dat_reg9 <= data_in;
149
             when "1010" =>
150
                    dat_reg10 <= data_in;
151
             when "1011" =>
152
                    dat_reg11 <= data_in;
153
             when "1100" =>
154
                    dat_reg12 <= data_in;
155
             when "1101" =>
156
                    dat_reg13 <= data_in;
157
             when "1110" =>
158
                    dat_reg14 <= data_in;
159
             when "1111" =>
160
                    dat_reg15 <= data_in;
161
        when others =>
162
                    null;
163
                  end case;
164
           end if;
165
         end if;
166
  end if;
167
end process;
168
 
169
dat_read : process(  addr_hi,
170
                     dat_reg0, dat_reg1, dat_reg2, dat_reg3,
171
                     dat_reg4, dat_reg5, dat_reg6, dat_reg7,
172
                     dat_reg8, dat_reg9, dat_reg10, dat_reg11,
173
                     dat_reg12, dat_reg13, dat_reg14, dat_reg15 )
174
variable phy_addr : std_logic_vector( 7 downto 0 );
175
begin
176
      case addr_hi is
177
             when "0000" =>
178
                    phy_addr := dat_reg0;
179
             when "0001" =>
180
                    phy_addr := dat_reg1;
181
             when "0010" =>
182
                    phy_addr := dat_reg2;
183
             when "0011" =>
184
                    phy_addr := dat_reg3;
185
             when "0100" =>
186
                    phy_addr := dat_reg4;
187
             when "0101" =>
188
                    phy_addr := dat_reg5;
189
             when "0110" =>
190
                    phy_addr := dat_reg6;
191
             when "0111" =>
192
                    phy_addr := dat_reg7;
193
             when "1000" =>
194
                    phy_addr := dat_reg8;
195
             when "1001" =>
196
                    phy_addr := dat_reg9;
197
             when "1010" =>
198
                    phy_addr := dat_reg10;
199
             when "1011" =>
200
                    phy_addr := dat_reg11;
201
             when "1100" =>
202
                    phy_addr := dat_reg12;
203
             when "1101" =>
204
                    phy_addr := dat_reg13;
205
             when "1110" =>
206
                    phy_addr := dat_reg14;
207
             when "1111" =>
208
                    phy_addr := dat_reg15;
209
        when others =>
210
                    null;
211
                end case;
212
      data_out( 7 downto 4 ) <= phy_addr( 7 downto 4 );
213
      data_out( 3 downto 0 ) <= not( phy_addr( 3 downto 0 ) );
214
 
215
end process;
216
 
217
end rtl;
218
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.