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dilbert57 |
--===========================================================================--
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-- --
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-- Synthesizable unsigned 32 bit integer divider --
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-- --
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--===========================================================================--
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--
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-- File name : divs32.vhd
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--
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-- Entity name : sdiv32
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--
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-- Purpose : Implements a 32 bit signed integer divider
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--
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-- Dependencies : ieee.std_logic_1164
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-- ieee.numeric_std
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-- ieee.std_logic_unsigned
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--
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-- Author : John E. Kent
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--
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-- Email : dilbert57@opencores.org
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--
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-- Web : http://opencores.org/project,system09
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--
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-- Registers :
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-- 0 Dividend 1st Byte MSB
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-- 1 2nd Byte
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-- 2 3rd Byte
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-- 3 4th Byte LSB
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-- 4 Divisor 1st Byte MSB
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-- 5 2nd Byte
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-- 6 3rd Byte
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-- 7 4th Byte LSB
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-- 8 quotient 1st Byte MSB
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-- 9 2nd Byte
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-- 10 3rd Byte
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-- 11 4th byte LSB
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-- 12 Remainder 1st Byte MSB
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-- 13 2nd Byte
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-- 14 3rd Byte
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-- 15 4th byte LSB
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--
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-- 32 bit unsigned binary division.
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--
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-- Write the most significant byte of the dividend at the 0th register first
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-- down to the least significant byte of the divisor in the 7th register.
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-- Writing the least significant byte of the divisor will start the division.
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--
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-- The 32 bit division will take 32 clock cycles.
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-- There is no status register so the CPU must execute a software delay
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-- to wait 32 clock cycles after the least significant byte of the divisor
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-- is written before reading the quotient of the division or the remainder.
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--
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-- The dividend and divisor input registers are read/writable
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-- The quotient and remainder output registers are read only.
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-- The quotient register holds the integer part of the result of the division.
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-- The remainder register holds the dividend modulo the divisor.
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--
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-- Copyright (C) 2012 - 2014 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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-- Version Author Date Changes
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--
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-- 0.1 John Kent 2012-04-06 Initial version
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-- 0.2 John Kent 2014-05-07 Replaced Status register with 4 byte remainder
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-- 0.3 John Kent 2016-02-04 Shortend result_temp to 33 bits so subtraction is faster.
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-- Add hold output to pause CPU until result is valid.
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-- 0.4 John Kent 2018-03-21 Changed unsigned udiv32 to signed sdiv32
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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--library unisim;
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-- use unisim.vcomponents.all;
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entity sdiv32 is
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port (
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--
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-- CPU Interface signals
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--
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clk : in std_logic; -- CPU Clock
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rst : in std_logic; -- Reset input (active high)
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cs : in std_logic; -- Chip Select
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addr : in std_logic_vector(3 downto 0); -- Register Select
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rw : in std_logic; -- Read / Not Write
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data_in : in std_logic_vector(7 downto 0); -- Data Bus In
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data_out : out std_logic_vector(7 downto 0); -- Data Bus Out
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hold : out std_logic -- Result access hold
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);
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end sdiv32;
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--================== End of entity ==============================--
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-------------------------------------------------------------------
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-- Architecture for unsigned 32 bit integer divider interface
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-------------------------------------------------------------------
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architecture rtl of sdiv32 is
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signal dividend : std_logic_vector(31 downto 0) := (others => '0');
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signal divisor : std_logic_vector(31 downto 0) := (others => '0');
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signal result : std_logic_vector(63 downto 0) := (others => '0');
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signal quotient : std_logic_vector(31 downto 0) := (others => '0');
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signal remainder : std_logic_vector(31 downto 0) := (others => '0');
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signal count : std_logic_vector( 4 downto 0) := (others => '0');
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signal req_flag : std_logic := '0'; -- Request Division
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signal act_flag : std_logic := '0'; -- Division Active
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begin
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--
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-- Write registers
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--
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sdiv32_write : process( clk, rst, cs, rw, addr, data_in, req_flag, act_flag )
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begin
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if rst = '1' then
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dividend <= (others=> '0'); -- reset the dividend to zero
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divisor <= (others=> '0'); -- reset the divisor to zero
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req_flag <= '0'; -- the default state is stopped
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elsif falling_edge( clk ) then
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--
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-- write to registers
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--
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if (cs = '1') and (rw = '0') then
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case addr is
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when "0000" =>
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dividend(31 downto 24) <= data_in;
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when "0001" =>
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dividend(23 downto 16) <= data_in;
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when "0010" =>
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dividend(15 downto 8) <= data_in;
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when "0011" =>
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dividend( 7 downto 0) <= data_in;
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when "0100" =>
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divisor(31 downto 24) <= data_in;
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when "0101" =>
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divisor(23 downto 16) <= data_in;
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when "0110" =>
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divisor(15 downto 8) <= data_in;
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when "0111" =>
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divisor( 7 downto 0) <= data_in;
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--
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-- writing the last byte of the divisor
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-- should pulse the request flag high for one cycle
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-- starting the division,
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-- provided the previous division has finished
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--
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if (req_flag = '0') and (act_flag = '0') then
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req_flag <= '1';
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end if;
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when others =>
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null;
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end case;
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end if;
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end if; -- rst/clk
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if (req_flag = '1') and (act_flag = '1') then
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req_flag <= '0';
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end if;
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hold <= cs and rw and addr(3) and act_flag;
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end process;
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--
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-- Read registers
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--
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sdiv32_read : process( addr, dividend, divisor, quotient, remainder )
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begin
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case addr is
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when "0000" =>
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data_out <= dividend(31 downto 24);
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when "0001" =>
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data_out <= dividend(23 downto 16);
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when "0010" =>
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data_out <= dividend(15 downto 8);
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when "0011" =>
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data_out <= dividend( 7 downto 0);
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when "0100" =>
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data_out <= divisor(31 downto 24);
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when "0101" =>
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data_out <= divisor(23 downto 16);
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when "0110" =>
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data_out <= divisor(15 downto 8);
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when "0111" =>
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data_out <= divisor( 7 downto 0);
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when "1000" =>
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data_out <= quotient(31 downto 24);
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when "1001" =>
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data_out <= quotient(23 downto 16);
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when "1010" =>
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data_out <= quotient(15 downto 8);
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when "1011" =>
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data_out <= quotient( 7 downto 0);
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when "1100" =>
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data_out <= remainder(31 downto 24);
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when "1101" =>
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data_out <= remainder(23 downto 16);
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when "1110" =>
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data_out <= remainder(15 downto 8);
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when "1111" =>
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data_out <= remainder(7 downto 0);
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when others =>
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null;
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end case;
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end process;
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--
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-- When the finish flag is high and the start flag goes high,
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-- start the division by clearing the finish flag
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-- When the finish flag is low and the count reaches 31
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sdiv32_divide : process( rst, clk, dividend, divisor, remainder, req_flag, act_flag, count )
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variable result_temp : std_logic_vector(32 downto 0);
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begin
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if (rst = '1') then
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result <= (others=>'0');
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result_temp := (others=>'0');
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remainder <= (others=>'0');
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quotient <= (others=>'0');
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count <= (others=>'0');
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act_flag <= '0'; -- default state is inactive
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elsif falling_edge( clk ) then
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--
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-- activate the division if the last division was complete
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-- i.e. the active flag was clear
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-- and the last byte of the divisor was just written
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-- i.e. the request flag was pulsed high for one clock cycle
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--
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if (req_flag = '1') and (act_flag = '0') then
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--
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-- put dividend in result and make positive
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--
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result(63 downto 32) <= (others => '0');
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if dividend(31) = '0' then
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result(31 downto 0) <= dividend; -- Dividend in the Least Significant Word of remainder
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else
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result(31 downto 0) <= "00000000000000000000000000000000" - dividend;
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end if;
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--
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-- Initialize temp variables
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--
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result_temp := (others => '0'); -- Clear the remainder temp variable
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--
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-- reset bit counter and activate division
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--
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count <= (others => '0'); -- Clear the bit counter
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act_flag <= '1'; -- Flag division in progress
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elsif (req_flag = '0') and (act_flag = '1') then -- If active flag is set the division must be in progress
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--
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-- if dividend positive, subrtact divisor
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-- if dividend negative, add divisor
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--
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if (divisor(31)) = '0' then
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result_temp := result(63 downto 31) - (divisor(31) & divisor); -- subtract the divisor from the remainder if positive
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else
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result_temp := result(63 downto 31) + (divisor(31) & divisor); -- add the divisor to the remainder if negative
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end if;
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--
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-- if carry clear from add or subract
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-- update the remainder
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--
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if result_temp(32) = '0' then -- if the remainder temp carry is clear
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result(63 downto 32) <= result_temp(31 downto 0); -- update the result with remainder
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else
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result(63 downto 32) <= result(62 downto 31); -- otherwise shift remainder up one bit
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end if;
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--
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-- shift the quotient up one bit
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-- The LSBit is the inverted remainder carry
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--
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result(31 downto 1) <= result(30 downto 0); -- shift lower remainder up one bit
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result(0) <= not result_temp(32); -- shift quotient in bottom of remainder
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--
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-- 32 bit division should take 32 clock cycles
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--
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count <= count + "00001";
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--
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-- When the count reaches the 31st cycle of the division
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-- flag that the division is complete by clrearing the active flag.
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--
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if count = "11111" then
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act_flag <= '0'; -- flag division complete
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end if;
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end if; -- start/finish
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--
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-- negating the result will take another clock cycle.
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-- If the cpu is held on a read access of the
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-- quotient or remainder it may get the wrong result.
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--
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--
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-- quotient has sign of dividend exclusive or divisor
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--
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if( (dividend(31) xor divisor(31)) = '0') then
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quotient <= result(31 downto 0);
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else
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quotient <= "00000000000000000000000000000000" - result(31 downto 0);
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end if;
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--
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-- remainder has sign of dividend
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--
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if dividend(31) = '0' then
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remainder <= result(63 downto 32);
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else
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remainder <= "00000000000000000000000000000000" - result(63 downto 32);
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end if;
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end if; -- rst/clk
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end process;
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end rtl; -- end of architecture
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