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davidgb |
--===========================================================================--
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-- --
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-- Synthesizable 6844 Compatible DMA Controller --
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-- --
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--===========================================================================--
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--
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-- File name : dma6844.vhd
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--
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-- Entity name : dma6844
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--
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-- Purpose : Implements a 6844 compatible Direct Memory Access Controller
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-- It is intended for use with 68xx compatible FPGA SoCs.
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--
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-- Dependencies : ieee.std_logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_arith
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-- unisim.vcomponents
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--
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-- Author : John E. Kent
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--
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-- Email : dilbert57@opencores.org
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--
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-- Web : http://opencores.org/project,system09
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--
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-- Registers :
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--
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-- 4 Channel version
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--
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-- IO + 0 = DMA_AH0 = Address Register 0 High
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-- IO + 1 = DMA_AL0 = Address Register 0 Low
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-- IO + 2 = DMA_CH0 = Count Register 0 High
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-- IO + 3 = DMA_CL0 = Count Register 0 Low
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--
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-- IO + 4 = DMA_AH1 = Address Register 1 High
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-- IO + 5 = DMA_AL1 = Address Register 1 Low
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-- IO + 6 = DMA_CH1 = Count Register 1 High
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-- IO + 7 = DMA_CL1 = Count Register 1 Low
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--
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-- IO + 8 = DMA_AH2 = Address Register 2 High
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-- IO + 9 = DMA_AL2 = Address Register 2 Low
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-- IO + 10 = DMA_CH2 = Count Register 2 High
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-- IO + 11 = DMA_CL2 = Count Register 2 Low
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--
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-- IO + 12 = DMA_AH3 = Address Register 3 High
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-- IO + 13 = DMA_AL3 = Address Register 3 Low
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-- IO + 14 = DMA_CH3 = Count Register 3 High
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-- IO + 15 = DMA_CL3 = Count Register 3 Low
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--
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-- IO + 16 = DMA_CC0 = Channel Control Register 0
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-- IO + 17 = DMA_CC1 = Channel Control Register 1
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-- IO + 18 = DMA_CC2 = Channel Control Register 2
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-- IO + 19 = DMA_CC3 = Channel Control Register 3
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-- Bit[7] = DMA_DEF = DMA END FLAG (DEND)
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-- Bit[6] = DMA_BSY = DMA BUSY FLAG (READ ONLY)
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-- Bit[3] = DMA_AUD = DMA ADDRESS NOT UP/DOWN
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-- Bit[2] = DMA_MCA = DMA MODE CONTROL 0=>DRQ2 1=>DRQ1
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-- Bit[1] = DMA_MCB = DMA MODE CONTROL 0=>SINGLE 1=>BLOCK
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-- 0 0 = DMA_MD2 = DMA MODE 2 - SINGLE TRANSFER - DRQ2
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-- 0 1 = DMA_MD3 = DMA MODE 3 - BLOCK TRANSFER - DRQ2
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-- 1 0 = DMA_MD1 = DMA MODE 1 - SINGLE TRANSFER - DRQ1
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-- 1 1 = DMA_MDU = DMA MODE 4 - BLOCK TRANSFER - DRQ1 - ACTUALLY UDEFINED
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-- Bit[0] = DMA_RW = DMA READ/NOT WRITE
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--
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-- IO + 20 = DMA_PRI = DMA Priority Control Register
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-- Bit[7] = DMA_ROT = DMA Rotate Control 0=>FIXED 1=>ROTATE
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-- Bit[3] = DMA_RE3 = DMA REQUEST ENABLE #3
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-- Bit[2] = DMA_RE2 = DMA REQUEST ENABLE #2
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-- Bit[1] = DMA_RE1 = DMA REQUEST ENABLE #1
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-- Bit[0] = DMA_RE0 = DMA REQUEST ENABLE #0
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--
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-- IO + 21 = DMA_INT = DMA Interrupt Control Register
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-- Bit[7] = DMA_IEF = DMA END IRQ FLAG
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-- Bit[3] = DMA_IE3 = DMA END IRQ ENABLE #3
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-- Bit[2] = DMA_IE2 = DMA END IRQ ENABLE #2
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-- Bit[1] = DMA_IE1 = DMA END IRQ ENABLE #1
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-- Bit[0] = DMA_IE0 = DMA END IRQ ENABLE #0
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--
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-- IO + 22 = DMA_CHN = DMA Data Chain register
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-- Bit[3] = DMA_C24 = TWO/FOUR CHANNEL SELECT
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-- Bit[2] = DMA_DCB = DATA CHAIN CHANNEL SELECT B
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-- Bit[1] = DMA_DCA = DATA CHAIN CHANNEL SELECT A
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-- Bit[0] = DMA_DCE = DATA CHAIN ENABLE
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--
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-- Copyright (C) 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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-- Revision Author Date Description
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-- 0.1 John E. Kent 18th April 2010 Initial release
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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library unisim;
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use unisim.vcomponents.all;
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entity dma6844 is
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generic (
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ADDR_WIDTH = 16;
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DATA_WIDTH = 8;
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CHAN_COUNT = 4
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)
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port (
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--
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-- CPU Slave Interface
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--
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clk : in std_logic;
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rst : in std_logic;
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rw : out std_logic;
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cs : out std_logic;
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addr : in std_logic_vector(LOG2(CHAN_COUNT*4*ADDR_WIDTH/DATA_WIDTH)-1 downto 0);
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data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
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data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
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irq : out std_logic;
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--
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-- Bus Master Interface
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--
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breq : out std_logic;
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bgnt : in std_logic;
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brw : out std_logic;
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bvma : out std_logic;
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baddr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
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--
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-- Device Interface
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--
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txreq : in std_logic_vector(CHAN_COUNT-1 downto 0);
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txstb : out std_logic_vector(CHAN_COUNT-1 downto 0);
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txack : out std_logic_vector(CHAN_COUNT-1 downto 0);
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txend : out std_logic_vector(CHAN_COUNT-1 downto 0)
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);
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end dma6844;
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architecture rtl of dma6844 is
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constant REG_COUNT : integer = (CHAN_COUNT * 2 * ADDR_WIDTH / DATA_WIDTH) + DMA_CHAN + 3;
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subtype addr_subtype is std_logic_vector(ADDR_WIDTH-1 downto 0);
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subtype data_subtype is std_logic_vector(DATA_WIDTH-1 downto 0);
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type addr_type is array(0 to CHAN_COUNT-1) of addr_subtype;
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type data_type is array(0 to CHAN_COUNT-1) of data_subtype;
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type reg_type is array(0 to REG_COUNT-1) of data_subtype;
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signal dma_addr : addr_type;
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signal dma_count : addr_type;
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signal dma_in_reg : reg_type;
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signal dma_out_reg : reg_type;
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signal dma_reg_wr : std_logic := '0';
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signal dma_reg_rd : std_logic := '0';
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--
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-- Registers
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--
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signal dma_adh_reg : data_type;
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signal dma_adl_reg : data_type;
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signal dma_cth_reg : data_type;
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signal dma_ctl_reg : data_type;
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signal dma_chc_reg : data_type;
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signal dma_pri_reg : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal dma_irq_reg : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal dma_chn_reg : std_logic_vector(DATA_WIDTH-1 downto 0);
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begin
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--
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-- Write to DMA input register
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--
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dma_reg_write : process( clk, rst )
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variable reg_addr : integer := 0;
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begin
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if( falling_edge(clk) )
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if( rst = '1' ) then
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for i in 0 to CHAN_COUNT-1 loop
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dma_addr(i) <= (others=>'0');
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dma_count(i) <= (others=>'0');
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end loop;
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for i in 0 to REG_COUNT-1 loop
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dma_in_reg(i) <= (others=>'0');
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end loop;
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else
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if( cs='1' and rw='0' ) then
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reg_addr := conv_integer(addr(ADDR_WIDTH-1 downto 0));
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if( reg_addr < REG_COUNT ) then
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dma_in_reg(reg_addr) <= data_in;
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end if;
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end if;
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end if;
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end if;
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end process;
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--
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-- Assign input register to specific register names
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--
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dma_reg_assign : process( dma_in_reg )
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begin
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for i in 0 to CHAN_COUNT-1 loop
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dma_adh_reg(i) <= dma_in_reg((i*4)+0);
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dma_adl_reg(i) <= dma_in_reg((i*4)+1);
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dma_cth_reg(i) <= dma_in_reg((i*4)+2);
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dma_ctl_reg(i) <= dma_in_reg((i*4)+3);
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dma_chc_reg(i) <= dma_in_reg((CHAN_COUNT*4)+i);
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end loop;
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dma_pri_reg <= dma_in_reg((CHAN_COUNT*5)+0);
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dma_irq_reg <= dma_in_reg((CHAN_COUNT*5)+1);
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dma_chn_reg <= dma_in_reg((CHAN_COUNT*5)+2);
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end process;
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--
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-- Process Transfer Request Inputs
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--
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dma_tx_req : process( clk, rst, txreq )
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begin
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if( rising_edge( clk ) ) then
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if( rst='1' ) then
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else
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for i in 0 to CHAN_COUNT-1 loop
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end loop;
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end if;
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end if;
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end process;
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end architecture rtl;
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