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[/] [System09/] [trunk/] [rtl/] [VHDL/] [epp.vhd] - Blame information for rev 79

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1 65 davidgb
--===========================================================================----
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--
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--  S Y N T H E Z I A B L E    epp - Enhanced Parallel Port
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--
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--  www.OpenCores.Org - September 2003
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--  This core adheres to the GNU public license  
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--
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-- File name      : epp.vhd
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--
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-- Purpose        : Simple Parallel Port for System09
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_unsigned
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--
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-- Uses           : None
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--
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-- Author         : John E. Kent      
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--                  dilbert57@opencores.org      
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--
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--===========================================================================----
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--
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-- Revision History:
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--===========================================================================--
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--
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-- Version 0.1 - 6th Sep 2008
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--  Generated from ioport.vhd
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--
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--===========================================================================
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--
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--  Parallel printer port pin assignment
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-- 
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--  Pin No (DB25)  SPP Signal      EPP Signal    Direction Register  Bit Inverted
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--  1             nStrobe            Write_n       Out       Control-0 Yes
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--  2             Data0           Data0         In/Out    Data-0        No
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--  3             Data1           Data1         In/Out    Data-1        No
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--  4             Data2           Data2         In/Out    Data-2        No
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--  5             Data3           Data3         In/Out    Data-3        No
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--  6             Data4           Data4         In/Out    Data-4        No
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--  7             Data5           Data5         In/Out    Data-5        No
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--  8             Data6           Data6         In/Out    Data-6        No
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--  9             Data7           Data7         In/Out    Data-7        No
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--  10            nAck            Interrupt     In        Status-6  No
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--  11            Busy            Wait          In        Status-7  Yes
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--  12            Paper-Out       Spare         In        Status-5  No
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--  13            Select          Spare         In        Status-4  No
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-- 
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--  14            Linefeed        Data_Strobe_n Out       Control-1 Yes
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--  15            nError          Spare         In        Status-3  No
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--  16             nInitialize     Reset         Out       Control-2 No
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--  17             nSelect-Printer Addr_Strobe_n Out       Control-3 Yes
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--  18-25          Ground          Ground        -         -         -
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-- 
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--  Address                              MSB                         LSB
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--                                 Bit:    7   6   5   4   3   2   1   0
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-- Base   (SPP Data port)    Write Pin:          9   8   7   6   5   4   3   2
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-- Base+1 (SPP Status port)  Read  Pin:  ~11  10  12  13  15                            
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-- Base+2 (SPP Control port) Write Pin:                  ~17  16 ~14  ~1
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-- Base+3 (EPP Address port) R/W
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-- Base+4 (EPP Data port)    R/W
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-- 
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--  ~ indicates a hardware inversion of the bit.
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-- 
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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entity epp is
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        port (
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         clk       : in  std_logic;
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    rst       : in  std_logic;
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    cs        : in  std_logic;
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    rw        : in  std_logic;
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    addr      : in  std_logic_vector(2 downto 0);
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    data_in   : in  std_logic_vector(7 downto 0);
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         data_out  : out std_logic_vector(7 downto 0);
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         epp_data  : out std_logic_vector(7 downto 0);
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         epp_stat  : in  std_logic_vector(7 downto 3);
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         epp_ctrl  : out std_logic_vector(3 downto 0);
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         hold      : out std_logic;
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         irq       : out std_logic
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         );
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end;
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architecture rtl of epp is
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constant CTRL_RW_BIT : integer := 0;
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constant CTRL_DS_BIT : integer := 1;
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constant CTRL_RS_BIT : integer := 2;
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constant CTRL_AS_BIT : integer := 3;
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constant STAT_IR_BIT : integer := 6;
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constant STAT_WT_BIT : integer := 7;
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signal epp_ctrl_reg : std_logic_vector(3 downto 0);
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begin
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--
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-- Read / Write control
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--
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epp_control : process( rst, clk, cs, rw, addr, epp_stat, epp_crl_reg, data_in )
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begin
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  if rst = '1' then
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    epp_ctrl_reg(CTRL_RW_BIT) <= '1';
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    epp_ctrl_reg(CTRL_AS_BIT) <= '1';
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    epp_ctrl_reg(CTRL_RS_BIT) <= '0';
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    epp_ctrl_reg(CTRL_DS_BIT) <= '1';
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    epp_data <= (others=>'Z');
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  --
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  -- clock controls on rising edge
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  --
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  elsif clk'event and clk = '1' then
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    epp_ctrl_reg(CTRL_RS_BIT) <= '1';
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    if cs = '1' then
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      case addr is
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                --
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                -- address register
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                --
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      when "011" =>
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        --
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        -- set Data port direction
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        --
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             if rw = '1' then
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          epp_ctrl_reg(CTRL_RW_BIT) <= '1';
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          epp_data <= (others=>'Z');
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        else
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          epp_ctrl_reg(CTRL_RW_BIT) <= '0';
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                         epp_data <= data_in;
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        end if;
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        --
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                  -- initiale an address strobe
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                  --
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        if epp_stat(STAT_WT_BIT) = '0' then
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          epp_ctrl_reg(CTRL_AS_BIT) <= '0';
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        elsif epp_stat(STAT_WT_BIT) = '1' then
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          epp_ctrl_reg(CTRL_AS_BIT) <= '1';
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        end if;
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                --
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                -- data register
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                --
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      when "100" =>
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                  --
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                  -- set data port direction
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                  --
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             if rw = '1' then
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          epp_ctrl_reg(CTRL_RW_BIT) <= '1';
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          epp_data <= (others=>'Z');
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        else
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          epp_ctrl_reg(CTRL_RW_BIT) <= '0';
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                         epp_data <= data_in;
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        end if;
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                  --
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                  -- initiate a data strobe
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                  --
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        if epp_stat(STAT_WT_BIT) = '0' then
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          epp_ctrl_reg(CTRL_DS_BIT) <= '0';
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        elsif epp_stat(STAT_WT_BIT) = '1' then
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          epp_ctrl_reg(CTRL_DS_BIT) <= '1';
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        end if;
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      when others =>
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        epp_ctrl_reg(CTRL_RW_BIT) <= '1';
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        epp_ctrl_reg(CTRL_AS_BIT) <= '1';
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        epp_ctrl_reg(CTRL_DS_BIT) <= '1';
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        epp_data <= (others=>'Z');
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                  null;
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      end case; -- addr
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    end if; -- cs
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  end if; -- clk / reset
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  irq      <= epp_stat(STAT_IR_BIT);
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  hold     <= not( epp_ctrl_reg(CTRL_DS_BIT) ) or not( epp_ctrl_reg(CTRL_AS_BIT) );
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  epp_ctrl <= epp_ctrl_reg;
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  data_out <= epp_data;
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end process;
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end rtl;
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