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[/] [System09/] [trunk/] [rtl/] [VHDL/] [mul32.vhd] - Blame information for rev 101

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1 99 davidgb
--===========================================================================--
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--                                                                           --
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--  mul32.vhd - Synthesizable 32 bit Multiplier Register for Spartan 3/3E    --
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--                                                                           --
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--===========================================================================--
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--
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--  File name      : mul32.vhd
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--
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--  Entity name    : mul32
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--
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--  Purpose        : Implements a 32 bit x 32 bit hardware multiplier register
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--                   with 64 bit result. Consists of 16 x 8 bit registers.
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--                   Designed for Spartan 3/3E with 18 x 18 bit multiplier blocks. 
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--                  
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--  Dependencies   : ieee.std_logic_1164
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--                   ieee.std_logic_unsigned
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--                   unisim.vcomponents
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--
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--  Author         : John E. Kent
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--
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--  Email          : dilbert57@opencores.org      
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--
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--  Web            : http://opencores.org/project,system09
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--
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--  Registers      :
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-- 
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--   0 R/W left   input  Most Significant Byte
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--   1 R/W left   input
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--   2 R/W left   input
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--   3 R/W left   input  Least Significant Byte
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--   4 R/W right  input  Most Significant Byte
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--   5 R/W right  input
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--   6 R/W right  input
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--   7 R/W right  input  Least Significant Byte
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--   8 R/O result output Most Significant Byte
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--   9 R/O result output 
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--  10 R/O result output 
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--  11 R/O result output 
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--  12 R/O result output 
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--  13 R/O result output 
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--  14 R/O result output 
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--  15 R/O result output Least Significant Byte
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--
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--  Copyright (C) 2008 - 2010 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                              Revision  History                            --
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--                                                                           --
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--===========================================================================--
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--
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-- Version  Author        Date         Description
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--
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-- 0.1      John Kent     2008-09-07   Initial version
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--
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-- 0.2      John Kent     2010-06-17   Header & GPL added
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--
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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library unisim;
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  use unisim.vcomponents.all;
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entity mul32 is
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        port (
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         clk       : in  std_logic;
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    rst       : in  std_logic;
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    cs        : in  std_logic;
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    rw        : in  std_logic;
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    addr      : in  std_logic_vector(3 downto 0);
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    dati      : in  std_logic_vector(7 downto 0);
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         dato      : out std_logic_vector(7 downto 0));
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end entity;
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architecture rtl of mul32 is
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--
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-- registers
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--
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signal mul_reg0 : std_logic_vector(7 downto 0);
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signal mul_reg1 : std_logic_vector(7 downto 0);
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signal mul_reg2 : std_logic_vector(7 downto 0);
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signal mul_reg3 : std_logic_vector(7 downto 0);
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signal mul_reg4 : std_logic_vector(7 downto 0);
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signal mul_reg5 : std_logic_vector(7 downto 0);
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signal mul_reg6 : std_logic_vector(7 downto 0);
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signal mul_reg7 : std_logic_vector(7 downto 0);
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signal mul_reg8 : std_logic_vector(7 downto 0);
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signal mul_reg9 : std_logic_vector(7 downto 0);
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signal mul_reg10 : std_logic_vector(7 downto 0);
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signal mul_reg11 : std_logic_vector(7 downto 0);
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signal mul_reg12 : std_logic_vector(7 downto 0);
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signal mul_reg13 : std_logic_vector(7 downto 0);
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signal mul_reg14 : std_logic_vector(7 downto 0);
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signal mul_reg15 : std_logic_vector(7 downto 0);
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begin
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---------------------------------
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--
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-- Write Multiplier Registers
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--
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---------------------------------
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mul_write : process( clk )
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begin
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  if clk'event and clk = '0' then
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    if rst = '1' then
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      mul_reg0  <= "00000000";
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      mul_reg1  <= "00000000";
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      mul_reg2  <= "00000000";
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      mul_reg3  <= "00000000";
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      mul_reg4  <= "00000000";
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      mul_reg5  <= "00000000";
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      mul_reg6  <= "00000000";
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      mul_reg7  <= "00000000";
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    else
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           if cs = '1' and rw = '0' then
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        case addr is
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             when "0000" =>
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                    mul_reg0 <= dati;
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             when "0001" =>
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                    mul_reg1 <= dati;
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             when "0010" =>
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                    mul_reg2 <= dati;
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             when "0011" =>
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                    mul_reg3 <= dati;
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             when "0100" =>
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                    mul_reg4 <= dati;
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             when "0101" =>
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                    mul_reg5 <= dati;
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             when "0110" =>
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                    mul_reg6 <= dati;
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             when "0111" =>
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                    mul_reg7 <= dati;
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        when others =>
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                    null;
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                  end case;
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           end if;
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         end if;
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  end if;
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end process;
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---------------------------------
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--
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-- Read Multiplier Registers
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--
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---------------------------------
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mul_read : process(  addr,
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                     mul_reg0, mul_reg1, mul_reg2, mul_reg3,
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                     mul_reg4, mul_reg5, mul_reg6, mul_reg7,
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                     mul_reg8, mul_reg9, mul_reg10, mul_reg11,
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                     mul_reg12, mul_reg13, mul_reg14, mul_reg15 )
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begin
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      case addr is
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             when "0000" =>
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                    dato <= mul_reg0;
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             when "0001" =>
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                    dato <= mul_reg1;
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             when "0010" =>
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                    dato <= mul_reg2;
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             when "0011" =>
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                    dato <= mul_reg3;
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             when "0100" =>
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                    dato <= mul_reg4;
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             when "0101" =>
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                    dato <= mul_reg5;
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             when "0110" =>
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                    dato <= mul_reg6;
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             when "0111" =>
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                    dato <= mul_reg7;
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             when "1000" =>
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                    dato <= mul_reg8;
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             when "1001" =>
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                    dato <= mul_reg9;
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             when "1010" =>
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                    dato <= mul_reg10;
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             when "1011" =>
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                    dato <= mul_reg11;
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             when "1100" =>
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                    dato <= mul_reg12;
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             when "1101" =>
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                    dato <= mul_reg13;
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             when "1110" =>
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                    dato <= mul_reg14;
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             when "1111" =>
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                    dato <= mul_reg15;
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        when others =>
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                    null;
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                end case;
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end process;
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---------------------------------
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--
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-- Perform 32 x 32 multiply
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--
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---------------------------------
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214 65 davidgb
my_mul32 : process(
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                     mul_reg0, mul_reg1, mul_reg2, mul_reg3,
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                     mul_reg4, mul_reg5, mul_reg6, mul_reg7
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                                                         )
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variable mul_left_hi  : std_logic_vector(17 downto 0);
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variable mul_left_lo  : std_logic_vector(17 downto 0);
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variable mul_right_hi : std_logic_vector(17 downto 0);
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variable mul_right_lo : std_logic_vector(17 downto 0);
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variable mul_out_0    : std_logic_vector(35 downto 0);
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variable mul_out_1    : std_logic_vector(35 downto 0);
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variable mul_out_2    : std_logic_vector(35 downto 0);
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variable mul_out_3    : std_logic_vector(35 downto 0);
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variable mul_out      : std_logic_vector(63 downto 0);
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begin
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  mul_left_hi  := "00" & mul_reg0 & mul_reg1;
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  mul_left_lo  := "00" & mul_reg2 & mul_reg3;
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  mul_right_hi := "00" & mul_reg4 & mul_reg5;
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  mul_right_lo := "00" &mul_reg6 & mul_reg7;
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  mul_out_0    := mul_left_hi * mul_right_hi;
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  mul_out_1    := mul_left_hi * mul_right_lo;
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  mul_out_2    := mul_left_lo * mul_right_hi;
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  mul_out_3    := mul_left_lo * mul_right_lo;
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  mul_out      := (mul_out_0( 31 downto 0) & "0000000000000000" & "0000000000000000") +
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                  ("0000000000000000" & mul_out_1( 31 downto 0) & "0000000000000000") +
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                  ("0000000000000000" & mul_out_2( 31 downto 0) & "0000000000000000") +
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                  ("0000000000000000" & "0000000000000000" & mul_out_3( 31 downto 0));
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  mul_reg8  <= mul_out(63 downto 56);
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  mul_reg9  <= mul_out(55 downto 48);
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  mul_reg10 <= mul_out(47 downto 40);
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  mul_reg11 <= mul_out(39 downto 32);
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  mul_reg12 <= mul_out(31 downto 24);
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  mul_reg13 <= mul_out(23 downto 16);
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  mul_reg14 <= mul_out(15 downto  8);
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  mul_reg15 <= mul_out( 7 downto  0);
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end process;
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end rtl;
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