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[/] [System09/] [trunk/] [rtl/] [VHDL/] [mulu32_s2.vhd] - Blame information for rev 209

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1 130 dilbert57
--===========================================================================--
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--                                                                           --
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--  umul32.vhd - Synthesizable 32 bit unsigned integer multiplier            --
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--               For FPGAs without hardware multiplier blocks                --
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--                                                                           --
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--===========================================================================--
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--
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--  File name      : mulu32_S2.vhd
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--
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--  Entity name    : umul32
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--
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--  Purpose        : Implements a 32 bit x 32 bit unsigned integer multiplier
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--                   Produces 64 bit result. 
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--                   Consists of 16 x 8 bit registers.
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--                   4 x 8bit read/write registers for 32 bit multiplicand.
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--                   4 x 8bit read/write registers for 32 bit multiplier.
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--                   8 x 8bit read only register for 64 bit result.
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--                   There is no control or status register.
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--                   Must wait 32 clock cycles for result after writing LSByte of multiplier
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--                   Designed for FPGAs which don't have hardware multiplier blocks 
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--                   such as Spartan 2/2E (which are no longer supported by current Xilinx software)
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--
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--  Dependencies   : ieee.std_logic_1164
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--                   ieee.std_logic_unsigned
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--                   unisim.vcomponents
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--
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--  Author         : John E. Kent
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--
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--  Email          : dilbert57@opencores.org      
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--
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--  Web            : http://opencores.org/project,system09
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--
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--  Registers      :
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-- 
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--   0 R/W multiplicand input  Most Significant Byte
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--   1 R/W multiplicand input
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--   2 R/W multiplicand input
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--   3 R/W multiplicand input  Least Significant Byte
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--   4 R/W multiplier   input  Most Significant Byte
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--   5 R/W multiplier   input
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--   6 R/W multiplier   input
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--   7 R/W multiplier   input  Least Significant Byte
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--   8 R/O result       output Most Significant Byte
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--   9 R/O result       output 
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--  10 R/O result       output 
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--  11 R/O result       output 
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--  12 R/O result       output 
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--  13 R/O result       output 
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--  14 R/O result       output 
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--  15 R/O result       output Least Significant Byte
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--
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--  Copyright (C) 2010 - 2012 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                              Revision  History                            --
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--                                                                           --
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--===========================================================================--
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--
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-- Version  Author        Date         Description
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--
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-- 0.1      John Kent     2008-09-07   Initial version
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-- 0.2      John Kent     2010-06-17   Header & GPL added
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-- 0.3      John Kent     2012-04-06   converted into umul32
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-- 0.4      John Kent     2016-02-04   Version without hardware multiply
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--
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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--library unisim;
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--  use unisim.vcomponents.all;
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entity umul32 is
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        port (
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         clk       : in  std_logic;
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    rst       : in  std_logic;
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    cs        : in  std_logic;
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    rw        : in  std_logic;
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    addr      : in  std_logic_vector(3 downto 0);
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    data_in   : in  std_logic_vector(7 downto 0);
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         data_out  : out std_logic_vector(7 downto 0);
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         hold      : out std_logic
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         );
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end entity;
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architecture rtl of umul32 is
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--
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-- registers
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--
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signal multiplicand : std_logic_vector(31 downto 0) := (others=>'0');
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signal multiplier   : std_logic_vector(31 downto 0) := (others=>'0');
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signal result       : std_logic_vector(64 downto 0) := (others=>'0');
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signal multiplier_temp  : std_logic_vector(31 downto 0) := (others=>'0');
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signal count        : std_logic_vector(4 downto 0); -- bit counter
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signal req_flag     : std_logic := '0';
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signal act_flag     : std_logic := '0';
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begin
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---------------------------------
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--
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-- Write Multiplier Registers
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--
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---------------------------------
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umul32_write : process( clk, rst, cs, rw, addr, data_in, act_flag, req_flag )
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begin
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  if rst = '1' then
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    multiplicand <= (others => '0');
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    multiplier   <= (others => '0');
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    req_flag   <= '0';
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  elsif falling_edge( clk ) then
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    if (cs = '1') and (rw = '0') then
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      case addr is
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           when "0000" =>
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                  multiplicand(31 downto 24) <= data_in;
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           when "0001" =>
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                  multiplicand(23 downto 16) <= data_in;
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           when "0010" =>
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                  multiplicand(15 downto  8) <= data_in;
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           when "0011" =>
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                  multiplicand( 7 downto  0) <= data_in;
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           when "0100" =>
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                  multiplier(31 downto 24) <= data_in;
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           when "0101" =>
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                  multiplier(23 downto 16) <= data_in;
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           when "0110" =>
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                  multiplier(15 downto  8) <= data_in;
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           when "0111" =>
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        multiplier( 7 downto  0) <= data_in;
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                  if (act_flag = '0') and (req_flag <= '0') then
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                    req_flag <= '1';
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                  end if;
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      when others =>
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        null;
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                end case;
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         end if; -- cs
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         if (act_flag = '1') and (req_flag = '1') then
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           req_flag <= '0';
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    end if;
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    hold <= cs and rw and addr(3) and act_flag;
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  end if; -- rst/clk
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end process;
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---------------------------------
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--
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-- Read Multiplier Registers
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--
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---------------------------------
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umul32_read : process( addr, multiplicand, multiplier, result )
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begin
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  case addr is
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  when "0000" =>
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         data_out <= multiplicand(31 downto 24);
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  when "0001" =>
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    data_out <= multiplicand(23 downto 16);
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  when "0010" =>
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    data_out <= multiplicand(15 downto  8);
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  when "0011" =>
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    data_out <= multiplicand( 7 downto  0);
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  when "0100" =>
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    data_out <= multiplier(31 downto 24);
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  when "0101" =>
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    data_out <= multiplier(23 downto 16);
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  when "0110" =>
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    data_out <= multiplier(15 downto  8);
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  when "0111" =>
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    data_out <= multiplier( 7 downto  0);
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  when "1000" =>
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    data_out <= result(63 downto 56);
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  when "1001" =>
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    data_out <= result(55 downto 48);
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  when "1010" =>
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    data_out <= result(47 downto 40);
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  when "1011" =>
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    data_out <= result(39 downto 32);
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  when "1100" =>
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    data_out <= result(31 downto 24);
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  when "1101" =>
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    data_out <= result(23 downto 16);
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  when "1110" =>
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    data_out <= result(15 downto  8);
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  when "1111" =>
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    data_out <= result( 7 downto  0);
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  when others =>
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    null;
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  end case;
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end process;
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---------------------------------
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--
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-- Perform 32 x 32 multiply
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--
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---------------------------------
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--
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-- When the active flag is clear and the request flag goes high, 
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-- start the multiplication by setting the active flag
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-- When the active flag is high and the count reaches 31
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-- reset the active flag
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-- 
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umul32_multiply : process( rst, clk, req_flag, act_flag )
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variable result_temp : std_logic_vector(32 downto 0);
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begin
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  if (rst = '1') then
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    multiplier_temp <= (others=>'0');
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    result          <= (others=>'0');
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    count           <= (others=>'0');
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    act_flag        <= '0';             -- default state is inactive
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  elsif falling_edge( clk ) then
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      --
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      -- start the division if the last division was complete
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                -- i.e. the active flag was clear
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      -- and the last byte of the divisor was just written
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      -- i.e. the request flag was pulsed high for one clock cycle
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                --
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      if (req_flag = '1') and (act_flag = '0') then
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        multiplier_temp <= multiplier;       -- Get Multiplier into temp
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        result          <= (others => '0');  -- Clear the result
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        count           <= (others => '0');  -- Zero the bit counter
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        act_flag        <= '1';              -- Flag multiplication in progress
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      elsif ( req_flag = '0' ) and (act_flag = '1') then  -- if active flag is set the multiplication must be in progress
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        result_temp(32 downto 0) := "0" & result(63 downto 32);
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        if multiplier_temp(0) = '1' then                            -- if least significant bit of multiplier is set
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          result_temp(32 downto 0) := ("0" & result(63 downto 32)) + ("0" & multiplicand);    -- add the multiplicand to the msbits of the result
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        end if;
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        --
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        -- shift the result down one bit
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        --
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                  result(30 downto  0) <= result(31 downto 1);
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        result(63 downto 31) <= result_temp(32 downto 0);
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                  --
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        -- shift multiplier temp down one bit
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        --
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        multiplier_temp(30 downto 0) <= multiplier_temp(31 downto 1);
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                  multiplier_temp(31) <= '0';
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        --
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        -- 32 bit multiplication should take 32 clock cycles
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        --
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        count               <= count + "00001";
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        --
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                  -- When the count reaches the 31st cycle of the division 
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        -- flag that the multiplication is complete by setting the finish flag.
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        -- 
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        if count = "11111" then
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          act_flag <= '0';  -- flag Multiplication complete
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        end if;
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      end if; -- start/finish
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  end if; -- rst/clk
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end process;
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end rtl;
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