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[/] [System09/] [trunk/] [rtl/] [VHDL/] [peripheral_bus.vhd] - Blame information for rev 102

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1 100 davidgb
--===========================================================================--
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--                                                                           --
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--                       Peripheral Bus Interface                            --
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--                                                                           --
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--===========================================================================--
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--
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--  File name      : peripheral_bus.vhd
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--
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--  Entity name    : peripheral_bus
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--
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--  Purpose        : Implements a 16 bit peripheral bus interface 
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--                   On the XESS XST-3.0 carrier board it is shared 
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--                   by an IDE interface, and Ethernet MAC
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--                   and two 16 bit expansion slots.
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--                   The same bus structure is used on the 
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--                   BurchED B3 and B5-X300 Spartan 2 boards
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--                   to implement an IDE Compact Flash interface.
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--
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--                   The 16 bit data bus is accessed by two
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--                   consecutive byte wide read or write cycles.
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--
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--                   On an even byte read a read strobe is generated
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--                   on the peripheral bus and the high bits of the
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--                   peripheral data bus are output to the CPU
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--                   data bus and the lower 8 bits latched.
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--                   A bus hold cycle is generated to allow time
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--                   for the peripheral data bus to settle.
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--                   On the odd byte read, the latched lower data 
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--                   bits of the peripheral bus are output on the
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--                   CPU data bus.
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--
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--                   Conversely, on an even byte write the CPU data
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--                   bus value is latched. On the odd byte write, the
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--                   latched value is output to the high 8 bits of
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--                   the peripheral bus, and the CPU data is output
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--                   to the lower 8 bits of the peripheral bus and
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--                   a peripheral write strobe is generated.
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--                   A hold signal is geneated back to the CPU to
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--                   allow the peripheral bus to settle.
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--                  
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--  Dependencies   : ieee.std_logic_1164
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--                   ieee.numeric_std
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--                   unisim.vcomponents
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--
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--  Author         : John E. Kent
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--
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--  Email          : dilbert57@opencores.org      
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--
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--  Web            : http://opencores.org/project,system09
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--
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--  Memory Map     :
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--
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--  IO address + $00 IDE Compact Flash interface
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--  IO address + $40 Ethernet MAC interface (XESS XST-3.0)
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--  IO address + $80 Expansion Slot 0       (XESS XST-3.0)
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--  IO address + $C0 Expansion Slot 1       (XESS XST-3.0)
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--
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--
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--  Copyright (C) 2010 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                              Revision  History                            --
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--                                                                           --
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--===========================================================================--
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--
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-- Version Author       Date         Changes
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--
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-- 0.1     John Kent    2010-08-28   New model
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--
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.numeric_std.all;
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  use ieee.std_logic_unsigned.all;
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library unisim;
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  use unisim.vcomponents.all;
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-----------------------------------------------------------------------
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--                 Entity for peripheral bus                         --
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-----------------------------------------------------------------------
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entity peripheral_bus is
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  port (
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    --
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    -- CPU Interface signals
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    --
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    clk      : in  std_logic;                     -- System Clock
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    rst      : in  std_logic;                     -- Reset input (active high)
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    cs       : in  std_logic;                     -- Peripheral Bus Chip Select
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    addr     : in  std_logic_vector(7 downto 0);  -- Register Select
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    rw       : in  std_logic;                     -- Read / Not Write
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    data_in  : in  std_logic_vector(7 downto 0);  -- Data Bus In 
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    data_out : out std_logic_vector(7 downto 0);  -- Data Bus Out
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    hold     : out std_logic;                     -- Hold bus cycle output
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    --
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    -- Peripheral Bus Interface Signals
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    -- IO + ($00 - $FF) 
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    -- (for compatibility with XSA-3S1000 / XST 3.0)
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    --
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    pb_rd_n  : out   std_logic; -- ide pin 25
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    pb_wr_n  : out   std_logic; -- ide pin 23
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    pb_addr  : out   std_logic_vector( 4 downto 0);
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    pb_data  : inout std_logic_vector(15 downto 0);
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    -- Peripheral chip selects on Peripheral Bus 
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    ide_cs   : out  std_logic;  -- IDE / CF interface ($00 - $3F)
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    eth_cs   : out  std_logic;  -- Ethernet interface ($40 - $7F)
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    sl1_cs   : out  std_logic;  -- Expansion slot 1   ($80 - $BF)
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    sl2_cs   : out  std_logic   -- Expansion slot 2   ($C0 - $FF)
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    );
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end peripheral_bus;
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--================== End of entity ==============================--
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-------------------------------------------------------------------------------
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-- Architecture for peripheral bus interface
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-------------------------------------------------------------------------------
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architecture rtl of peripheral_bus is
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  type hold_state_type is ( hold_release_state, hold_request_state );
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  signal pb_hold_state : hold_state_type := hold_release_state;
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  signal pb_wru        : std_logic;       -- upper byte write strobe
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  signal pb_wrl        : std_logic;       -- lower byte write strobe
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  signal pb_rdu        : std_logic;       -- upper byte read strobe
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  signal pb_rdl        : std_logic;       -- lower byte read strobe
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  signal pb_hold       : std_logic := '0';         -- hold peripheral bus access
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  signal pb_count      : std_logic_vector(3 downto 0) := (others=>'0'); -- hold counter
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  signal pb_wreg       : std_logic_vector(7 downto 0) := (others=>'0'); -- lower byte write register
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  signal pb_rreg       : std_logic_vector(7 downto 0) := (others=>'0'); -- lower byte read register
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begin
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peripheral_bus_decode : process( addr, cs )
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begin
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  ide_cs <= '0';
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  eth_cs <= '0';
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  sl1_cs <= '0';
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  sl2_cs <= '0';
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  case addr(7 downto 6) is
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  --
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  -- IDE Interface $E100 to $E13F
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  --
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  when "00" =>
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    ide_cs <= cs;
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  --
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  -- Ethernet Interface $E140 to $E17F
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  --
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  when "01" =>
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    eth_cs <= cs;
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  --
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  -- Slot 1 Interface $E180 to $E1BF
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  --
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  when "10" =>
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    sl1_cs <= cs;
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  --
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  -- Slot 2 Interface $E1C0 to $E1FF
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  --
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  when "11" =>
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    sl2_cs <= cs;
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  --
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  -- Nothing else
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  --
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  when others =>
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    null;
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  end case;
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end process;
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--
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-- 16-bit Peripheral Bus
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-- 6809 Big endian
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-- ISA bus little endian
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-- Not sure about IDE interface
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--
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peripheral_bus_control: process( clk, rst, cs, addr, rw, data_in,
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                                 pb_hold, pb_wreg, pb_rreg,
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                                 pb_wru, pb_wrl, pb_rdu, pb_rdl, pb_data )
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begin
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   pb_addr <= addr(5 downto 1);
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   --
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   -- internal read/write strobes
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   --
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   pb_wru  <= cs and (not rw) and (not addr(0));
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   pb_wrl  <= cs and (not rw) and      addr(0) ;
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   pb_rdu  <= cs and      rw  and (not addr(0));
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   pb_rdl  <= cs and      rw  and      addr(0) ;
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   pb_wr_n  <= not pb_wrl;
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   pb_rd_n  <= not pb_rdu;
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   --
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   -- The peripheral bus will be an output 
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   -- the registered even byte on data(15 downto 8)
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   -- and the CPU odd bytes on data(7 downto 0)
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   -- on odd byte writes
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   --
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   if pb_wrl = '1' then
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     pb_data <= pb_wreg & data_in;
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   else
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     pb_data <= (others => 'Z');
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   end if;
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   --
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   -- On even byte reads,
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   -- the CPU reads the low (even) byte of the peripheral bus
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   -- On odd byte reads,
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   -- the CPU reads the registered (odd byte) input from the peripheral bus
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   --
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   if pb_rdu = '1' then
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      data_out <= pb_data(15 downto 8);
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   elsif pb_rdl = '1' then
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      data_out <= pb_rreg;
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   else
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      data_out <= (others => '0');
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   end if;
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   --
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   -- Register upper byte from CPU on first CPU write
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   -- and lower byte from the peripheral bus on first CPU read
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   --
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   if falling_edge(clk) then
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     if rst = '1' then
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       pb_wreg   <= (others => '0');
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       pb_rreg   <= (others => '0');
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     else
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       if pb_wru = '1' then
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         pb_wreg <= data_in;
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       end if;
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       if pb_rdu = '1' then
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         pb_rreg <= pb_data(7 downto 0);
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       end if;
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     end if;
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   end if;
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end process;
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--
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-- Hold Peripheral bus accesses for a few cycles
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--
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peripheral_bus_hold: process( clk, rst, cs,
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                              pb_hold_state, pb_hold,
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                              pb_rdu, pb_wrl )
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begin
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  if rising_edge( clk ) then
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    if rst = '1' then
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                 pb_hold       <= '0';
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                 pb_count      <= "0000";
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            pb_hold_state <= hold_release_state;
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         else
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      --
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      -- The perpheral bus hold signal should be generated on 
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      -- 16 bit bus even upper byte read or 
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      -- 16 bit bus odd lower byte write.
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      -- 
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      case pb_hold_state is
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                when hold_release_state =>
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                  if (pb_rdu = '1') or (pb_wrl = '1') then
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          pb_count      <= "0011";
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          pb_hold       <= '1';
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          pb_hold_state <= hold_request_state;
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        else
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          pb_hold       <= '0';
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          pb_hold_state <= hold_release_state;
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        end if;
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                 when hold_request_state =>
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         if pb_count = "0000" then
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           pb_hold       <= '0';
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           pb_hold_state <= hold_release_state;
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         else
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                     pb_count <= pb_count - "0001";
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                        end if;
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295
       when others =>
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                    null;
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298
       end case;
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         end if;
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  end if;
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  hold <= cs and pb_hold;
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end process;
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end rtl;

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