OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [VHDL/] [peripheral_bus.vhd] - Blame information for rev 209

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 100 davidgb
--===========================================================================--
2
--                                                                           --
3
--                       Peripheral Bus Interface                            --
4
--                                                                           --
5
--===========================================================================--
6
--
7
--  File name      : peripheral_bus.vhd
8
--
9
--  Entity name    : peripheral_bus
10
--
11
--  Purpose        : Implements a 16 bit peripheral bus interface 
12
--                   On the XESS XST-3.0 carrier board it is shared 
13
--                   by an IDE interface, and Ethernet MAC
14
--                   and two 16 bit expansion slots.
15
--                   The same bus structure is used on the 
16
--                   BurchED B3 and B5-X300 Spartan 2 boards
17
--                   to implement an IDE Compact Flash interface.
18
--
19
--                   The 16 bit data bus is accessed by two
20
--                   consecutive byte wide read or write cycles.
21
--
22
--                   On an even byte read a read strobe is generated
23
--                   on the peripheral bus and the high bits of the
24
--                   peripheral data bus are output to the CPU
25
--                   data bus and the lower 8 bits latched.
26
--                   A bus hold cycle is generated to allow time
27
--                   for the peripheral data bus to settle.
28
--                   On the odd byte read, the latched lower data 
29
--                   bits of the peripheral bus are output on the
30
--                   CPU data bus.
31
--
32
--                   Conversely, on an even byte write the CPU data
33
--                   bus value is latched. On the odd byte write, the
34
--                   latched value is output to the high 8 bits of
35
--                   the peripheral bus, and the CPU data is output
36
--                   to the lower 8 bits of the peripheral bus and
37
--                   a peripheral write strobe is generated.
38
--                   A hold signal is geneated back to the CPU to
39
--                   allow the peripheral bus to settle.
40
--                  
41
--  Dependencies   : ieee.std_logic_1164
42
--                   ieee.numeric_std
43
--                   unisim.vcomponents
44
--
45
--  Author         : John E. Kent
46
--
47
--  Email          : dilbert57@opencores.org      
48
--
49
--  Web            : http://opencores.org/project,system09
50
--
51
--  Memory Map     :
52
--
53
--  IO address + $00 IDE Compact Flash interface
54
--  IO address + $40 Ethernet MAC interface (XESS XST-3.0)
55
--  IO address + $80 Expansion Slot 0       (XESS XST-3.0)
56
--  IO address + $C0 Expansion Slot 1       (XESS XST-3.0)
57
--
58
--
59
--  Copyright (C) 2010 John Kent
60
--
61
--  This program is free software: you can redistribute it and/or modify
62
--  it under the terms of the GNU General Public License as published by
63
--  the Free Software Foundation, either version 3 of the License, or
64
--  (at your option) any later version.
65
--
66
--  This program is distributed in the hope that it will be useful,
67
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
68
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
69
--  GNU General Public License for more details.
70
--
71
--  You should have received a copy of the GNU General Public License
72
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
73
--
74
--===========================================================================--
75
--                                                                           --
76
--                              Revision  History                            --
77
--                                                                           --
78
--===========================================================================--
79
--
80
-- Version Author       Date         Changes
81
--
82
-- 0.1     John Kent    2010-08-28   New model
83
--
84
 
85
library ieee;
86
  use ieee.std_logic_1164.all;
87
  use ieee.numeric_std.all;
88
  use ieee.std_logic_unsigned.all;
89 118 dilbert57
--library unisim;
90
--  use unisim.vcomponents.all;
91 100 davidgb
 
92
-----------------------------------------------------------------------
93
--                 Entity for peripheral bus                         --
94
-----------------------------------------------------------------------
95
 
96
entity peripheral_bus is
97
  port (
98
    --
99
    -- CPU Interface signals
100
    --
101
    clk      : in  std_logic;                     -- System Clock
102
    rst      : in  std_logic;                     -- Reset input (active high)
103
    cs       : in  std_logic;                     -- Peripheral Bus Chip Select
104
    addr     : in  std_logic_vector(7 downto 0);  -- Register Select
105
    rw       : in  std_logic;                     -- Read / Not Write
106
    data_in  : in  std_logic_vector(7 downto 0);  -- Data Bus In 
107
    data_out : out std_logic_vector(7 downto 0);  -- Data Bus Out
108
    hold     : out std_logic;                     -- Hold bus cycle output
109
    --
110
    -- Peripheral Bus Interface Signals
111
    -- IO + ($00 - $FF) 
112
    -- (for compatibility with XSA-3S1000 / XST 3.0)
113
    --
114
    pb_rd_n  : out   std_logic; -- ide pin 25
115
    pb_wr_n  : out   std_logic; -- ide pin 23
116
    pb_addr  : out   std_logic_vector( 4 downto 0);
117
    pb_data  : inout std_logic_vector(15 downto 0);
118
 
119
    -- Peripheral chip selects on Peripheral Bus 
120
    ide_cs   : out  std_logic;  -- IDE / CF interface ($00 - $3F)
121
    eth_cs   : out  std_logic;  -- Ethernet interface ($40 - $7F)
122
    sl1_cs   : out  std_logic;  -- Expansion slot 1   ($80 - $BF)
123
    sl2_cs   : out  std_logic   -- Expansion slot 2   ($C0 - $FF)
124
    );
125
end peripheral_bus;
126
--================== End of entity ==============================--
127
 
128
-------------------------------------------------------------------------------
129
-- Architecture for peripheral bus interface
130
-------------------------------------------------------------------------------
131
 
132
architecture rtl of peripheral_bus is
133
 
134
 
135
  type hold_state_type is ( hold_release_state, hold_request_state );
136
  signal pb_hold_state : hold_state_type := hold_release_state;
137
  signal pb_wru        : std_logic;       -- upper byte write strobe
138
  signal pb_wrl        : std_logic;       -- lower byte write strobe
139
  signal pb_rdu        : std_logic;       -- upper byte read strobe
140
  signal pb_rdl        : std_logic;       -- lower byte read strobe
141
  signal pb_hold       : std_logic := '0';         -- hold peripheral bus access
142
  signal pb_count      : std_logic_vector(3 downto 0) := (others=>'0'); -- hold counter
143
  signal pb_wreg       : std_logic_vector(7 downto 0) := (others=>'0'); -- lower byte write register
144
  signal pb_rreg       : std_logic_vector(7 downto 0) := (others=>'0'); -- lower byte read register
145
 
146
begin
147
 
148
peripheral_bus_decode : process( addr, cs )
149
begin
150
 
151
  ide_cs <= '0';
152
  eth_cs <= '0';
153
  sl1_cs <= '0';
154
  sl2_cs <= '0';
155
 
156
  case addr(7 downto 6) is
157
  --
158
  -- IDE Interface $E100 to $E13F
159
  --
160
  when "00" =>
161
    ide_cs <= cs;
162
  --
163
  -- Ethernet Interface $E140 to $E17F
164
  --
165
  when "01" =>
166
    eth_cs <= cs;
167
  --
168
  -- Slot 1 Interface $E180 to $E1BF
169
  --
170
  when "10" =>
171
    sl1_cs <= cs;
172
  --
173
  -- Slot 2 Interface $E1C0 to $E1FF
174
  --
175
  when "11" =>
176
    sl2_cs <= cs;
177
  --
178
  -- Nothing else
179
  --
180
  when others =>
181
    null;
182
  end case;
183
 
184
end process;
185
 
186
--
187
-- 16-bit Peripheral Bus
188
-- 6809 Big endian
189
-- ISA bus little endian
190
-- Not sure about IDE interface
191
--
192
peripheral_bus_control: process( clk, rst, cs, addr, rw, data_in,
193
                                 pb_hold, pb_wreg, pb_rreg,
194
                                 pb_wru, pb_wrl, pb_rdu, pb_rdl, pb_data )
195
begin
196
   pb_addr <= addr(5 downto 1);
197
   --
198
   -- internal read/write strobes
199
   --
200
   pb_wru  <= cs and (not rw) and (not addr(0));
201
   pb_wrl  <= cs and (not rw) and      addr(0) ;
202
   pb_rdu  <= cs and      rw  and (not addr(0));
203
   pb_rdl  <= cs and      rw  and      addr(0) ;
204
 
205
   pb_wr_n  <= not pb_wrl;
206
   pb_rd_n  <= not pb_rdu;
207
 
208
   --
209
   -- The peripheral bus will be an output 
210
   -- the registered even byte on data(15 downto 8)
211
   -- and the CPU odd bytes on data(7 downto 0)
212
   -- on odd byte writes
213
   --
214
   if pb_wrl = '1' then
215
     pb_data <= pb_wreg & data_in;
216
   else
217
     pb_data <= (others => 'Z');
218
   end if;
219
 
220
   --
221
   -- On even byte reads,
222
   -- the CPU reads the low (even) byte of the peripheral bus
223
   -- On odd byte reads,
224
   -- the CPU reads the registered (odd byte) input from the peripheral bus
225
   --
226
   if pb_rdu = '1' then
227
      data_out <= pb_data(15 downto 8);
228
   elsif pb_rdl = '1' then
229
      data_out <= pb_rreg;
230
   else
231
      data_out <= (others => '0');
232
   end if;
233
 
234
   --
235
   -- Register upper byte from CPU on first CPU write
236
   -- and lower byte from the peripheral bus on first CPU read
237
   --
238
   if falling_edge(clk) then
239
     if rst = '1' then
240
       pb_wreg   <= (others => '0');
241
       pb_rreg   <= (others => '0');
242
     else
243
 
244
       if pb_wru = '1' then
245
         pb_wreg <= data_in;
246
       end if;
247
 
248
       if pb_rdu = '1' then
249
         pb_rreg <= pb_data(7 downto 0);
250
       end if;
251
 
252
     end if;
253
   end if;
254
 
255
end process;
256
 
257
--
258
-- Hold Peripheral bus accesses for a few cycles
259
--
260
peripheral_bus_hold: process( clk, rst, cs,
261
                              pb_hold_state, pb_hold,
262
                              pb_rdu, pb_wrl )
263
begin
264
  if rising_edge( clk ) then
265
    if rst = '1' then
266
                 pb_hold       <= '0';
267
                 pb_count      <= "0000";
268
            pb_hold_state <= hold_release_state;
269
         else
270
      --
271
      -- The perpheral bus hold signal should be generated on 
272
      -- 16 bit bus even upper byte read or 
273
      -- 16 bit bus odd lower byte write.
274
      -- 
275
      case pb_hold_state is
276
 
277
                when hold_release_state =>
278
                  if (pb_rdu = '1') or (pb_wrl = '1') then
279
          pb_count      <= "0011";
280
          pb_hold       <= '1';
281
          pb_hold_state <= hold_request_state;
282
        else
283
          pb_hold       <= '0';
284
          pb_hold_state <= hold_release_state;
285
        end if;
286
 
287
                 when hold_request_state =>
288
         if pb_count = "0000" then
289
           pb_hold       <= '0';
290
           pb_hold_state <= hold_release_state;
291
         else
292
                     pb_count <= pb_count - "0001";
293
                        end if;
294
 
295
       when others =>
296
                    null;
297
 
298
       end case;
299
         end if;
300
  end if;
301
  hold <= cs and pb_hold;
302
end process;
303
 
304
end rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.