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[/] [System09/] [trunk/] [rtl/] [VHDL/] [timer.vhd] - Blame information for rev 209

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Line No. Rev Author Line
1 99 davidgb
--===========================================================================--
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--                                                                           --
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--                  Synthesizable 8 bit Timer                                --
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--                                                                           --
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--===========================================================================--
6 19 dilbert57
--
7 99 davidgb
--  File name      : timer.vhd
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--
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--  Entity name    : timer
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--
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--  Purpose        : 8 bit timer module for System09
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--
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--  Dependencies   : ieee.std_logic_1164
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--                   ieee.std_logic_unsigned
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--
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--  Uses           : None
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--
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--  Author         : John E. Kent      
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--
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--  Email          : dilbert57@opencores.org      
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--
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--  Web            : http://opencores.org/project,system09
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--
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--  Registers      :
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--
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--  IO address + 0 Read - Down Count register
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--        Bits[7..0] = Counter Value
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--
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--  IO address + 0 Write - Preset Count register
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--        Bits[7..0] = Preset Value
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--
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--  IO address + 1 Read - Status register
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--        Bit[7]     = Interrupt Flag
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--        Bits[6..0] = undefined
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--
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--  IO address + 1 Write - Control register
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--        Bit[7]     = Interrupt Enable
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--        Bits[6..1] = Unedfined
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--        Bit[0]     = Counter enable
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--
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--  Operation       :
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--
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--        Write count to counter register
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--        Enable counter by setting bit 0 of the control register
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--        Enable interrupts by setting bit 7 of the control register
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--        Counter will count down to zero
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--        When it reaches zero the terminal flag is set
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--        If the interrupt is enabled an interrupt is generated
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--        The interrupt may be disabled by writing a 0 to bit 7 
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--        of the control register or by loading a new down count 
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--        into the counter register.
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--
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--  Copyright (C) 2002 - 2010 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                              Revision  History                            --
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--                                                                           --
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--===========================================================================--
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--
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-- Version Date        Author     Changes
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--
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-- 0.1     2002-09-06  John Kent  Converted to a single timer 
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--                                Made synchronous with system clock
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-- 1.0     2003-09-06  John Kent  Changed Clock Edge
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--                                Released to opencores.org
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-- 2.0     2008-02-05  John Kent  Removed Timer inputs and outputs
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--                                Made into a simple 8 bit interrupt down counter
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-- 2.1     2010-06-17  John Kent  Updated header and added GPL
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--
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-- 
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity timer is
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        port (
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         clk        : in  std_logic;
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    rst        : in  std_logic;
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    cs         : in  std_logic;
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    addr       : in  std_logic;
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    rw         : in  std_logic;
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    data_in    : in  std_logic_vector(7 downto 0);
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         data_out   : out std_logic_vector(7 downto 0);
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         irq        : out std_logic
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  );
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end;
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architecture rtl of timer is
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signal timer_ctrl  : std_logic_vector(7 downto 0);
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signal timer_stat  : std_logic_vector(7 downto 0);
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signal timer_count : std_logic_vector(7 downto 0);
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signal timer_term  : std_logic; -- Timer terminal count
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--
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-- control/status register bits
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--
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constant BIT_ENB   : integer := 0; -- 0=disable, 1=enabled
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constant BIT_IRQ   : integer := 7; -- 0=disabled, 1-enabled
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begin
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  --------------------------------
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  --
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  -- write control registers
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  --
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  --------------------------------
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  timer_control : process( clk, rst, cs, rw, addr, data_in,
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                         timer_ctrl, timer_term, timer_count )
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  begin
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    if clk'event and clk = '0' then
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      if rst = '1' then
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             timer_count <= (others=>'0');
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                  timer_ctrl  <= (others=>'0');
127 22 dilbert57
                  timer_term  <= '0';
128 99 davidgb
      elsif cs = '1' and rw = '0' then
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             if addr='0' then
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                    timer_count <= data_in;
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                    timer_term  <= '0';
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             else
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                    timer_ctrl <= data_in;
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                  end if;
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           else
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             if (timer_ctrl(BIT_ENB) = '1') then
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                    if (timer_count = "00000000" ) then
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                      timer_term <= '1';
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          else
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            timer_count <= timer_count - 1;
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                    end if;
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                  end if;
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      end if;
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    end if;
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  end process;
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  --
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  -- timer status register
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  --
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  timer_status : process( timer_ctrl, timer_term )
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  begin
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    timer_stat(6 downto 0) <= timer_ctrl(6 downto 0);
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    timer_stat(BIT_IRQ) <= timer_term;
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  end process;
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  --
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  -- timer data output mux
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  --
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  timer_data_out : process( addr, timer_count, timer_stat )
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  begin
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    if addr = '0' then
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      data_out <= timer_count;
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    else
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      data_out <= timer_stat;
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    end if;
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  end process;
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  --
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  -- read timer strobe to reset interrupts
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  --
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  timer_interrupt : process( timer_term, timer_ctrl )
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  begin
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         irq <= timer_term and timer_ctrl(BIT_IRQ);
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  end process;
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176 19 dilbert57
end rtl;
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