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[/] [System09/] [trunk/] [rtl/] [VHDL/] [trace.vhd] - Blame information for rev 19

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1 19 dilbert57
--===========================================================================--
2
--
3
--  S Y N T H E Z I A B L E    Real Time Trace   C O R E
4
--
5
--  www.OpenCores.Org - May 2003
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : trace.vhd
9
--
10
-- entity name    : trace
11
--
12
-- Purpose        : Implements a trace buffer
13
--
14
-- Dependencies   : ieee.Std_Logic_1164
15
--                  ieee.std_logic_unsigned
16
--
17
-- Author         : John E. Kent      
18
--
19
--===========================================================================----
20
--
21
-- Revision History:
22
--
23
-- Date:          Revision         Author
24
-- 19 June 2004     0.1              John Kent
25
--
26
--===========================================================================----
27
--
28
-- Register Memory Map
29
--
30
-- $00 - Address Comparitor High Byte
31
-- $01 - Address Comparitor Low byte
32
-- $02 - Data    Comparitor
33
-- $03 - Control Comparitor
34
-- $04 - Address Qualifier High Byte
35
-- $05 - Address Qualifier Low byte
36
-- $06 - Data    Qualifier
37
-- $07 - Control Qualifier
38
--
39
-- Address, Data and Control signals must match in the Comparitor registers 
40
-- Matches are qualified by setting a bit in the Qualifier registers
41
--
42
-- Control Comparitor / Qualify (write)
43
-- b0 - r/w        1=read   0=write
44
-- b1 - vma        1=valid  0=invalid
45
-- b5 - trace      1=enable 0=disable
46
-- b6 - pre/post   1=before 0=after
47
-- b7 - irq output 1=match  0=mismatch
48
--
49
-- Control Qualifier Read
50
-- b7 - match flag
51
--
52
library ieee;
53
use ieee.std_logic_1164.all;
54
use ieee.std_logic_unsigned.all;
55
 
56
entity trace is
57
        port (
58
         clk           : in  std_logic;
59
    rst           : in  std_logic;
60
    rs            : in  std_logic;        -- register select
61
    bs            : in  std_logic;        -- bank select
62
    rw            : in  std_logic;
63
         vma           : in  std_logic;
64
    addr          : in  std_logic_vector(15 downto 0);
65
    data_in       : in  std_logic_vector(7 downto 0);
66
         reg_data_out  : out std_logic_vector(7 downto 0);
67
         buff_data_out : out std_logic_vector(7 downto 0);
68
    cpu_data_in   : in  std_logic_vector(7 downto 0);
69
         irq           : out std_logic
70
  );
71
end;
72
 
73
architecture trace_arch of trace is
74
 
75
signal clk_n      : std_logic;
76
signal irq_out    : std_logic;
77
signal qual_write : std_logic;
78
signal qual_read  : std_logic;
79
--
80
-- bank select
81
--
82
signal bank_reg : std_logic_vector(7 downto 0);
83
 
84
--
85
-- Trigger registers
86
--
87
signal comp_addr_hi : std_logic_vector(7 downto 0);
88
signal comp_addr_lo : std_logic_vector(7 downto 0);
89
signal qual_addr_hi : std_logic_vector(7 downto 0);
90
signal qual_addr_lo : std_logic_vector(7 downto 0);
91
signal comp_data    : std_logic_vector(7 downto 0);
92
signal qual_data    : std_logic_vector(7 downto 0);
93
signal comp_ctrl    : std_logic_vector(7 downto 0);
94
signal qual_ctrl    : std_logic_vector(7 downto 0);
95
signal match_flag   : std_logic;
96
 
97
--
98
-- Trace counter
99
--
100
signal trace_clk        : std_logic;
101
signal trace_rst        : std_logic;
102
signal trace_stb        : std_logic;
103
signal trace_we         : std_logic;
104
signal trace_count      : std_logic_vector(9 downto 0);
105
signal trace_offset     : std_logic_vector(9 downto 0);
106
 
107
signal trace_data_out_0 : std_logic_vector(7 downto 0);
108
signal trace_data_out_1 : std_logic_vector(7 downto 0);
109
signal trace_data_out_2 : std_logic_vector(7 downto 0);
110
signal trace_data_out_3 : std_logic_vector(7 downto 0);
111
signal trace_data_out_4 : std_logic_vector(7 downto 0);
112
signal trace_data_out_5 : std_logic_vector(7 downto 0);
113
 
114
signal buff_stb         : std_logic_vector(5 downto 0);
115
signal buff_we          : std_logic;
116
signal buff_addr        : std_logic_vector(9 downto 0);
117
 
118
signal buff_data_out_0 : std_logic_vector(7 downto 0);
119
signal buff_data_out_1 : std_logic_vector(7 downto 0);
120
signal buff_data_out_2 : std_logic_vector(7 downto 0);
121
signal buff_data_out_3 : std_logic_vector(7 downto 0);
122
signal buff_data_out_4 : std_logic_vector(7 downto 0);
123
signal buff_data_out_5 : std_logic_vector(7 downto 0);
124
 
125
signal mux_stb         : std_logic_vector(5 downto 0);
126
signal mux_we          : std_logic;
127
signal mux_addr        : std_logic_vector(9 downto 0);
128
 
129
signal ctrl_in         : std_logic_vector(7 downto 0);
130
signal trigger         : std_logic;
131
 
132
component ram1k
133
    Port (
134
            -- Port A is 8 bit
135
       WB_CLK_I  : in  std_logic;
136
       WB_RST_I  : in  std_logic;
137
       WB_ADR_I  : in  std_logic_vector (9 downto 0);
138
       WB_DAT_O  : out std_logic_vector (7 downto 0);
139
       WB_DAT_I  : in  std_logic_vector (7 downto 0);
140
            WB_WE_I   : in  std_logic;
141
       WB_STB_I  : in  std_logic
142
    );
143
end component;
144
 
145
 
146
component BUFG
147
  port (
148
     i: in std_logic;
149
          o: out std_logic
150
  );
151
end component;
152
 
153
begin
154
 
155
--
156
-- Bank 1 = Trace buffer cpu control out
157
--
158
my_trace_buffer_1 : ram1k port map (
159
       WB_CLK_I  => clk,
160
       WB_RST_I  => rst,
161
       WB_ADR_I  => mux_addr,
162
       WB_DAT_O  => buff_data_out_1,
163
       WB_DAT_I  => ctrl_in(7 downto 0),
164
            WB_WE_I   => mux_we,
165
       WB_STB_I  => mux_stb(1)
166
    );
167
 
168
--
169
-- Trace buffer 2 is cpu address out high
170
--
171
my_trace_buffer_2 : ram1k port map (
172
       WB_CLK_I  => clk,
173
       WB_RST_I  => rst,
174
       WB_ADR_I  => mux_addr,
175
       WB_DAT_O  => buff_data_out_2,
176
       WB_DAT_I  => addr(15 downto 8),
177
            WB_WE_I   => mux_we,
178
       WB_STB_I  => mux_stb(2)
179
    );
180
 
181
--
182
-- Trace buffer 3 is cpu address out low
183
--
184
my_trace_buffer_3 : ram1k port map (
185
       WB_CLK_I  => clk,
186
       WB_RST_I  => rst,
187
       WB_ADR_I  => mux_addr,
188
       WB_DAT_O  => buff_data_out_3,
189
       WB_DAT_I  => addr(7 downto 0),
190
            WB_WE_I   => mux_we,
191
       WB_STB_I  => mux_stb(3)
192
    );
193
 
194
--
195
-- Trace buffer 4 is cpu data out
196
--
197
my_trace_buffer_4 : ram1k port map (
198
       WB_CLK_I  => clk,
199
       WB_RST_I  => rst,
200
       WB_ADR_I  => mux_addr,
201
       WB_DAT_O  => buff_data_out_4,
202
       WB_DAT_I  => data_in(7 downto 0),
203
            WB_WE_I   => mux_we,
204
       WB_STB_I  => mux_stb(4)
205
    );
206
 
207
--
208
-- Trace buffer 5 is cpu data in
209
--
210
my_trace_buffer_5 : ram1k port map (
211
       WB_CLK_I  => clk,
212
       WB_RST_I  => rst,
213
       WB_ADR_I  => mux_addr,
214
       WB_DAT_O  => buff_data_out_5,
215
       WB_DAT_I  => cpu_data_in(7 downto 0),
216
            WB_WE_I   => mux_we,
217
       WB_STB_I  => mux_stb(5)
218
    );
219
 
220
 
221
--clk_buffer : BUFG port map(
222
--      i => clk_n,
223
--         o => trace_clk
224
--   );  
225
 
226
--------------------------------
227
--
228
-- write page bank register
229
--
230
--------------------------------
231
bank_reg_write : process( clk, rst, rs, rw, data_in, bank_reg)
232
begin
233
        if clk'event and clk = '0' then
234
                if rst = '1' then
235
                        bank_reg <= "00000000";
236
                else
237
                        if rs='1' and rw='0' then
238
                                bank_reg <= data_in;
239
                        else
240
                           bank_reg <= bank_reg;
241
                        end if;
242
                end if;
243
        end if;
244
end process;
245
 
246
 
247
--------------------------------
248
--
249
-- read page buffers
250
--
251
--------------------------------
252
 
253
buffer_read : process(  bs, bank_reg,
254
                                                                buff_data_out_0, buff_data_out_1, buff_data_out_2, buff_data_out_3,
255
                                                                buff_data_out_4, buff_data_out_5 )
256
variable count : integer;
257
begin
258
        for count in 0 to 5 loop
259
                buff_stb(count) <= '0';
260
        end loop;
261
 
262
        case bank_reg(2 downto 0) is
263
        when "000" =>
264
                buff_stb(0)   <= bs;
265
                buff_data_out <= buff_data_out_0;
266
        when "001" =>
267
           buff_stb(1)   <= bs;
268
                buff_data_out <= buff_data_out_1;
269
        when "010" =>
270
                buff_stb(2)   <= bs;
271
                buff_data_out <= buff_data_out_2;
272
        when "011" =>
273
                buff_stb(3)   <= bs;
274
                buff_data_out <= buff_data_out_3;
275
        when "100" =>
276
                buff_stb(4)   <= bs;
277
                buff_data_out <= buff_data_out_4;
278
        when "101" =>
279
                buff_stb(5)   <= bs;
280
                buff_data_out <= buff_data_out_5;
281
   when others =>
282
                buff_data_out <= "00000000";
283
        end case;
284
 
285
        reg_data_out <= bank_reg;
286
 
287
end process;
288
 
289
--------------------------------
290
--
291
-- write control registers
292
--
293
--------------------------------
294
trace_write : process( clk, rst, bs, rw, addr, data_in, qual_write,
295
                      comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
296
                      qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl )
297
begin
298
  if clk'event and clk = '0' then
299
    if rst = '1' then
300
                  comp_addr_hi <= "00000000";
301
                  comp_addr_lo <= "00000000";
302
                  comp_data    <= "00000000";
303
                  comp_ctrl    <= "00000000";
304
                  qual_addr_hi <= "00000000";
305
                  qual_addr_lo <= "00000000";
306
                  qual_data    <= "00000000";
307
                  qual_ctrl    <= "00000000";
308
                  qual_write  <= '0';
309
    elsif buff_stb(0) = '1' and rw = '0' then
310
           case addr(2 downto 0) is
311
                when "000" =>
312
                  comp_addr_hi <= data_in;
313
                  comp_addr_lo <= comp_addr_lo;
314
                  comp_data    <= comp_data;
315
                  comp_ctrl    <= comp_ctrl;
316
                  qual_addr_hi <= qual_addr_hi;
317
                  qual_addr_lo <= qual_addr_lo;
318
                  qual_data    <= qual_data;
319
                  qual_ctrl    <= qual_ctrl;
320
                  qual_write  <= '0';
321
                when "001" =>
322
                  comp_addr_hi <= comp_addr_hi;
323
                  comp_addr_lo <= data_in;
324
                  comp_data    <= comp_data;
325
                  comp_ctrl    <= comp_ctrl;
326
                  qual_addr_hi <= qual_addr_hi;
327
                  qual_addr_lo <= qual_addr_lo;
328
                  qual_data    <= qual_data;
329
                  qual_ctrl    <= qual_ctrl;
330
                  qual_write  <= '0';
331
                when "010" =>
332
                  comp_addr_hi <= comp_addr_hi;
333
                  comp_addr_lo <= comp_addr_lo;
334
                  comp_data    <= data_in;
335
                  comp_ctrl    <= comp_ctrl;
336
                  qual_addr_hi <= qual_addr_hi;
337
                  qual_addr_lo <= qual_addr_lo;
338
                  qual_data    <= qual_data;
339
                  qual_ctrl    <= qual_ctrl;
340
                  qual_write  <= '0';
341
                when "011" =>
342
                  comp_addr_hi <= comp_addr_hi;
343
                  comp_addr_lo <= comp_addr_lo;
344
                  comp_data    <= comp_data;
345
                  comp_ctrl    <= data_in;
346
                  qual_addr_hi <= qual_addr_hi;
347
                  qual_addr_lo <= qual_addr_lo;
348
                  qual_data    <= qual_data;
349
                  qual_ctrl    <= qual_ctrl;
350
                  qual_write  <= '0';
351
                when "100" =>
352
                  comp_addr_hi <= comp_addr_hi;
353
                  comp_addr_lo <= comp_addr_lo;
354
                  comp_data    <= comp_data;
355
                  comp_ctrl    <= comp_ctrl;
356
                  qual_addr_hi <= data_in;
357
                  qual_addr_lo <= qual_addr_lo;
358
                  qual_data    <= qual_data;
359
                  qual_ctrl    <= qual_ctrl;
360
                  qual_write  <= '0';
361
                when "101" =>
362
                  comp_addr_hi <= comp_addr_hi;
363
                  comp_addr_lo <= comp_addr_lo;
364
                  comp_data    <= comp_data;
365
                  comp_ctrl    <= comp_ctrl;
366
                  qual_addr_hi <= qual_addr_hi;
367
                  qual_addr_lo <= data_in;
368
                  qual_data    <= qual_data;
369
                  qual_ctrl    <= qual_ctrl;
370
                  qual_write  <= '0';
371
                when "110" =>
372
                  comp_addr_hi <= comp_addr_hi;
373
                  comp_addr_lo <= comp_addr_lo;
374
                  comp_data    <= comp_data;
375
                  comp_ctrl    <= comp_ctrl;
376
                  qual_addr_hi <= qual_addr_hi;
377
                  qual_addr_lo <= qual_addr_lo;
378
                  qual_data    <= data_in;
379
                  qual_ctrl    <= qual_ctrl;
380
                  qual_write  <= '0';
381
--              when "111" =>
382
      when others =>
383
                  comp_addr_hi <= comp_addr_hi;
384
                  comp_addr_lo <= comp_addr_lo;
385
                  comp_data    <= comp_data;
386
                  comp_ctrl    <= comp_ctrl;
387
                  qual_addr_hi <= qual_addr_hi;
388
                  qual_addr_lo <= qual_addr_lo;
389
                  qual_data    <= qual_data;
390
                  qual_ctrl    <= data_in;
391
                  qual_write  <= '1';
392
                end case;
393
         else
394
                  comp_addr_hi <= comp_addr_hi;
395
                  comp_addr_lo <= comp_addr_lo;
396
                  comp_data    <= comp_data;
397
                  comp_ctrl    <= comp_ctrl;
398
                  qual_addr_hi <= qual_addr_hi;
399
                  qual_addr_lo <= qual_addr_lo;
400
                  qual_data    <= qual_data;
401
                  qual_ctrl    <= qual_ctrl;
402
                  qual_write  <= '0';
403
         end if;
404
  end if;
405
end process;
406
 
407
--
408
-- trap data output mux
409
--
410
trace_read : process( buff_stb, rw, addr, qual_read,
411
                     comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
412
                     qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl,
413
                                                        match_flag )
414
begin
415
   case addr(2 downto 0) is
416
        when "000" =>
417
           buff_data_out_0  <= comp_addr_hi;
418
                qual_read <= '0';
419
        when "001" =>
420
           buff_data_out_0  <= comp_addr_lo;
421
                qual_read <= '0';
422
        when "010" =>
423
           buff_data_out_0  <= comp_data;
424
                qual_read <= '0';
425
        when "011" =>
426
           buff_data_out_0  <= comp_ctrl;
427
                qual_read <= '0';
428
        when "100" =>
429
           buff_data_out_0  <= qual_addr_hi;
430
                qual_read <= '0';
431
        when "101" =>
432
           buff_data_out_0  <= qual_addr_lo;
433
                qual_read <= '0';
434
        when "110" =>
435
           buff_data_out_0  <= qual_data;
436
                qual_read <= '0';
437
--      when "111" =>
438
   when others =>
439
                qual_read <= buff_stb(0) and rw;
440
           buff_data_out_0(6 downto 0) <= qual_ctrl(6 downto 0);
441
                buff_data_out_0(7) <= match_flag;
442
        end case;
443
end process;
444
 
445
mux_proc : process( bs, rw,
446
                    trace_count, buff_addr,
447
                                                  trace_we,   buff_we,
448
                                                  trace_stb,  buff_stb )
449
begin
450
 
451
        if bs='0' and rw='1' then
452
                mux_addr <= trace_count;
453
                mux_we   <= trace_we;
454
                mux_stb  <= trace_stb & trace_stb & trace_stb & trace_stb & trace_stb & trace_stb;
455
        else
456
                mux_addr <= buff_addr;
457
                mux_we   <= buff_we;
458
                mux_stb  <= buff_stb;
459
        end if;
460
 
461
end process;
462
 
463
--
464
-- Trigger hardware
465
--
466
trace_match : process( Clk, rst, rw, buff_stb, addr, vma, match_flag, data_in,
467
                      comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
468
                                                         qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl)
469
variable match         : std_logic;
470
variable match_addr_hi : std_logic;
471
variable match_addr_lo : std_logic;
472
variable match_data    : std_logic;
473
variable match_ctrl    : std_logic;
474
 
475
begin
476
  match_addr_hi :=
477
           ((comp_addr_hi(7) xor addr(15)  ) and qual_addr_hi(7) ) or
478
                     ((comp_addr_hi(6) xor addr(14)  ) and qual_addr_hi(6) ) or
479
                     ((comp_addr_hi(5) xor addr(13)  ) and qual_addr_hi(5) ) or
480
                     ((comp_addr_hi(4) xor addr(12)  ) and qual_addr_hi(4) ) or
481
                     ((comp_addr_hi(3) xor addr(11)  ) and qual_addr_hi(3) ) or
482
                     ((comp_addr_hi(2) xor addr(10)  ) and qual_addr_hi(2) ) or
483
                     ((comp_addr_hi(1) xor addr( 9)  ) and qual_addr_hi(1) ) or
484
                     ((comp_addr_hi(0) xor addr( 8)  ) and qual_addr_hi(0) );
485
  match_addr_lo :=
486
                     ((comp_addr_lo(7) xor addr( 7)  ) and qual_addr_lo(7) ) or
487
                     ((comp_addr_lo(6) xor addr( 6)  ) and qual_addr_lo(6) ) or
488
                     ((comp_addr_lo(5) xor addr( 5)  ) and qual_addr_lo(5) ) or
489
                     ((comp_addr_lo(4) xor addr( 4)  ) and qual_addr_lo(4) ) or
490
                     ((comp_addr_lo(3) xor addr( 3)  ) and qual_addr_lo(3) ) or
491
                     ((comp_addr_lo(2) xor addr( 2)  ) and qual_addr_lo(2) ) or
492
                     ((comp_addr_lo(1) xor addr( 1)  ) and qual_addr_lo(1) ) or
493
                     ((comp_addr_lo(0) xor addr( 0)  ) and qual_addr_lo(0) );
494
  match_data :=
495
           ((comp_data(7)    xor data_in(7)) and qual_data(7)    ) or
496
           ((comp_data(6)    xor data_in(6)) and qual_data(6)    ) or
497
           ((comp_data(5)    xor data_in(5)) and qual_data(5)    ) or
498
           ((comp_data(4)    xor data_in(4)) and qual_data(4)    ) or
499
           ((comp_data(3)    xor data_in(3)) and qual_data(3)    ) or
500
           ((comp_data(2)    xor data_in(2)) and qual_data(2)    ) or
501
           ((comp_data(1)    xor data_in(1)) and qual_data(1)    ) or
502
           ((comp_data(0)    xor data_in(0)) and qual_data(0)    );
503
  match_ctrl :=
504
           ((comp_ctrl(0)    xor rw        ) and qual_ctrl(0)    ) or
505
           ((comp_ctrl(1)    xor vma       ) and qual_ctrl(1)    );
506
 
507
   match := not ( match_addr_hi or match_addr_lo or match_data or match_ctrl);
508
 
509
    if clk'event and clk = '0' then
510
           if rst = '1' then
511
                  match_flag <= '0';
512
      elsif buff_stb(0) = '1' and rw = '0' then
513
                  match_flag <= '0';
514
      else
515
                  if match = comp_ctrl(7) then
516
                    match_flag <= '1';
517
                  else
518
                    match_flag <= match_flag;
519
                  end if;
520
 
521
                end if;
522
    end if;
523
         trigger <= match_flag;
524
  end process;
525
 
526
trace_capture : process( clk, rst, qual_read, qual_write,
527
                                                                 trigger, trace_stb, qual_ctrl, irq_out,
528
                         trace_count, trace_offset )
529
variable irq_tmp : std_logic;
530
begin
531
  if clk'event and clk = '1' then
532
    if rst = '1' then
533
                trace_count  <= "0000000000";
534
                trace_offset <= "0000000000";
535
                trace_stb    <= qual_ctrl(6);
536
         else
537
           --
538
                -- zero in bit 6 of the qalifier control register
539
                -- means start capture after trigger point.
540
                --
541
                if qual_ctrl(6) = '0' then
542
 
543
                        if trace_stb = '0' then
544
                                trace_stb    <= trigger;
545
                                irq_tmp      := irq_out;
546
                                trace_offset <= trace_count;
547
                        else
548
                                if trace_count = trace_offset then
549
                                        trace_stb <= '0';
550
                                        irq_tmp   := '1';
551
                                else
552
                                        trace_stb  <= trace_stb;
553
                                        irq_tmp    := irq_out;
554
                                end if;
555
                                trace_offset <= trace_offset;
556
                        end if;
557
 
558
                        if qual_read = '1' then
559
                                irq_out <= '0';
560
                        else
561
                                irq_out <= irq_tmp;
562
                        end if;
563
           --
564
                -- one in bit 6 of the qalifier control register
565
                -- means finish capture at trigger point.
566
                --
567
                else
568
                if trace_stb = '0' then
569
                                trace_stb    <= qual_write;
570
                                trace_offset <= trace_offset;
571
                                irq_tmp      := irq_out;
572
                        else
573
                                if trigger = '1' then
574
                                   trace_offset <= trace_count;
575
                                        trace_stb    <= '0';
576
                                        irq_tmp      := '1';
577
                                else
578
                                        trace_offset <= trace_offset;
579
                                        trace_stb    <= trace_stb;
580
                                        irq_tmp      := irq_out;
581
                                end if;
582
                        end if;
583
 
584
                        if qual_write = '1' then
585
                                irq_out <= '0';
586
                        else
587
                                irq_out <= irq_tmp;
588
                        end if;
589
                end if;
590
                trace_count <= trace_count + 1;
591
         end if;
592
  end if;
593
end process;
594
 
595
--
596
-- Tie up a few signals
597
--
598
process( clk, rst, addr, vma, rw, irq_out, trace_offset, qual_ctrl, trace_stb )
599
begin
600
  trace_clk  <= clk;
601
  trace_rst  <= rst;
602
  trace_we   <= trace_stb;
603
  buff_addr  <= addr(9 downto 0) + trace_offset;
604
  buff_we    <= '0';
605
  irq        <= irq_out and qual_ctrl(7);
606
  ctrl_in(0) <= rw;
607
  ctrl_in(1) <= vma;
608
  ctrl_in(7 downto 2) <= "000000";
609
end process;
610
 
611
end trace_arch;
612
 

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