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[/] [System09/] [trunk/] [rtl/] [VHDL/] [trap.vhd] - Blame information for rev 95

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1 19 dilbert57
--===========================================================================--
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--
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--  S Y N T H E Z I A B L E    Timer   C O R E
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--
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--  www.OpenCores.Org - May 2003
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--  This core adheres to the GNU public license  
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--
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-- File name      : Trap.vhd
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--
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-- entity name    : trap
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--
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-- Purpose        : Implements a 8 bit address and data comparitor module
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_unsigned
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--
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-- Author         : John E. Kent      
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--
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--===========================================================================----
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--
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-- Revision History:
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--
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-- Date:          Revision         Author
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-- 5 May 2003     0.1              John Kent
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--
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--===========================================================================----
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--
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-- Register Memory Map
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--
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-- $00 - Address Comparitor High Byte
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-- $01 - Address Comparitor Low byte
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-- $02 - Data    Comparitor
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-- $03 - Control Comparitor
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-- $04 - Address Qualifier High Byte
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-- $05 - Address Qualifier Low byte
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-- $06 - Data    Qualifier
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-- $07 - Control Qualifier
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--
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-- Address, Data and Control signals must match in the Comparitor registers 
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-- Matches are qualified by setting a bit in the Qualifier registers
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--
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-- Control Comparitor / Qualify (write)
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-- b0 - r/w        1=read  0=write
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-- b1 - vma        1=valid 0=invalid
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-- b7 - irq output 1=match 0=mismatch
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--
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-- Control Qualifier Read
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-- b7 - match flag
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity trap is
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        port (
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         clk        : in  std_logic;
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    rst        : in  std_logic;
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    cs         : in  std_logic;
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    rw         : in  std_logic;
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         vma        : in  std_logic;
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    addr       : in  std_logic_vector(15 downto 0);
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    data_in    : in  std_logic_vector(7 downto 0);
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         data_out   : out std_logic_vector(7 downto 0);
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         irq        : out std_logic
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  );
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end;
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architecture trap_arch of trap is
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--
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-- Trap registers
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--
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signal comp_addr_hi : std_logic_vector(7 downto 0);
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signal comp_addr_lo : std_logic_vector(7 downto 0);
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signal qual_addr_hi : std_logic_vector(7 downto 0);
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signal qual_addr_lo : std_logic_vector(7 downto 0);
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signal comp_data    : std_logic_vector(7 downto 0);
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signal qual_data    : std_logic_vector(7 downto 0);
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signal comp_ctrl    : std_logic_vector(7 downto 0);
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signal qual_ctrl    : std_logic_vector(7 downto 0);
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signal match_flag   : std_logic;
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begin
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--------------------------------
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--
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-- write control registers
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--
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--------------------------------
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trap_write : process( clk, rst, cs, rw, addr, data_in,
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                      comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
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                      qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl )
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begin
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  if clk'event and clk = '0' then
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    if rst = '1' then
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                  comp_addr_hi <= "00000000";
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                  comp_addr_lo <= "00000000";
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                  comp_data    <= "00000000";
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                  comp_ctrl    <= "00000000";
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                  qual_addr_hi <= "00000000";
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                  qual_addr_lo <= "00000000";
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                  qual_data    <= "00000000";
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                  qual_ctrl    <= "00000000";
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    elsif cs = '1' and rw = '0' then
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           case addr(2 downto 0) is
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                when "000" =>
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                  comp_addr_hi <= data_in;
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                  comp_addr_lo <= comp_addr_lo;
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                  comp_data    <= comp_data;
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                  comp_ctrl    <= comp_ctrl;
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                  qual_addr_hi <= qual_addr_hi;
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                  qual_addr_lo <= qual_addr_lo;
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                  qual_data    <= qual_data;
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                  qual_ctrl    <= qual_ctrl;
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                when "001" =>
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                  comp_addr_hi <= comp_addr_hi;
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                  comp_addr_lo <= data_in;
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                  comp_data    <= comp_data;
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                  comp_ctrl    <= comp_ctrl;
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                  qual_addr_hi <= qual_addr_hi;
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                  qual_addr_lo <= qual_addr_lo;
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                  qual_data    <= qual_data;
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                  qual_ctrl    <= qual_ctrl;
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                when "010" =>
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                  comp_addr_hi <= comp_addr_hi;
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                  comp_addr_lo <= comp_addr_lo;
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                  comp_data    <= data_in;
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                  comp_ctrl    <= comp_ctrl;
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                  qual_addr_hi <= qual_addr_hi;
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                  qual_addr_lo <= qual_addr_lo;
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                  qual_data    <= qual_data;
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                  qual_ctrl    <= qual_ctrl;
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                when "011" =>
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                  comp_addr_hi <= comp_addr_hi;
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                  comp_addr_lo <= comp_addr_lo;
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                  comp_data    <= comp_data;
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                  comp_ctrl    <= data_in;
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                  qual_addr_hi <= qual_addr_hi;
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                  qual_addr_lo <= qual_addr_lo;
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                  qual_data    <= qual_data;
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                  qual_ctrl    <= qual_ctrl;
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                when "100" =>
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                  comp_addr_hi <= comp_addr_hi;
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                  comp_addr_lo <= comp_addr_lo;
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                  comp_data    <= comp_data;
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                  comp_ctrl    <= comp_ctrl;
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                  qual_addr_hi <= data_in;
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                  qual_addr_lo <= qual_addr_lo;
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                  qual_data    <= qual_data;
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                  qual_ctrl    <= qual_ctrl;
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                when "101" =>
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                  comp_addr_hi <= comp_addr_hi;
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                  comp_addr_lo <= comp_addr_lo;
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                  comp_data    <= comp_data;
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                  comp_ctrl    <= comp_ctrl;
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                  qual_addr_hi <= qual_addr_hi;
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                  qual_addr_lo <= data_in;
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                  qual_data    <= qual_data;
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                  qual_ctrl    <= qual_ctrl;
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                when "110" =>
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                  comp_addr_hi <= comp_addr_hi;
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                  comp_addr_lo <= comp_addr_lo;
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                  comp_data    <= comp_data;
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                  comp_ctrl    <= comp_ctrl;
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                  qual_addr_hi <= qual_addr_hi;
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                  qual_addr_lo <= qual_addr_lo;
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                  qual_data    <= data_in;
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                  qual_ctrl    <= qual_ctrl;
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--              when "111" =>
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      when others =>
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                  comp_addr_hi <= comp_addr_hi;
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                  comp_addr_lo <= comp_addr_lo;
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                  comp_data    <= comp_data;
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                  comp_ctrl    <= comp_ctrl;
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                  qual_addr_hi <= qual_addr_hi;
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                  qual_addr_lo <= qual_addr_lo;
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                  qual_data    <= qual_data;
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                  qual_ctrl    <= data_in;
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                end case;
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         else
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                  comp_addr_hi <= comp_addr_hi;
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                  comp_addr_lo <= comp_addr_lo;
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                  comp_data    <= comp_data;
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                  comp_ctrl    <= comp_ctrl;
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                  qual_addr_hi <= qual_addr_hi;
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                  qual_addr_lo <= qual_addr_lo;
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                  qual_data    <= qual_data;
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                  qual_ctrl    <= qual_ctrl;
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         end if;
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  end if;
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end process;
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--
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-- trap data output mux
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--
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trap_read : process( addr,
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                     comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
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                     qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl,
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                                                        match_flag )
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begin
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   case addr(2 downto 0) is
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        when "000" =>
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           data_out <= comp_addr_hi;
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        when "001" =>
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           data_out <= comp_addr_lo;
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        when "010" =>
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           data_out <= comp_data;
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        when "011" =>
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           data_out <= comp_ctrl;
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        when "100" =>
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           data_out <= qual_addr_hi;
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        when "101" =>
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           data_out <= qual_addr_lo;
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        when "110" =>
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           data_out <= qual_data;
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--      when "111" =>
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   when others =>
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           data_out(6 downto 0) <= qual_ctrl(6 downto 0);
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                data_out(7) <= match_flag;
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        end case;
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end process;
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--
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-- Trap hardware
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--
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trap_match : process( Clk, rst, cs, rw, addr, vma, match_flag, data_in,
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                      comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
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                                                         qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl)
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variable match         : std_logic;
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variable match_addr_hi : std_logic;
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variable match_addr_lo : std_logic;
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variable match_data    : std_logic;
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variable match_ctrl    : std_logic;
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begin
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  match_addr_hi :=
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           ((comp_addr_hi(7) xor addr(15)  ) and qual_addr_hi(7) ) or
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                     ((comp_addr_hi(6) xor addr(14)  ) and qual_addr_hi(6) ) or
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                     ((comp_addr_hi(5) xor addr(13)  ) and qual_addr_hi(5) ) or
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                     ((comp_addr_hi(4) xor addr(12)  ) and qual_addr_hi(4) ) or
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                     ((comp_addr_hi(3) xor addr(11)  ) and qual_addr_hi(3) ) or
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                     ((comp_addr_hi(2) xor addr(10)  ) and qual_addr_hi(2) ) or
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                     ((comp_addr_hi(1) xor addr( 9)  ) and qual_addr_hi(1) ) or
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                     ((comp_addr_hi(0) xor addr( 8)  ) and qual_addr_hi(0) );
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  match_addr_lo :=
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                     ((comp_addr_lo(7) xor addr( 7)  ) and qual_addr_lo(7) ) or
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                     ((comp_addr_lo(6) xor addr( 6)  ) and qual_addr_lo(6) ) or
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                     ((comp_addr_lo(5) xor addr( 5)  ) and qual_addr_lo(5) ) or
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                     ((comp_addr_lo(4) xor addr( 4)  ) and qual_addr_lo(4) ) or
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                     ((comp_addr_lo(3) xor addr( 3)  ) and qual_addr_lo(3) ) or
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                     ((comp_addr_lo(2) xor addr( 2)  ) and qual_addr_lo(2) ) or
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                     ((comp_addr_lo(1) xor addr( 1)  ) and qual_addr_lo(1) ) or
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                     ((comp_addr_lo(0) xor addr( 0)  ) and qual_addr_lo(0) );
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  match_data :=
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           ((comp_data(7)    xor data_in(7)) and qual_data(7)    ) or
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           ((comp_data(6)    xor data_in(6)) and qual_data(6)    ) or
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           ((comp_data(5)    xor data_in(5)) and qual_data(5)    ) or
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           ((comp_data(4)    xor data_in(4)) and qual_data(4)    ) or
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           ((comp_data(3)    xor data_in(3)) and qual_data(3)    ) or
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           ((comp_data(2)    xor data_in(2)) and qual_data(2)    ) or
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           ((comp_data(1)    xor data_in(1)) and qual_data(1)    ) or
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           ((comp_data(0)    xor data_in(0)) and qual_data(0)    );
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  match_ctrl :=
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           ((comp_ctrl(0)    xor rw        ) and qual_ctrl(0)    ) or
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           ((comp_ctrl(1)    xor vma       ) and qual_ctrl(1)    );
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   match := not ( match_addr_hi or match_addr_lo or match_data or match_ctrl);
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    if clk'event and clk = '0' then
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           if rst = '1' then
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                  match_flag <= '0';
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      elsif cs = '1' and rw = '0' then
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                  match_flag <= '0';
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      else
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                  if match = comp_ctrl(7) then
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                    match_flag <= '1';
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                  else
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                    match_flag <= match_flag;
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                  end if;
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                end if;
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    end if;
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         irq <= match_flag and qual_ctrl(7);
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  end process;
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end trap_arch;
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