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[/] [System09/] [trunk/] [rtl/] [VHDL/] [vdu8_bert.vhd] - Blame information for rev 131

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1 118 dilbert57
--===========================================================================--
2
--                                                                           --
3
--  vdu8_bert.vhd - Synthesizable Colour Video Display Unit for System09     --
4
--                                                                           --
5
--===========================================================================--
6 19 dilbert57
--
7 118 dilbert57
--  File name      : vdu8_bert.vhd
8 19 dilbert57
--
9 118 dilbert57
--  Purpose        : Implements a text based Colour Video Display Unit for System09
10
--                   Supports 2KByte Text buffer and 2KByte Attribute memory
11
--                   Displays 80 characters across by 25 character rows
12
--                   Characters are 8 pixels across x 16 lines down.
13
--                   Character attribute bita for foreground and backgrond colour
14
--                   1 bit for each Blue Green and Red signal
15
--                   Supports 2 x 8 chunky graphics character mode.
16
--                   Assumes a pixel clock input of 50 MHz
17
--                   Generates a 12.5MHz CPU Clock output for old Spartan 2 boards.
18
--                   Partially cleaned up by Bertrand Cuzeau
19
--                  
20
--  Dependencies   : ieee.Std_Logic_1164
21
--                   ieee.std_logic_unsigned
22
--                   ieee.std_logic_arith
23
--                   ieee.numeric_std
24
--
25
--  Uses           : ram_2k (ram2k_b16.vhd)             2KByte Character & Attribute buffer
26
--                   char_rom (char_rom2k_b16.vhd)      2KByte Character Generator ROM 
27
--
28
--  Author         : John E. Kent
29
--
30
--  Email          : dilbert57@opencores.org      
31
--
32
--  Web            : http://opencores.org/project,system09
33
--
34
--  Description    : Display Timing:
35
--                       800 pixels / line
36
--                       446 lines / frame
37
--                       None interlaced
38
--                       25MHz pixel clock implies 
39
--                       31.25 KHz line rate
40
--                       70.067 Hz frame rate   
41
--                       Timing settable by generics.
42
--
43
--                   Display Size:
44
--                       80 characters across
45
--                       25 characters down.
46
--
47
--                   Character Size:
48
--                        8 horizontal pixels across
49
--                       16 vertical scan lines down (2 scan lines/row)
50
--
51
--                   Registers:
52
--                   Base + 0 ASCII character register
53
--                            Writing to this register writes an 8 bit byte 
54
--                            into the text buffer at the specified cursor position
55
--                            Text Mode: ASCII Character (0 to 127)
56
--                            Chunky Graphics Mode: B0 B1 (0 to 255)
57
--                                                  B2 B3
58
--                                                  B4 B5
59
--                                                  B6 B7
60
--                   Base + 1 Attibute bit (0 to 255)
61
--                            Writing to the register writes an 8 bit byte 
62
--                            into the attribute buffer at the specified cursor position
63
--                            B7 - 0 => Text Mode / 1 => Chunky Graphics Mode
64
--                            B6 - 1 => Character Background Blue
65
--                            B5 - 1 => Character Background Green
66
--                            B4 - 1 => Character Background Red
67
--                            B3 - 1 => Character Background & Foreground Alternates
68
--                            B2 - 1 => Character Foreground Blue
69
--                            B1 - 1 => Character Foreground Green
70
--                            B0 - 1 => Character Foreground Red
71
--                   Base + 2 Cursor Horizontal Position (0 to 79)
72
--                   Base + 3 Cusror Vertical Position (0 to 24)
73
--                   Base + 4 Vertical Scroll Offset (0 to 24)
74
--                            Scrolls the display up by the specified number of character rows
75
--
76
--  Video Timing :
77
--
78
--  Horizontal 800 Pixels/ 25MHz Pixel Clock = 32usec Line period = 31.25 KHz Line Frequency
79
--  /--------------------------\_____________/---------------\______________/
80
--      640 Pixels Display       16 Pixel FP    96 Pixel HS     48 Pixel BP
81
--    
82
--      VGA_CLK_FREQ           : integer := 25000000; -- HZ
83
--           VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
84
--           VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
85
--           VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
86
--           VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS 0.32us
87
--           VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
88
--
89
--  Vertical 446 Lines * 32 usec Line rate = 14.272ms Frame Period = 70.07Hz Frame frequency  
90
--  /---------------------------\____________/---------------\______________/
91
--      400 Line Display          10 Line FP     2 Line VS      34 Line BP
92
--
93
--           VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
94
--           VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
95
--           VGA_VER_BACK_PORCH     : integer := 34; -- LINES 1.088ms
96
--           VGA_LIN_PER_CHAR       : integer := 16; -- LINES 0.512ms
97
--           VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
98
--
99
--
100
--  Copyright (C) 2003 - 2010 John Kent
101
--
102
--  This program is free software: you can redistribute it and/or modify
103
--  it under the terms of the GNU General Public License as published by
104
--  the Free Software Foundation, either version 3 of the License, or
105
--  (at your option) any later version.
106
--
107
--  This program is distributed in the hope that it will be useful,
108
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
109
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
110
--  GNU General Public License for more details.
111
--
112
--  You should have received a copy of the GNU General Public License
113
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
114
--
115
--===========================================================================--
116
--                                                                           --
117
--                              Revision  History                            --
118
--                                                                           --
119
--===========================================================================--
120
--
121
-- Version Author      Date        Changes
122
--
123
-- 0.1     John Kent   2004-09-03  Initial release
124
--
125
-- 0.2     Bert Cuzeau 2007-01-16  Modified by for compliance and code cleanliness
126
--                                 The effort is not over.
127
--                                 There are still signal initialized, which is BAD.
128
--
129
-- 0.3     John Kent   2010-06-16  Added GPL notice. Updated description
130
--
131 19 dilbert57
 
132
Library IEEE;
133
  use IEEE.std_logic_1164.all;
134
  use IEEE.numeric_std.all;
135
 
136
Entity vdu8 is
137 118 dilbert57
  generic(
138
        VGA_CLK_FREQ           : integer := 25000000; -- HZ
139
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
140
             VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
141
             VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us
142
             VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us
143
             VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us
144
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
145
             VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
146
             VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
147
             VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
148
             VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
149
  );
150 19 dilbert57
  port(
151
    -- control register interface
152
    vdu_clk_in   : in  std_logic;       -- 50MHz  System clock
153
    cpu_clk_out  : out std_logic;       -- 12.5 MHz CPU Clock
154
    vdu_rst      : in  std_logic;
155
    vdu_cs       : in  std_logic;
156
    vdu_rw       : in  std_logic;
157
    vdu_addr     : in  std_logic_vector(2 downto 0);
158
    vdu_data_in  : in  std_logic_vector(7 downto 0);
159
    vdu_data_out : out std_logic_vector(7 downto 0);
160
 
161
    -- vga port connections
162
    vga_red_o   : out std_logic;
163
    vga_green_o : out std_logic;
164
    vga_blue_o  : out std_logic;
165
    vga_hsync_o : out std_logic;
166
    vga_vsync_o : out std_logic
167
    );
168
end vdu8;
169
 
170
Architecture RTL of vdu8 is
171
 
172
  --
173
  -- Synchronisation constants
174
  --
175 118 dilbert57
  --
176
  -- Synchronisation constants
177
  --
178
  -- Displayed Characters per row
179
  constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
180
  -- Last horizontal pixel displayed
181
  constant HOR_DISP_END : integer := (HOR_DISP_CHR * VGA_HOR_CHAR_PIXELS) - 1;
182
  -- Start of horizontal synch pulse
183
  constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_FRONT_PORCH;
184
  -- End of Horizontal Synch pulse
185
  constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
186
  -- Last pixel in scan line
187
  constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_BACK_PORCH;
188
 
189
  -- Number of displayed characters rows
190
  constant VER_DISP_CHR : integer := VGA_VER_CHARS;
191
  -- last row displayed
192
  constant VER_DISP_END : integer := (VER_DISP_CHR * VGA_VER_CHAR_LINES) - 1;
193
  -- start of vertical synch pulse
194
  constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_FRONT_PORCH;
195
  -- end of vertical synch pulse
196
  constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
197
  -- Last scan row in the frame
198
  constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_BACK_PORCH;
199 19 dilbert57
 
200
  signal horiz_sync    : std_logic := '1';
201
  signal vert_sync     : std_logic := '1';
202
  signal cursor_on_v   : std_logic;
203
  signal cursor_on_h   : std_logic;
204
  signal video_on_v    : std_logic := '0';
205
  signal video_on_h    : std_logic := '0';
206
  signal h_count       : std_logic_vector(9 downto 0) := (others=>'0');
207
  signal v_count       : std_logic_vector(8 downto 0) := (others=>'0');  -- 0 to VER_SCAN_END
208
  signal blink_count   : std_logic_vector(22 downto 0):= (others=>'1');
209
  --
210
  -- Character generator ROM
211
  --
212
  signal char_addr     : std_logic_vector(10 downto 0);
213
  signal char_data_out : std_logic_vector(7 downto 0);
214
 
215
  --
216
  -- Control Registers
217
  --
218
  signal reg_character : std_logic_vector(7 downto 0);
219
  signal reg_colour    : std_logic_vector(7 downto 0);
220
  signal reg_hcursor   : std_logic_vector(6 downto 0);   -- 80 columns
221
  signal reg_vcursor   : std_logic_vector(4 downto 0);   -- 25 rows
222
  signal reg_voffset   : std_logic_vector(4 downto 0);   -- 25 rows
223
  --
224
  -- Video Shift register
225
  --
226
  signal vga_shift     : std_logic_vector(7 downto 0);
227
  signal vga_fg_colour : std_logic_vector(2 downto 0);
228
  signal vga_bg_colour : std_logic_vector(2 downto 0);
229
  signal cursor_on     : std_logic;
230
  signal cursor_on1    : std_logic;
231
  signal video_on      : std_logic := '0';
232
  signal video_on1     : std_logic := '0';
233
  signal video_on2     : std_logic := '0';
234
  --
235
  -- vga character ram access bus
236
  --
237
  signal col_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
238
  signal row_addr      : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 -1)
239
  signal col1_addr     : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
240
  signal row1_addr     : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 - 1)
241
  signal hor_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
242
  signal ver_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 124
243
  signal vga0_cs       : std_logic;
244
  signal vga0_rw       : std_logic;
245
  signal vga1_cs       : std_logic;
246
  signal vga1_rw       : std_logic;
247
  signal vga2_cs       : std_logic;
248
  signal vga2_rw       : std_logic;
249
  signal vga_cs        : std_logic;
250
  signal vga_rw        : std_logic;
251
  signal vga_addr      : std_logic_vector(10 downto 0) := (others=>'0');  -- 2K byte character buffer
252
  signal vga_data_out  : std_logic_vector(7 downto 0);
253
  signal attr_data_out : std_logic_vector(7 downto 0);
254
  --
255
  -- Character write handshake signals
256
  --
257
  signal req_write     : std_logic;     -- request character write
258
  signal ack_write     : std_logic;
259
  --
260
  -- Clock divider
261
  --
262
  signal clk_count     : unsigned(1 downto 0);
263
  signal vdu_clk       : std_logic;
264
 
265
  --
266
  -- Slice character gen
267
  --
268
  --
269
  -- block Ram Character gen
270
  --
271
  component char_rom
272
    port (
273
      clk   : in  std_logic;
274
      addr  : in  std_logic_vector (10 downto 0);
275
      rdata : out std_logic_vector (7 downto 0)
276
      );
277
  end component;
278
 
279
  component ram_2k
280
    port (
281
      clk   : in  std_logic;
282
      rst   : in  std_logic;
283
      cs    : in  std_logic;
284
      r_wn  : in  std_logic;
285
      addr  : in  std_logic_vector (10 downto 0);
286
      wdata : in  std_logic_vector (7 downto 0);
287
      rdata : out std_logic_vector (7 downto 0)
288
      );
289
  end component;
290
 
291
begin
292
 
293
--
294
-- instantiate Character generator ROM
295
--
296
vdu_char_rom : char_rom port map(
297
    clk   => vdu_clk,
298
    addr  => char_addr,
299
    rdata => char_data_out
300
    );
301
 
302
--
303
-- Character buffer RAM
304
--
305
char_buff_ram : ram_2k port map(
306
    clk   => vdu_clk,
307
    rst   => vdu_rst,
308
    cs    => vga_cs,
309
    r_wn  => vga_rw,
310
    addr  => vga_addr,
311
    wdata => reg_character,
312
    rdata => vga_data_out
313
    );
314
 
315
--
316
-- Attribute buffer RAM
317
--
318
  attr_buff_ram : ram_2k port map(
319
    clk   => vdu_clk,
320
    rst   => vdu_rst,
321
    cs    => vga_cs,
322
    r_wn  => vga_rw,
323
    addr  => vga_addr,
324
    wdata => reg_colour,
325
    rdata => attr_data_out
326
    );
327
 
328
-----------------------
329
-- vdu_clk_buffer : BUFG port map (i => clk_count(0), o => vdu_clk );
330
-- cpu_clk_buffer : BUFG port map (i => clk_count(1), o => cpu_clk_out );
331
  vdu_clk     <= clk_count(0);          -- <<<< modif ALSE B. Cuzeau
332
  cpu_clk_out <= clk_count(1);          -- <<<< modif ALSE B. Cuzeau
333
-----------------------
334
 
335
--
336
-- Clock divider
337
-- Assumes 50 MHz system clock
338
-- 25MHz pixel clock
339
-- 12.5MHz CPU clock
340
--
341
  vga_clock : process(vdu_clk_in, vdu_rst)
342
  begin
343
    if vdu_rst = '1' then
344
      clk_count <= "00";
345
    elsif vdu_clk_in'event and vdu_clk_in = '0' then
346
      clk_count <= clk_count + 1;
347
    end if;
348
  end process;
349
 
350
--
351
-- CPU Write interface
352
--
353
  vga_cpu_write : process(vdu_clk, vdu_rst)
354
  begin
355
    if vdu_rst = '1' then
356
      reg_character <= "00000000";
357
      reg_colour    <= "00000111";
358
      reg_hcursor   <= "0000000";
359
      reg_vcursor   <= "00000";
360
      reg_voffset   <= "00000";
361
      req_write     <= '0';
362
 
363
    elsif vdu_clk'event and vdu_clk = '0' then
364
      if (vdu_cs = '1') and (vdu_rw = '0') then
365
        case vdu_addr is
366
          when "000" =>
367
            reg_character <= vdu_data_in;
368
            req_write     <= '1';
369
          when "001" =>
370
            reg_colour    <= vdu_data_in;
371
          when "010" =>
372
            reg_hcursor   <= vdu_data_in(6 downto 0);
373
          when "011" =>
374
            reg_vcursor   <= vdu_data_in(4 downto 0);
375
          when others =>
376
            reg_voffset   <= vdu_data_in(4 downto 0);
377
        end case;
378
      else
379
 
380
        if (req_write = '1') and (ack_write = '1') then
381
          req_write <= '0';
382
        else
383
          req_write <= req_write;
384
        end if;
385
 
386
      end if;
387
    end if;
388
  end process;
389
--
390
-- CPU Read interface
391
--
392
  vga_cpu_read : process(vdu_addr, vdu_cs,
393
                          reg_character, reg_colour,
394
                          reg_hcursor, reg_vcursor, reg_voffset)
395
  begin
396
    case vdu_addr is
397
      when "000" =>
398
        vdu_data_out <= reg_character;
399
      when "001" =>
400
        vdu_data_out <= reg_colour;
401
      when "010" =>
402
        vdu_data_out <= "0" & reg_hcursor;
403
      when "011" =>
404
        vdu_data_out <= "000" & reg_vcursor;
405
      when others =>
406
        vdu_data_out <= "000" & reg_voffset;
407
    end case;
408
  end process;
409
 
410
--
411
-- Video memory access
412
--
413
  vga_addr_proc : process(vdu_clk, vdu_rst)
414
  begin
415
 
416
    if vdu_rst = '1' then
417
      vga0_cs   <= '0';
418
      vga0_rw   <= '1';
419
      row_addr  <= "000000";
420
      col_addr  <= "0000000";
421
      --
422
      vga1_cs   <= '0';
423
      vga1_rw   <= '1';
424
      row1_addr <= "000000";
425
      col1_addr <= "0000000";
426
      --
427
      vga2_cs   <= '0';
428
      vga2_rw   <= '1';
429
      ver_addr  <= "0000000";
430
      hor_addr  <= "0000000";
431
      --
432
      vga_cs    <= '0';
433
      vga_rw    <= '1';
434
      vga_addr  <= "00000000000";
435
 
436
    elsif vdu_clk'event and vdu_clk = '0' then
437
      --
438
      -- on h_count = 0 initiate character write.
439
      -- all other cycles are reads.
440
      --
441
      case h_count(2 downto 0) is
442
        when "000" =>                   -- pipeline character write
443
          vga0_cs  <= req_write;
444
          vga0_rw  <= '0';
445
          col_addr <= reg_hcursor(6 downto 0);
446
          row_addr <= unsigned("0" & reg_vcursor(4 downto 0)) + unsigned("0" & reg_voffset(4 downto 0));
447
        when others =>                  -- other 6 cycles free
448
          vga0_cs  <= '1';
449
          vga0_rw  <= '1';
450
          col_addr <= h_count(9 downto 3);
451
          row_addr <= unsigned("0" & v_count(8 downto 4)) + unsigned("0" & reg_voffset(4 downto 0));
452
      end case;
453
      --
454
      -- on vdu_clk + 1 round off row address
455
      --
456
      vga1_cs <= vga0_cs;
457
      vga1_rw <= vga0_rw;
458
      if row_addr < VER_DISP_CHR then
459
        row1_addr <= row_addr;
460
      else
461
        row1_addr <= row_addr - VER_DISP_CHR;
462
      end if;
463
      col1_addr <= col_addr;
464
      --
465
      -- on vdu_clk + 2 calculate vertical address
466
      --
467
      vga2_cs   <= vga1_cs;
468
      vga2_rw   <= vga1_rw;
469
      ver_addr  <= std_logic_vector(unsigned("00" & row1_addr(4 downto 0)) + unsigned(row1_addr(4 downto 0) & "00"));
470
      hor_addr  <= col1_addr;
471
      --
472
      -- on vdu_clk + 3 calculate memory address
473
      --
474
      vga_cs    <= vga2_cs;
475
      vga_rw    <= vga2_rw;
476
      vga_addr  <= std_logic_vector(unsigned("0000" & hor_addr) + unsigned(ver_addr & "0000"));
477
    end if;
478
  end process;
479
--
480
-- Video shift register
481
--
482
  vga_shift_proc : process( vdu_clk, vdu_rst)
483
  begin
484
    if vdu_rst = '1' then
485
      ack_write     <= '0';
486
      video_on2     <= '0';
487
      video_on      <= '0';
488
      cursor_on     <= '0';
489
      vga_bg_colour <= "000";
490
      vga_fg_colour <= "111";
491
      vga_shift     <= "00000000";
492
      vga_red_o     <= '0';
493
      vga_green_o   <= '0';
494
      vga_blue_o    <= '0';
495
      -- Put all video signals through DFFs to elminate any delays that cause a blurry image
496
 
497
    elsif vdu_clk'event and vdu_clk = '0' then
498
      -- Character Data valid on 1 count
499
      if h_count(2 downto 0) = "000" then
500
        if (req_write = '1') and (ack_write = '0') then
501
          ack_write <= '1';
502
        elsif (req_write = '0') and (ack_write = '1') then
503
          ack_write <= '0';
504
        else
505
          ack_write <= ack_write;
506
        end if;
507
        video_on2     <= video_on1;
508
        video_on      <= video_on2;
509
        cursor_on     <= (cursor_on1 or attr_data_out(3)) and blink_count(22);
510
        vga_fg_colour <= attr_data_out(2 downto 0);
511
        vga_bg_colour <= attr_data_out(6 downto 4);
512
        if attr_data_out(7) = '0' then
513
          vga_shift <= char_data_out;
514
        else
515
          case v_count(3 downto 2) is
516
            when "00" =>
517
              vga_shift(7 downto 4) <= vga_data_out(0) & vga_data_out(0) & vga_data_out(0) & vga_data_out(0);
518
              vga_shift(3 downto 0) <= vga_data_out(1) & vga_data_out(1) & vga_data_out(1) & vga_data_out(1);
519
            when "01" =>
520
              vga_shift(7 downto 4) <= vga_data_out(2) & vga_data_out(2) & vga_data_out(2) & vga_data_out(2);
521
              vga_shift(3 downto 0) <= vga_data_out(3) & vga_data_out(3) & vga_data_out(3) & vga_data_out(3);
522
            when "10" =>
523
              vga_shift(7 downto 4) <= vga_data_out(4) & vga_data_out(4) & vga_data_out(4) & vga_data_out(4);
524
              vga_shift(3 downto 0) <= vga_data_out(5) & vga_data_out(5) & vga_data_out(5) & vga_data_out(5);
525
            when others =>
526
              vga_shift(7 downto 4) <= vga_data_out(6) & vga_data_out(6) & vga_data_out(6) & vga_data_out(6);
527
              vga_shift(3 downto 0) <= vga_data_out(7) & vga_data_out(7) & vga_data_out(7) & vga_data_out(7);
528
          end case;
529
        end if;
530
      else
531
        vga_shift <= vga_shift(6 downto 0) & '0';
532
      end if;
533
 
534
      --
535
      -- Colour mask is
536
      --  7  6  5  4  3  2  1  0
537
      --  X BG BB BR  X FG FB FR
538
      --
539
      if vga_shift(7) = (not cursor_on) then
540
        vga_red_o   <= video_on and vga_fg_colour(0);
541
        vga_green_o <= video_on and vga_fg_colour(1);
542
        vga_blue_o  <= video_on and vga_fg_colour(2);
543
      else
544
        vga_red_o   <= video_on and vga_bg_colour(0);
545
        vga_green_o <= video_on and vga_bg_colour(1);
546
        vga_blue_o  <= video_on and vga_bg_colour(2);
547
      end if;
548
    end if;
549
  end process;
550
 
551
 
552
--
553
-- Sync generator & timing process
554
-- Generate Horizontal and Vertical Timing Signals for Video Signal
555
--
556
  vga_sync : process(vdu_clk)
557
  begin
558
    if vdu_clk'event and vdu_clk = '0' then
559
      --
560
      -- H_count counts pixels (640 + extra time for sync signals)
561
      --
562
      --  Horiz_sync  -----------------------------__________--------
563
      --  H_count       0                640      659       755    799
564
      --
565
      if unsigned(h_count) = HOR_SCAN_END then
566
        h_count <= (others=>'0');
567
      else
568
        h_count <= std_logic_vector(unsigned(h_count) + 1);
569
      end if;
570
--
571
-- Generate Horizontal Sync Signal using H_count
572
--
573
      if unsigned(h_count) = HOR_SYNC_BEG then
574
        horiz_sync <= '0';
575
      elsif unsigned(h_count) = HOR_SYNC_END then
576
        horiz_sync <= '1';
577
      else
578
        horiz_sync <= horiz_sync;
579
      end if;
580
--
581
-- V_count counts rows of pixels
582
-- 400 lines + extra time for sync signals
583
-- 25 rows * 16 scan lines
584
--
585
--  Vert_sync      ---------------------------------_______------------
586
--  V_count         0                       400    413     414        444
587
--
588
      if (unsigned(v_count) = VER_SCAN_END) and (unsigned(h_count) = HOR_SCAN_END) then
589
        v_count <= "000000000";
590
      elsif unsigned(h_count) = HOR_SYNC_END then
591
        v_count <= std_logic_vector(unsigned(v_count) + 1);
592
      end if;
593
--
594
-- Generate Vertical Sync Signal using V_count
595
--
596
      if unsigned(v_count) = VER_SYNC_BEG then
597
        vert_sync <= '0';
598
      elsif unsigned(v_count) = VER_SYNC_END then
599
        vert_sync <= '1';
600
      else
601
        vert_sync <= vert_sync;
602
      end if;
603
 
604
-- Generate Video on Screen Signals for Pixel Data
605
      if unsigned(h_count) = HOR_SCAN_END then
606
        video_on_h <= '1';
607
      elsif unsigned(h_count) = HOR_DISP_END then
608
        video_on_h <= '0';
609
      else
610
        video_on_h <= video_on_h;
611
      end if;
612
 
613
      if unsigned(v_count) = VER_SCAN_END then
614
        video_on_v <= '1';
615
      elsif unsigned(v_count) = VER_DISP_END then
616
        video_on_v <= '0';
617
      else
618
        video_on_v <= video_on_v;
619
      end if;
620
 
621
 
622
      if h_count(9 downto 3) = reg_hcursor(6 downto 0) then
623
        cursor_on_h <= '1';
624
      else
625
        cursor_on_h <= '0';
626
      end if;
627
 
628
      if (v_count(8 downto 4) = reg_vcursor(4 downto 0)) then
629
        cursor_on_v <= '1';
630
      else
631
        cursor_on_v <= '0';
632
      end if;
633
 
634
      -- cursor_on is only active when on selected character
635
      blink_count <= std_logic_vector(unsigned(blink_count) + 1);
636
    end if;
637
 
638
  end process;
639
 
640
  -- video_on is high only when RGB data is displayed
641
  vga_hsync_o <= horiz_sync;
642
  vga_vsync_o <= vert_sync;
643
  video_on1   <= video_on_H and video_on_V;
644
  cursor_on1  <= cursor_on_h and cursor_on_v;
645
 
646
--
647
-- Here to look up character ROM
648
-- This will take one clock cycle
649
-- and should be performed on h_count = "111"
650
--
651
  char_addr(10 downto 4) <= vga_data_out(6 downto 0);
652
  char_addr(3 downto 0)  <= v_count(3 downto 0);
653
 
654
end RTL;

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