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[/] [System09/] [trunk/] [rtl/] [VHDL/] [vdu8_bert.vhd] - Blame information for rev 95

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Line No. Rev Author Line
1 19 dilbert57
-- ---------------------------------------------------
2
-- Video Display terminal
3
-- ---------------------------------------------------
4
-- John Kent
5
-- 3th September 2004
6
-- Assumes a pixel clock input of 50 MHz
7
-- Generates a 12.5MHz CPU Clock output
8
--
9
-- Display Format is:
10
-- 80 characters across by 25 characters down.
11
-- 8 horizontal pixels / character
12
-- 16 vertical scan lines / character (2 scan lines/row)
13
--
14
-- Modified by Bert Cuzeau for compliance and code cleanliness
15
-- The effort is not over.
16
-- There are still signal initialized, which is BAD.
17
 
18
Library IEEE;
19
  use IEEE.std_logic_1164.all;
20
  use IEEE.numeric_std.all;
21
 
22
Entity vdu8 is
23
  port(
24
    -- control register interface
25
    vdu_clk_in   : in  std_logic;       -- 50MHz  System clock
26
    cpu_clk_out  : out std_logic;       -- 12.5 MHz CPU Clock
27
    vdu_rst      : in  std_logic;
28
    vdu_cs       : in  std_logic;
29
    vdu_rw       : in  std_logic;
30
    vdu_addr     : in  std_logic_vector(2 downto 0);
31
    vdu_data_in  : in  std_logic_vector(7 downto 0);
32
    vdu_data_out : out std_logic_vector(7 downto 0);
33
 
34
    -- vga port connections
35
    vga_red_o   : out std_logic;
36
    vga_green_o : out std_logic;
37
    vga_blue_o  : out std_logic;
38
    vga_hsync_o : out std_logic;
39
    vga_vsync_o : out std_logic
40
    );
41
end vdu8;
42
 
43
Architecture RTL of vdu8 is
44
 
45
  --
46
  -- Synchronisation constants
47
  --
48
  constant HOR_DISP_END : integer := 639;  -- Last horizontal pixel displayed
49
  constant HOR_SYNC_BEG : integer := 679;  -- Start of horizontal synch pulse
50
  constant HOR_SYNC_END : integer := 775;  -- End of Horizontal Synch pulse
51
  constant HOR_SCAN_END : integer := 799;  -- Last pixel in scan line
52
  constant HOR_DISP_CHR : integer := 80;  -- Number of characters displayed per row
53
 
54
  constant VER_DISP_END : integer := 399;  -- last row displayed
55
  constant VER_SYNC_BEG : integer := 413;  -- start of vertical synch pulse
56
  constant VER_SYNC_END : integer := 414;  -- end of vertical synch pulse
57
  constant VER_SCAN_END : integer := 450;  -- Last scan row in the frame
58
  constant VER_DISP_CHR : integer := 25;  -- Number of character rows displayed
59
 
60
  signal horiz_sync    : std_logic := '1';
61
  signal vert_sync     : std_logic := '1';
62
  signal cursor_on_v   : std_logic;
63
  signal cursor_on_h   : std_logic;
64
  signal video_on_v    : std_logic := '0';
65
  signal video_on_h    : std_logic := '0';
66
  signal h_count       : std_logic_vector(9 downto 0) := (others=>'0');
67
  signal v_count       : std_logic_vector(8 downto 0) := (others=>'0');  -- 0 to VER_SCAN_END
68
  signal blink_count   : std_logic_vector(22 downto 0):= (others=>'1');
69
  --
70
  -- Character generator ROM
71
  --
72
  signal char_addr     : std_logic_vector(10 downto 0);
73
  signal char_data_out : std_logic_vector(7 downto 0);
74
 
75
  --
76
  -- Control Registers
77
  --
78
  signal reg_character : std_logic_vector(7 downto 0);
79
  signal reg_colour    : std_logic_vector(7 downto 0);
80
  signal reg_hcursor   : std_logic_vector(6 downto 0);   -- 80 columns
81
  signal reg_vcursor   : std_logic_vector(4 downto 0);   -- 25 rows
82
  signal reg_voffset   : std_logic_vector(4 downto 0);   -- 25 rows
83
  --
84
  -- Video Shift register
85
  --
86
  signal vga_shift     : std_logic_vector(7 downto 0);
87
  signal vga_fg_colour : std_logic_vector(2 downto 0);
88
  signal vga_bg_colour : std_logic_vector(2 downto 0);
89
  signal cursor_on     : std_logic;
90
  signal cursor_on1    : std_logic;
91
  signal video_on      : std_logic := '0';
92
  signal video_on1     : std_logic := '0';
93
  signal video_on2     : std_logic := '0';
94
  --
95
  -- vga character ram access bus
96
  --
97
  signal col_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
98
  signal row_addr      : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 -1)
99
  signal col1_addr     : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
100
  signal row1_addr     : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 - 1)
101
  signal hor_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
102
  signal ver_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 124
103
  signal vga0_cs       : std_logic;
104
  signal vga0_rw       : std_logic;
105
  signal vga1_cs       : std_logic;
106
  signal vga1_rw       : std_logic;
107
  signal vga2_cs       : std_logic;
108
  signal vga2_rw       : std_logic;
109
  signal vga_cs        : std_logic;
110
  signal vga_rw        : std_logic;
111
  signal vga_addr      : std_logic_vector(10 downto 0) := (others=>'0');  -- 2K byte character buffer
112
  signal vga_data_out  : std_logic_vector(7 downto 0);
113
  signal attr_data_out : std_logic_vector(7 downto 0);
114
  --
115
  -- Character write handshake signals
116
  --
117
  signal req_write     : std_logic;     -- request character write
118
  signal ack_write     : std_logic;
119
  --
120
  -- Clock divider
121
  --
122
  signal clk_count     : unsigned(1 downto 0);
123
  signal vdu_clk       : std_logic;
124
 
125
  --
126
  -- Slice character gen
127
  --
128
  --
129
  -- block Ram Character gen
130
  --
131
  component char_rom
132
    port (
133
      clk   : in  std_logic;
134
      addr  : in  std_logic_vector (10 downto 0);
135
      rdata : out std_logic_vector (7 downto 0)
136
      );
137
  end component;
138
 
139
  component ram_2k
140
    port (
141
      clk   : in  std_logic;
142
      rst   : in  std_logic;
143
      cs    : in  std_logic;
144
      r_wn  : in  std_logic;
145
      addr  : in  std_logic_vector (10 downto 0);
146
      wdata : in  std_logic_vector (7 downto 0);
147
      rdata : out std_logic_vector (7 downto 0)
148
      );
149
  end component;
150
 
151
begin
152
 
153
--
154
-- instantiate Character generator ROM
155
--
156
vdu_char_rom : char_rom port map(
157
    clk   => vdu_clk,
158
    addr  => char_addr,
159
    rdata => char_data_out
160
    );
161
 
162
--
163
-- Character buffer RAM
164
--
165
char_buff_ram : ram_2k port map(
166
    clk   => vdu_clk,
167
    rst   => vdu_rst,
168
    cs    => vga_cs,
169
    r_wn  => vga_rw,
170
    addr  => vga_addr,
171
    wdata => reg_character,
172
    rdata => vga_data_out
173
    );
174
 
175
--
176
-- Attribute buffer RAM
177
--
178
  attr_buff_ram : ram_2k port map(
179
    clk   => vdu_clk,
180
    rst   => vdu_rst,
181
    cs    => vga_cs,
182
    r_wn  => vga_rw,
183
    addr  => vga_addr,
184
    wdata => reg_colour,
185
    rdata => attr_data_out
186
    );
187
 
188
-----------------------
189
-- vdu_clk_buffer : BUFG port map (i => clk_count(0), o => vdu_clk );
190
-- cpu_clk_buffer : BUFG port map (i => clk_count(1), o => cpu_clk_out );
191
  vdu_clk     <= clk_count(0);          -- <<<< modif ALSE B. Cuzeau
192
  cpu_clk_out <= clk_count(1);          -- <<<< modif ALSE B. Cuzeau
193
-----------------------
194
 
195
--
196
-- Clock divider
197
-- Assumes 50 MHz system clock
198
-- 25MHz pixel clock
199
-- 12.5MHz CPU clock
200
--
201
  vga_clock : process(vdu_clk_in, vdu_rst)
202
  begin
203
    if vdu_rst = '1' then
204
      clk_count <= "00";
205
    elsif vdu_clk_in'event and vdu_clk_in = '0' then
206
      clk_count <= clk_count + 1;
207
    end if;
208
  end process;
209
 
210
--
211
-- CPU Write interface
212
--
213
  vga_cpu_write : process(vdu_clk, vdu_rst)
214
  begin
215
    if vdu_rst = '1' then
216
      reg_character <= "00000000";
217
      reg_colour    <= "00000111";
218
      reg_hcursor   <= "0000000";
219
      reg_vcursor   <= "00000";
220
      reg_voffset   <= "00000";
221
      req_write     <= '0';
222
 
223
    elsif vdu_clk'event and vdu_clk = '0' then
224
      if (vdu_cs = '1') and (vdu_rw = '0') then
225
        case vdu_addr is
226
          when "000" =>
227
            reg_character <= vdu_data_in;
228
            req_write     <= '1';
229
          when "001" =>
230
            reg_colour    <= vdu_data_in;
231
          when "010" =>
232
            reg_hcursor   <= vdu_data_in(6 downto 0);
233
          when "011" =>
234
            reg_vcursor   <= vdu_data_in(4 downto 0);
235
          when others =>
236
            reg_voffset   <= vdu_data_in(4 downto 0);
237
        end case;
238
      else
239
 
240
        if (req_write = '1') and (ack_write = '1') then
241
          req_write <= '0';
242
        else
243
          req_write <= req_write;
244
        end if;
245
 
246
      end if;
247
    end if;
248
  end process;
249
--
250
-- CPU Read interface
251
--
252
  vga_cpu_read : process(vdu_addr, vdu_cs,
253
                          reg_character, reg_colour,
254
                          reg_hcursor, reg_vcursor, reg_voffset)
255
  begin
256
    case vdu_addr is
257
      when "000" =>
258
        vdu_data_out <= reg_character;
259
      when "001" =>
260
        vdu_data_out <= reg_colour;
261
      when "010" =>
262
        vdu_data_out <= "0" & reg_hcursor;
263
      when "011" =>
264
        vdu_data_out <= "000" & reg_vcursor;
265
      when others =>
266
        vdu_data_out <= "000" & reg_voffset;
267
    end case;
268
  end process;
269
 
270
--
271
-- Video memory access
272
--
273
  vga_addr_proc : process(vdu_clk, vdu_rst)
274
  begin
275
 
276
    if vdu_rst = '1' then
277
      vga0_cs   <= '0';
278
      vga0_rw   <= '1';
279
      row_addr  <= "000000";
280
      col_addr  <= "0000000";
281
      --
282
      vga1_cs   <= '0';
283
      vga1_rw   <= '1';
284
      row1_addr <= "000000";
285
      col1_addr <= "0000000";
286
      --
287
      vga2_cs   <= '0';
288
      vga2_rw   <= '1';
289
      ver_addr  <= "0000000";
290
      hor_addr  <= "0000000";
291
      --
292
      vga_cs    <= '0';
293
      vga_rw    <= '1';
294
      vga_addr  <= "00000000000";
295
 
296
    elsif vdu_clk'event and vdu_clk = '0' then
297
      --
298
      -- on h_count = 0 initiate character write.
299
      -- all other cycles are reads.
300
      --
301
      case h_count(2 downto 0) is
302
        when "000" =>                   -- pipeline character write
303
          vga0_cs  <= req_write;
304
          vga0_rw  <= '0';
305
          col_addr <= reg_hcursor(6 downto 0);
306
          row_addr <= unsigned("0" & reg_vcursor(4 downto 0)) + unsigned("0" & reg_voffset(4 downto 0));
307
        when others =>                  -- other 6 cycles free
308
          vga0_cs  <= '1';
309
          vga0_rw  <= '1';
310
          col_addr <= h_count(9 downto 3);
311
          row_addr <= unsigned("0" & v_count(8 downto 4)) + unsigned("0" & reg_voffset(4 downto 0));
312
      end case;
313
      --
314
      -- on vdu_clk + 1 round off row address
315
      --
316
      vga1_cs <= vga0_cs;
317
      vga1_rw <= vga0_rw;
318
      if row_addr < VER_DISP_CHR then
319
        row1_addr <= row_addr;
320
      else
321
        row1_addr <= row_addr - VER_DISP_CHR;
322
      end if;
323
      col1_addr <= col_addr;
324
      --
325
      -- on vdu_clk + 2 calculate vertical address
326
      --
327
      vga2_cs   <= vga1_cs;
328
      vga2_rw   <= vga1_rw;
329
      ver_addr  <= std_logic_vector(unsigned("00" & row1_addr(4 downto 0)) + unsigned(row1_addr(4 downto 0) & "00"));
330
      hor_addr  <= col1_addr;
331
      --
332
      -- on vdu_clk + 3 calculate memory address
333
      --
334
      vga_cs    <= vga2_cs;
335
      vga_rw    <= vga2_rw;
336
      vga_addr  <= std_logic_vector(unsigned("0000" & hor_addr) + unsigned(ver_addr & "0000"));
337
    end if;
338
  end process;
339
--
340
-- Video shift register
341
--
342
  vga_shift_proc : process( vdu_clk, vdu_rst)
343
  begin
344
    if vdu_rst = '1' then
345
      ack_write     <= '0';
346
      video_on2     <= '0';
347
      video_on      <= '0';
348
      cursor_on     <= '0';
349
      vga_bg_colour <= "000";
350
      vga_fg_colour <= "111";
351
      vga_shift     <= "00000000";
352
      vga_red_o     <= '0';
353
      vga_green_o   <= '0';
354
      vga_blue_o    <= '0';
355
      -- Put all video signals through DFFs to elminate any delays that cause a blurry image
356
 
357
    elsif vdu_clk'event and vdu_clk = '0' then
358
      -- Character Data valid on 1 count
359
      if h_count(2 downto 0) = "000" then
360
        if (req_write = '1') and (ack_write = '0') then
361
          ack_write <= '1';
362
        elsif (req_write = '0') and (ack_write = '1') then
363
          ack_write <= '0';
364
        else
365
          ack_write <= ack_write;
366
        end if;
367
        video_on2     <= video_on1;
368
        video_on      <= video_on2;
369
        cursor_on     <= (cursor_on1 or attr_data_out(3)) and blink_count(22);
370
        vga_fg_colour <= attr_data_out(2 downto 0);
371
        vga_bg_colour <= attr_data_out(6 downto 4);
372
        if attr_data_out(7) = '0' then
373
          vga_shift <= char_data_out;
374
        else
375
          case v_count(3 downto 2) is
376
            when "00" =>
377
              vga_shift(7 downto 4) <= vga_data_out(0) & vga_data_out(0) & vga_data_out(0) & vga_data_out(0);
378
              vga_shift(3 downto 0) <= vga_data_out(1) & vga_data_out(1) & vga_data_out(1) & vga_data_out(1);
379
            when "01" =>
380
              vga_shift(7 downto 4) <= vga_data_out(2) & vga_data_out(2) & vga_data_out(2) & vga_data_out(2);
381
              vga_shift(3 downto 0) <= vga_data_out(3) & vga_data_out(3) & vga_data_out(3) & vga_data_out(3);
382
            when "10" =>
383
              vga_shift(7 downto 4) <= vga_data_out(4) & vga_data_out(4) & vga_data_out(4) & vga_data_out(4);
384
              vga_shift(3 downto 0) <= vga_data_out(5) & vga_data_out(5) & vga_data_out(5) & vga_data_out(5);
385
            when others =>
386
              vga_shift(7 downto 4) <= vga_data_out(6) & vga_data_out(6) & vga_data_out(6) & vga_data_out(6);
387
              vga_shift(3 downto 0) <= vga_data_out(7) & vga_data_out(7) & vga_data_out(7) & vga_data_out(7);
388
          end case;
389
        end if;
390
      else
391
        vga_shift <= vga_shift(6 downto 0) & '0';
392
      end if;
393
 
394
      --
395
      -- Colour mask is
396
      --  7  6  5  4  3  2  1  0
397
      --  X BG BB BR  X FG FB FR
398
      --
399
      if vga_shift(7) = (not cursor_on) then
400
        vga_red_o   <= video_on and vga_fg_colour(0);
401
        vga_green_o <= video_on and vga_fg_colour(1);
402
        vga_blue_o  <= video_on and vga_fg_colour(2);
403
      else
404
        vga_red_o   <= video_on and vga_bg_colour(0);
405
        vga_green_o <= video_on and vga_bg_colour(1);
406
        vga_blue_o  <= video_on and vga_bg_colour(2);
407
      end if;
408
    end if;
409
  end process;
410
 
411
 
412
--
413
-- Sync generator & timing process
414
-- Generate Horizontal and Vertical Timing Signals for Video Signal
415
--
416
  vga_sync : process(vdu_clk)
417
  begin
418
    if vdu_clk'event and vdu_clk = '0' then
419
      --
420
      -- H_count counts pixels (640 + extra time for sync signals)
421
      --
422
      --  Horiz_sync  -----------------------------__________--------
423
      --  H_count       0                640      659       755    799
424
      --
425
      if unsigned(h_count) = HOR_SCAN_END then
426
        h_count <= (others=>'0');
427
      else
428
        h_count <= std_logic_vector(unsigned(h_count) + 1);
429
      end if;
430
--
431
-- Generate Horizontal Sync Signal using H_count
432
--
433
      if unsigned(h_count) = HOR_SYNC_BEG then
434
        horiz_sync <= '0';
435
      elsif unsigned(h_count) = HOR_SYNC_END then
436
        horiz_sync <= '1';
437
      else
438
        horiz_sync <= horiz_sync;
439
      end if;
440
--
441
-- V_count counts rows of pixels
442
-- 400 lines + extra time for sync signals
443
-- 25 rows * 16 scan lines
444
--
445
--  Vert_sync      ---------------------------------_______------------
446
--  V_count         0                       400    413     414        444
447
--
448
      if (unsigned(v_count) = VER_SCAN_END) and (unsigned(h_count) = HOR_SCAN_END) then
449
        v_count <= "000000000";
450
      elsif unsigned(h_count) = HOR_SYNC_END then
451
        v_count <= std_logic_vector(unsigned(v_count) + 1);
452
      end if;
453
--
454
-- Generate Vertical Sync Signal using V_count
455
--
456
      if unsigned(v_count) = VER_SYNC_BEG then
457
        vert_sync <= '0';
458
      elsif unsigned(v_count) = VER_SYNC_END then
459
        vert_sync <= '1';
460
      else
461
        vert_sync <= vert_sync;
462
      end if;
463
 
464
-- Generate Video on Screen Signals for Pixel Data
465
      if unsigned(h_count) = HOR_SCAN_END then
466
        video_on_h <= '1';
467
      elsif unsigned(h_count) = HOR_DISP_END then
468
        video_on_h <= '0';
469
      else
470
        video_on_h <= video_on_h;
471
      end if;
472
 
473
      if unsigned(v_count) = VER_SCAN_END then
474
        video_on_v <= '1';
475
      elsif unsigned(v_count) = VER_DISP_END then
476
        video_on_v <= '0';
477
      else
478
        video_on_v <= video_on_v;
479
      end if;
480
 
481
 
482
      if h_count(9 downto 3) = reg_hcursor(6 downto 0) then
483
        cursor_on_h <= '1';
484
      else
485
        cursor_on_h <= '0';
486
      end if;
487
 
488
      if (v_count(8 downto 4) = reg_vcursor(4 downto 0)) then
489
        cursor_on_v <= '1';
490
      else
491
        cursor_on_v <= '0';
492
      end if;
493
 
494
      -- cursor_on is only active when on selected character
495
      blink_count <= std_logic_vector(unsigned(blink_count) + 1);
496
    end if;
497
 
498
  end process;
499
 
500
  -- video_on is high only when RGB data is displayed
501
  vga_hsync_o <= horiz_sync;
502
  vga_vsync_o <= vert_sync;
503
  video_on1   <= video_on_H and video_on_V;
504
  cursor_on1  <= cursor_on_h and cursor_on_v;
505
 
506
--
507
-- Here to look up character ROM
508
-- This will take one clock cycle
509
-- and should be performed on h_count = "111"
510
--
511
  char_addr(10 downto 4) <= vga_data_out(6 downto 0);
512
  char_addr(3 downto 0)  <= v_count(3 downto 0);
513
 
514
end RTL;

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