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[/] [System09/] [trunk/] [rtl/] [VHDL/] [vdu8_new.vhd] - Blame information for rev 159

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Line No. Rev Author Line
1 118 dilbert57
--===========================================================================--
2
--                                                                           --
3
--  vdu8_new.vhd - Synthesizable Colour Video Display Unit for System09      --
4
--                                                                           --
5
--===========================================================================--
6 65 davidgb
--
7 118 dilbert57
--  File name      : vdu8_new.vhd
8 65 davidgb
--
9 118 dilbert57
--  Purpose        : Implements a text based Colour Video Display Unit for System09
10
--                   Supports 2KByte Text buffer and 2KByte Attribute memory
11
--                   Displays 80 characters across by 25 character rows
12
--                   Characters are 8 pixels across x 16 lines down.
13
--                   Character attribute bita for foreground and backgrond colour
14
--                   1 bit for each Blue Green and Red signal
15
--                   Supports 2 x 8 chunky graphics character mode.
16
--                   Uses Generic arguments for setting the video synchronization timing.
17
--                   (I'm not sure what is "new" about this version.)
18
--                  
19
--  Dependencies   : ieee.Std_Logic_1164
20
--                   ieee.std_logic_arith
21
--                   ieee.std_logic_unsigned
22
--                   ieee.numeric_std
23
--                   unisim.vcomponents
24 65 davidgb
--
25 118 dilbert57
--  Uses           : ram_2k (ram2k_b16.vhd)             2KByte Character & Attribute buffer
26
--                   char_rom (char_rom2k_b16.vhd)      2KByte Character Generator ROM 
27
--
28
--  Author         : John E. Kent
29
--
30
--  Email          : dilbert57@opencores.org      
31
--
32
--  Web            : http://opencores.org/project,system09
33
--
34
--  Description    : Display Timing:
35
--                       800 pixels / line
36
--                       446 lines / frame
37
--                       None interlaced
38
--                       25MHz pixel clock implies 
39
--                       31.25 KHz line rate
40
--                       70.067 Hz frame rate   
41
--                       Timing settable by generics.
42
--
43
--                   Display Size:
44
--                       80 characters across
45
--                       25 characters down.
46
--
47
--                   Character Size:
48
--                        8 horizontal pixels across
49
--                       16 vertical scan lines down (2 scan lines/row)
50
--
51
--                   Registers:
52
--                   Base + 0 ASCII character register
53
--                            Writing to this register writes an 8 bit byte 
54
--                            into the text buffer at the specified cursor position
55
--                            Text Mode: ASCII Character (0 to 127)
56
--                            Chunky Graphics Mode: B0 B1 (0 to 255)
57
--                                                  B2 B3
58
--                                                  B4 B5
59
--                                                  B6 B7
60
--                   Base + 1 Attibute bit (0 to 255)
61
--                            Writing to the register writes an 8 bit byte 
62
--                            into the attribute buffer at the specified cursor position
63
--                            B7 - 0 => Text Mode / 1 => Chunky Graphics Mode
64
--                            B6 - 1 => Character Background Blue
65
--                            B5 - 1 => Character Background Green
66
--                            B4 - 1 => Character Background Red
67
--                            B3 - 1 => Character Background & Foreground Alternates
68
--                            B2 - 1 => Character Foreground Blue
69
--                            B1 - 1 => Character Foreground Green
70
--                            B0 - 1 => Character Foreground Red
71
--                   Base + 2 Cursor Horizontal Position (0 to 79)
72
--                   Base + 3 Cusror Vertical Position (0 to 24)
73
--                   Base + 4 Vertical Scroll Offset (0 to 24)
74
--                            Scrolls the display up by the specified number of character rows
75
--
76
--
77
--  Video Timing :
78
--
79
--  Horizontal 800 Pixels/ 25MHz Pixel Clock = 32usec Line period = 31.25 KHz Line Frequency
80
--  /--------------------------\_____________/---------------\______________/
81
--      640 Pixels Display       16 Pixel FP    96 Pixel HS     48 Pixel BP
82
--    
83
--      VGA_CLK_FREQ           : integer := 25000000; -- HZ
84
--           VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
85
--           VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
86
--           VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
87
--           VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS 0.32us
88
--           VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
89
--
90
--  Vertical 446 Lines * 32 usec Line rate = 14.272ms Frame Period = 70.07Hz Frame frequency  
91
--  /---------------------------\____________/---------------\______________/
92
--      400 Line Display          10 Line FP     2 Line VS      34 Line BP
93
--
94
--           VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
95
--           VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
96
--           VGA_VER_BACK_PORCH     : integer := 34; -- LINES 1.088ms
97
--           VGA_LIN_PER_CHAR       : integer := 16; -- LINES 0.512ms
98
--           VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
99
--
100
--  Copyright (C) 2003 - 2010 John Kent
101
--
102
--  This program is free software: you can redistribute it and/or modify
103
--  it under the terms of the GNU General Public License as published by
104
--  the Free Software Foundation, either version 3 of the License, or
105
--  (at your option) any later version.
106
--
107
--  This program is distributed in the hope that it will be useful,
108
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
109
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
110
--  GNU General Public License for more details.
111
--
112
--  You should have received a copy of the GNU General Public License
113
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
114
--
115
--===========================================================================--
116
--                                                                           --
117
--                              Revision  History                            --
118
--                                                                           --
119
--===========================================================================--
120
--
121
-- Version Author      Date        Changes
122 65 davidgb
--
123 118 dilbert57
-- 0.1     John Kent   2004-09-03  Initial release
124
--
125
-- 0.2     Bert Cuzeau 2007-01-16  Modified by for compliance and code cleanliness
126
--                                 The effort is not over.
127
--                                 There are still signal initialized, which is BAD.
128
--
129
-- 0.3     John Kent   2007-02-07  Added generics for VGA Timing
130
--
131
-- 0.4     John Kent   2010-06-16  Added GPL notice. Updated description
132
--                                 I'm not sure what is "new" about this version
133
--
134 65 davidgb
 
135
Library IEEE;
136
   use ieee.std_logic_1164.all;
137 118 dilbert57
   use ieee.std_logic_arith.all;
138
   use ieee.std_logic_unsigned.all;
139 65 davidgb
   use ieee.numeric_std.all;
140
library unisim;
141
   use unisim.vcomponents.all;
142
 
143
Entity vdu8 is
144
  generic(
145 118 dilbert57
        VGA_CLK_FREQ           : integer := 25000000; -- HZ
146
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
147
             VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
148
             VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us
149
             VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us
150
             VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us
151
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
152
             VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
153
             VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
154
             VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
155
             VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
156 65 davidgb
  );
157
  port(
158
    -- control register interface
159
    vdu_clk      : in  std_logic;       -- 12.5/25 MHz CPU Clock
160
    vdu_rst      : in  std_logic;
161
    vdu_cs       : in  std_logic;
162
    vdu_rw       : in  std_logic;
163
    vdu_addr     : in  std_logic_vector(2 downto 0);
164
    vdu_data_in  : in  std_logic_vector(7 downto 0);
165
    vdu_data_out : out std_logic_vector(7 downto 0);
166
 
167
    -- vga port connections
168
    vga_clk      : in  std_logic;       -- 25MHz clock
169
    vga_red_o    : out std_logic;
170
    vga_green_o  : out std_logic;
171
    vga_blue_o   : out std_logic;
172
    vga_hsync_o  : out std_logic;
173
    vga_vsync_o  : out std_logic
174
    );
175
end vdu8;
176
 
177
Architecture RTL of vdu8 is
178
  --
179
  -- Synchronisation constants
180
  --
181
  -- Displayed Characters per row
182
  constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
183
  -- Last horizontal pixel displayed
184 118 dilbert57
  constant HOR_DISP_END : integer := HOR_DISP_CHR * VGA_HOR_CHAR_PIXELS - 1;
185 65 davidgb
  -- Start of horizontal synch pulse
186 118 dilbert57
  constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_FRONT_PORCH;
187 65 davidgb
  -- End of Horizontal Synch pulse
188
  constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
189
  -- Last pixel in scan line
190 118 dilbert57
  constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_BACK_PORCH;
191 65 davidgb
 
192
  -- Displayed Characters per Column
193
  constant VER_DISP_CHR   : integer := VGA_VER_CHARS;
194
  -- last row displayed
195 118 dilbert57
  constant VER_DISP_END   : integer := VER_DISP_CHR * VGA_VER_CHAR_LINES - 1;
196 65 davidgb
  -- start of vertical synch pulse
197 118 dilbert57
  constant VER_SYNC_BEG   : integer := VER_DISP_END + VGA_VER_FRONT_PORCH;
198 65 davidgb
  -- end of vertical synch pulse
199
  constant VER_SYNC_END   : integer := VER_SYNC_BEG + VGA_VER_SYNC;
200
  -- Last scan row in the frame
201 118 dilbert57
  constant VER_SCAN_END   : integer := VER_SYNC_END + VGA_VER_BACK_PORCH;
202
 
203
  constant BLINK_PERIOD   : integer := 500; -- Blink Rate in msec
204 65 davidgb
  constant BLINK_RATE     : integer := BLINK_PERIOD * (VGA_CLOCK_FREQUENCY/1000);
205
 
206
  signal vga_rst       : std_logic;
207
  signal horiz_sync    : std_logic := '0';
208
  signal vert_sync     : std_logic := '0';
209
  signal cursor_on_v   : std_logic := '0';
210
  signal cursor_on_h   : std_logic := '0';
211
  signal video_on_v    : std_logic := '0';
212
  signal video_on_h    : std_logic := '0';
213
  signal h_count       : natural range 0 to HOR_SCAN_END := 0;
214 118 dilbert57
  signal v_count       : natural range 0 to VER_SCAN_END := 0;
215 65 davidgb
  signal p_count       : natural range 0 to VGA_PIXELS_PER_CHAR-1 := 0;
216
  signal l_count       : std_logic_vector(3 downto 0) := "0000";
217
  signal c_count       : std_logic_vector(6 downto 0) := "0000000";
218 118 dilbert57
  signal r_count       : std_logic_vector(5 downto 0) := "000000";
219 65 davidgb
  signal blink_count   : natural range 0 to BLINK_RATE := 0;
220
  --
221
  -- Character generator ROM
222
  --
223
  signal char_addr     : std_logic_vector(10 downto 0);
224
  signal char_data_out : std_logic_vector(7 downto 0);
225
 
226
  --
227
  -- Control Registers
228
  --
229
  signal reg_character : std_logic_vector(7 downto 0);
230
  signal reg_colour    : std_logic_vector(7 downto 0);
231
  signal reg_hcursor   : std_logic_vector(6 downto 0);   -- 80 columns
232
  signal reg_vcursor   : std_logic_vector(4 downto 0);   -- 25 rows
233
  signal reg_voffset   : std_logic_vector(4 downto 0);   -- 25 rows
234
  --
235
  -- Video Shift register
236
  --
237
  signal vga_shift     : std_logic_vector(7 downto 0);
238
  signal vga_fg_colour : std_logic_vector(2 downto 0);
239
  signal vga_bg_colour : std_logic_vector(2 downto 0);
240
  signal cursor_on     : std_logic := '0';
241
  signal cursor_on1    : std_logic := '0';
242
  signal video_on      : std_logic := '0';
243
  signal video_on1     : std_logic := '0';
244
  signal video_on2     : std_logic := '0';
245
  --
246
  -- vga character ram access bus
247
  --
248
  signal col_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
249
  signal row_addr      : std_logic_vector(5 downto 0) := (others=>'0'); -- 0 to 49 (25 * 2 -1)
250
  signal col1_addr     : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
251
  signal row1_addr     : std_logic_vector(5 downto 0) := (others=>'0'); -- 0 to 49 (25 * 2 - 1)
252
  signal hor_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
253
  signal ver_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 124
254
  signal vga0_cs       : std_logic;
255
  signal vga0_rw       : std_logic;
256
  signal vga1_cs       : std_logic;
257
  signal vga1_rw       : std_logic;
258
  signal vga2_cs       : std_logic;
259
  signal vga2_rw       : std_logic;
260
  signal vga_cs        : std_logic;
261
  signal vga_rw        : std_logic;
262
  signal vga_addr      : std_logic_vector(10 downto 0) := (others=>'0');  -- 2K byte character buffer
263
  signal vga_data_out  : std_logic_vector(7 downto 0);
264
  signal attr_data_out : std_logic_vector(7 downto 0);
265 118 dilbert57
 
266 65 davidgb
  --
267
  -- Character write handshake signals
268
  --
269
  signal req_write     : std_logic;     -- request character write
270
  signal ack_write     : std_logic;
271
 
272
  --
273
  -- Block Ram Character gen
274
  --
275
  component char_rom
276
    port (
277
      clk   : in  std_logic;
278
      rst   : in  std_logic;
279
      cs    : in  std_logic;
280
      rw    : in  std_logic;
281
      addr  : in  std_logic_vector (10 downto 0);
282
      wdata : in std_logic_vector (7 downto 0);
283
      rdata : out std_logic_vector (7 downto 0)
284
      );
285
  end component;
286
 
287
  component ram_2k
288
    port (
289
      clk   : in  std_logic;
290
      rst   : in  std_logic;
291
      cs    : in  std_logic;
292
      rw    : in  std_logic;
293
      addr  : in  std_logic_vector (10 downto 0);
294
      wdata : in  std_logic_vector (7 downto 0);
295
      rdata : out std_logic_vector (7 downto 0)
296
      );
297
  end component;
298
 
299
begin
300
 
301
--
302
-- instantiate Character generator ROM
303
--
304
vdu_char_rom : char_rom port map(
305
    clk   => vga_clk,
306
         rst   => vga_rst,
307
         cs    => '1',
308
         rw    => '1',
309
    addr  => char_addr,
310
    wdata => "00000000",
311
    rdata => char_data_out
312
    );
313
 
314
--
315
-- Character buffer RAM
316
--
317
char_buff_ram : ram_2k port map(
318
    clk   => vga_clk,
319
    rst   => vga_rst,
320
    cs    => vga_cs,
321
    rw    => vga_rw,
322
    addr  => vga_addr,
323
    wdata => reg_character,
324
    rdata => vga_data_out
325
    );
326
 
327
--
328
-- Attribute buffer RAM
329
--
330
  attr_buff_ram : ram_2k port map(
331
    clk   => vga_clk,
332
    rst   => vga_rst,
333
    cs    => vga_cs,
334
    rw    => vga_rw,
335
    addr  => vga_addr,
336
    wdata => reg_colour,
337
    rdata => attr_data_out
338
    );
339
 
340
--
341
-- CPU Write interface
342
--
343
  vga_cpu_write : process(vdu_clk, vdu_rst)
344
  begin
345
    if vdu_rst = '1' then
346
      reg_character <= "00000000";
347
      reg_colour    <= "00000111";
348
      reg_hcursor   <= "0000000";
349
      reg_vcursor   <= "00000";
350
      reg_voffset   <= "00000";
351
      req_write     <= '0';
352
 
353
    elsif falling_edge(vdu_clk) then
354
      if (vdu_cs = '1') and (vdu_rw = '0') then
355
        case vdu_addr is
356
          when "000" =>
357
            reg_character <= vdu_data_in;
358
            req_write     <= '1';
359
          when "001" =>
360
            reg_colour    <= vdu_data_in;
361
          when "010" =>
362
            reg_hcursor   <= vdu_data_in(6 downto 0);
363
          when "011" =>
364
            reg_vcursor   <= vdu_data_in(4 downto 0);
365
          when others =>
366
            reg_voffset   <= vdu_data_in(4 downto 0);
367
        end case;
368
      else
369
 
370
        if (req_write = '1') and (ack_write = '1') then
371
          req_write <= '0';
372
        else
373
          req_write <= req_write;
374
        end if;
375
 
376
      end if;
377
    end if;
378
  end process;
379
  --
380
  -- CPU Read interface
381
  --
382
  vga_cpu_read : process(vdu_addr, vdu_cs,
383
                         reg_character, reg_colour,
384
                         reg_hcursor, reg_vcursor, reg_voffset)
385
  begin
386
    case vdu_addr is
387
      when "000" =>
388
        vdu_data_out <= reg_character;
389
      when "001" =>
390
        vdu_data_out <= reg_colour;
391
      when "010" =>
392
        vdu_data_out <= "0" & reg_hcursor;
393
      when "011" =>
394
        vdu_data_out <= "000" & reg_vcursor;
395
      when others =>
396
        vdu_data_out <= "000" & reg_voffset;
397
    end case;
398
  end process;
399
 
400
  --
401
  -- Video memory access
402
  --
403
  vga_addr_proc : process(vga_clk, vga_rst)
404
  begin
405
 
406
    if vga_rst = '1' then
407
      vga0_cs   <= '0';
408
      vga0_rw   <= '1';
409
      row_addr  <= "000000";
410
      col_addr  <= "0000000";
411
      --
412
      vga1_cs   <= '0';
413
      vga1_rw   <= '1';
414
      row1_addr <= "000000";
415
      col1_addr <= "0000000";
416
      --
417
      vga2_cs   <= '0';
418
      vga2_rw   <= '1';
419
      ver_addr  <= "0000000";
420
      hor_addr  <= "0000000";
421
      --
422
      vga_cs    <= '0';
423
      vga_rw    <= '1';
424
      vga_addr  <= "00000000000";
425
 
426
    elsif falling_edge(vga_clk) then
427
      --
428
      -- on h_count = 0 initiate character write.
429
      -- all other cycles are reads.
430
      --
431
      case p_count is
432
        when 0 =>                   -- pipeline character write
433
          vga0_cs  <= req_write;
434
          vga0_rw  <= '0';
435
          col_addr <= reg_hcursor(6 downto 0);
436
          row_addr <= ("0" & reg_vcursor(4 downto 0)) + ("0" & reg_voffset(4 downto 0));
437
        when others =>                  -- other 7 cycles free
438
          vga0_cs  <= '1';
439
          vga0_rw  <= '1';
440
          col_addr <= c_count;
441
          row_addr <= r_count + ("0" & reg_voffset(4 downto 0));
442 118 dilbert57
      end case;
443 65 davidgb
 
444
      --
445
      -- on vga_clk + 1 round off row address
446
      --
447
      vga1_cs <= vga0_cs;
448 118 dilbert57
      vga1_rw <= vga0_rw;
449 65 davidgb
      if row_addr < VER_DISP_CHR then
450
        row1_addr <= row_addr;
451
      else
452
        row1_addr <= row_addr - VER_DISP_CHR;
453
      end if;
454
      col1_addr <= col_addr;
455
      --
456
      -- on vga_clk + 2 calculate vertical address
457
      --
458
      vga2_cs   <= vga1_cs;
459
      vga2_rw   <= vga1_rw;
460
      ver_addr  <= ("00" & row1_addr(4 downto 0)) + (row1_addr(4 downto 0) & "00");
461
      hor_addr  <= col1_addr;
462
      --
463
      -- on vga_clk + 3 calculate memory address
464
      --
465
      vga_cs    <= vga2_cs;
466
      vga_rw    <= vga2_rw;
467
      vga_addr  <= ("0000" & hor_addr) + (ver_addr & "0000");
468
    end if;
469
  end process;
470
--
471
-- Video shift register
472
--
473
  vga_shift_proc : process( vga_clk, vga_rst)
474
  begin
475
    if vga_rst = '1' then
476
      ack_write     <= '0';
477
      video_on2     <= '0';
478
      video_on      <= '0';
479
      cursor_on     <= '0';
480
      vga_bg_colour <= "000";
481
      vga_fg_colour <= "111";
482
      vga_shift     <= "00000000";
483
      vga_red_o     <= '0';
484
      vga_green_o   <= '0';
485
      vga_blue_o    <= '0';
486
      -- Put all video signals through DFFs to elminate any delays that cause a blurry image
487
 
488 118 dilbert57
    elsif falling_edge(vga_clk) then
489 65 davidgb
           --
490 118 dilbert57
      -- p_count = 0 load pixel shift register
491 65 davidgb
                --
492
      if p_count = 0 then
493
        if (req_write = '1') and (ack_write = '0') then
494
          ack_write <= '1';
495
        elsif (req_write = '0') and (ack_write = '1') then
496
          ack_write <= '0';
497
        else
498
          ack_write <= ack_write;
499 118 dilbert57
        end if;
500
 
501
                  --
502
                  -- Pipeline video enable
503 65 davidgb
                  --
504
        video_on2     <= video_on1;
505 118 dilbert57
        video_on      <= video_on2;
506
                  --
507
                  -- Blink Cursor
508
                  --
509 65 davidgb
                  if blink_count > (BLINK_RATE/2) then
510 118 dilbert57
           cursor_on  <= cursor_on1 or attr_data_out(3);
511
        else
512
                     cursor_on  <= '0';
513
        end if;
514
                  --
515
                  -- Set forground and background colours
516 65 davidgb
                  --
517
        vga_fg_colour <= attr_data_out(2 downto 0);
518 118 dilbert57
        vga_bg_colour <= attr_data_out(6 downto 4);
519
                  --
520
                  -- Attribute bit 7
521 65 davidgb
                  --   0 => text
522 118 dilbert57
                  --   1 => chunky graphics
523
                  --
524 65 davidgb
        if attr_data_out(7) = '0' then
525
          vga_shift <= char_data_out;
526
        else
527
          case l_count(3 downto 2) is
528
            when "00" =>
529
              vga_shift(7 downto 4) <= vga_data_out(0) & vga_data_out(0) & vga_data_out(0) & vga_data_out(0);
530
              vga_shift(3 downto 0) <= vga_data_out(1) & vga_data_out(1) & vga_data_out(1) & vga_data_out(1);
531
            when "01" =>
532
              vga_shift(7 downto 4) <= vga_data_out(2) & vga_data_out(2) & vga_data_out(2) & vga_data_out(2);
533
              vga_shift(3 downto 0) <= vga_data_out(3) & vga_data_out(3) & vga_data_out(3) & vga_data_out(3);
534
            when "10" =>
535
              vga_shift(7 downto 4) <= vga_data_out(4) & vga_data_out(4) & vga_data_out(4) & vga_data_out(4);
536
              vga_shift(3 downto 0) <= vga_data_out(5) & vga_data_out(5) & vga_data_out(5) & vga_data_out(5);
537
            when others =>
538
              vga_shift(7 downto 4) <= vga_data_out(6) & vga_data_out(6) & vga_data_out(6) & vga_data_out(6);
539
              vga_shift(3 downto 0) <= vga_data_out(7) & vga_data_out(7) & vga_data_out(7) & vga_data_out(7);
540
          end case;
541
        end if;
542 118 dilbert57
      else
543
                  --
544
                  -- p_count /= 0 shift out pixel shift register
545 65 davidgb
                  --
546
        vga_shift <= vga_shift(6 downto 0) & '0';
547
      end if;
548
 
549
      --
550
      -- Colour mask is
551
      --  7  6  5  4  3  2  1  0
552
      --  X BG BB BR  X FG FB FR
553
      --
554
      if vga_shift(7) = (not cursor_on) then
555
        vga_red_o   <= video_on and vga_fg_colour(0);
556
        vga_green_o <= video_on and vga_fg_colour(1);
557
        vga_blue_o  <= video_on and vga_fg_colour(2);
558
      else
559
        vga_red_o   <= video_on and vga_bg_colour(0);
560
        vga_green_o <= video_on and vga_bg_colour(1);
561
        vga_blue_o  <= video_on and vga_bg_colour(2);
562
      end if;
563
    end if;
564
  end process;
565
 
566
 
567
--
568
-- Sync generator & timing process
569
-- Generate Horizontal and Vertical Timing Signals for Video Signal
570
--
571
  vga_sync : process(vga_clk, vga_rst)
572 118 dilbert57
  begin
573
    if vga_rst = '1' then
574
        h_count     <= 0;
575
                  c_count     <= "0000000";
576 65 davidgb
                  p_count     <= 0;
577 118 dilbert57
        v_count     <= 0;
578
                  l_count     <= "0000";
579 65 davidgb
                  r_count     <= "000000";
580
        horiz_sync  <= '0';
581
        vert_sync   <= '0';
582
        video_on_h  <= '0';
583
        video_on_v  <= '0';
584
        cursor_on_h <= '0';
585
        cursor_on_v <= '0';
586 118 dilbert57
                  blink_count <= BLINK_RATE;
587 65 davidgb
    elsif falling_edge(vga_clk) then
588
      --
589
      -- H_count counts pixels (640 + extra time for sync signals)
590
      --
591
      --  Horiz_sync  -----------------------------__________--------
592
      --  H_count       0                640      659       755    799
593
      --
594
      if h_count = HOR_SCAN_END then
595 118 dilbert57
        h_count <= 0;
596
                  c_count <= "0000000";
597 65 davidgb
                  p_count <= 0;
598
      else
599 118 dilbert57
        h_count <= h_count + 1;
600
                  p_count <= p_count + 1;
601
                  if p_count = VGA_PIXELS_PER_CHAR-1 then
602
                    p_count <= 0;
603
                    c_count <= c_count + "0000001";
604 65 davidgb
                  end if;
605 118 dilbert57
      end if;
606 65 davidgb
 
607
      --
608
      -- V_count counts rows of pixels
609
      -- 400 lines + extra time for sync signals
610
      -- 25 rows * 16 scan lines
611
      --
612
      --  Vert_sync      ---------------------------------_______------------
613
      --  V_count         0                       400    413     414        444
614
      --
615
      if (v_count = VER_SCAN_END) and (h_count = HOR_SCAN_END) then
616 118 dilbert57
        v_count <= 0;
617
                  l_count <= "0000";
618 65 davidgb
                  r_count <= "000000";
619
      elsif h_count = HOR_SYNC_END then
620
        v_count <= v_count + 1;
621 118 dilbert57
        l_count <= l_count + "0001";
622
                  if l_count = VGA_LINES_PER_CHAR-1 then
623
                    l_count <= "0000";
624
                    r_count <= r_count + "000001";
625 65 davidgb
                  end if;
626 118 dilbert57
      end if;
627 65 davidgb
 
628
      --
629
      -- Generate Horizontal Sync Signal
630
      --
631
      if h_count = HOR_SYNC_BEG then
632
        horiz_sync <= '1';
633
      elsif h_count = HOR_SYNC_END then
634
        horiz_sync <= '0';
635
      end if;
636 118 dilbert57
 
637 65 davidgb
      --
638
      -- Generate Vertical Sync Signal
639
      --
640
      if v_count = VER_SYNC_BEG then
641
        vert_sync <= '1';
642
      elsif v_count = VER_SYNC_END then
643
        vert_sync <= '0';
644 118 dilbert57
      end if;
645 65 davidgb
 
646
                --
647 118 dilbert57
      -- Horizontal display enable
648 65 davidgb
                --
649
      if h_count = 0 then
650
        video_on_h <= '1';
651
      elsif h_count = HOR_DISP_END then
652
        video_on_h <= '0';
653
      end if;
654
 
655
                --
656 118 dilbert57
      -- Verical display enable
657 65 davidgb
                --
658
      if v_count = 0 then
659
        video_on_v <= '1';
660
      elsif v_count = VER_DISP_END then
661
        video_on_v <= '0';
662
      end if;
663
 
664 118 dilbert57
                --
665
                -- Horizontal cursor on
666 65 davidgb
                --
667
      if c_count = reg_hcursor(6 downto 0) then
668
        cursor_on_h <= '1';
669
      else
670
        cursor_on_h <= '0';
671
      end if;
672 118 dilbert57
 
673
                --
674
                -- Vertical cursor on
675 65 davidgb
                --
676
      if r_count = ("0" & reg_vcursor(4 downto 0)) then
677
        cursor_on_v <= '1';
678
      else
679
        cursor_on_v <= '0';
680
      end if;
681
 
682 118 dilbert57
      -- cursor_on is only active when on selected character
683
                if blink_count = 0 then
684
                  blink_count <= BLINK_RATE;
685 65 davidgb
                else
686 118 dilbert57
        blink_count <= blink_count - 1;
687 65 davidgb
      end if;
688
    end if;
689
 
690 118 dilbert57
  end process;
691
  --
692
  -- VGA reset = VDU reset
693
  -- VGA = timing section
694
  -- VDU = CPU registers
695
  --
696 65 davidgb
  vga_rst <= vdu_rst;
697 118 dilbert57
  --
698
  -- VGA Sync for 640 pixels x 400 lines
699
  -- negative horizonal sync
700
  -- positive verical sync
701
  --
702 65 davidgb
  vga_hsync_o <= not horiz_sync;
703
  vga_vsync_o <= vert_sync;
704
  --
705 118 dilbert57
  -- video_on is high only when RGB data is displayed
706 65 davidgb
  --
707
  video_on1   <= video_on_H and video_on_V;
708
  cursor_on1  <= cursor_on_h and cursor_on_v;
709
 
710
--
711
-- Here to look up character ROM
712
-- This will take one clock cycle
713
-- and should be performed on p_count = "111"
714
--
715
  char_addr(10 downto 4) <= vga_data_out(6 downto 0);
716
  char_addr(3 downto 0)  <= l_count;
717
 
718
end RTL;

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