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--===========================================================================--

--                                                                           --

--            Generic Single-Port Block RAM for Xilinx                       --

--                                                                           --

--===========================================================================--

--

--  File name      : block_spram.vhd

--

--  Entity name    : block_spram

--

--  Purpose        : Implements generic block memory of arbitrary size

--

--  Dependencies   : ieee.std_logic_1164

--                   ieee.std_logic_arith

--

--  Uses           : infers family-specific block memory as required

--

--  Author         : David Burnette

--

--  Email          :       

--

--  Web            : 

--

--  Description    : Generic Block RAM 

--

--

--  This program is free software: you can redistribute it and/or modify

--  it under the terms of the GNU General Public License as published by

--  the Free Software Foundation, either version 3 of the License, or

--  (at your option) any later version.

--

--  This program is distributed in the hope that it will be useful,

--  but WITHOUT ANY WARRANTY; without even the implied warranty of

--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--  GNU General Public License for more details.

--

--  You should have received a copy of the GNU General Public License

--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

--

--===========================================================================--

--                                                                           --

--                              Revision  History                            --

--                                                                           --

--===========================================================================--

--

-- Version Date        Author     Changes

--

-- 0.1     2021-02-19  David Burnette  Initial verison 

--

library IEEE;

  use IEEE.STD_LOGIC_1164.ALL;

  use IEEE.Numeric_Std.ALL;

library unisim;

        use unisim.vcomponents.all;

entity block_spram is

  generic (

    dwidth : integer := 8;     -- parameterized data width

         awidth : integer := 16     -- parameterized address width

         );

  port (

    clk         : in std_logic;

         cs          : in std_logic; -- chip-select/enable

         addr        : in std_logic_vector(awidth-1 downto 0);

         rw          : in std_logic;

         data_in     : in std_logic_vector(dwidth-1 downto 0);

         data_out    : out std_logic_vector(dwidth-1 downto 0)

         );

end block_spram;

architecture rtl of block_spram is

  type ram_t is array ( (2**awidth)-1 downto 0) of std_logic_vector(dwidth-1 downto 0);

  signal ram_data : ram_t := (others => (others => '0')); -- ram storage, initialized to zero

  attribute ram_style : string;

  attribute ram_style of ram_data : signal is "BLOCK"; -- direct ISE/Vivado to target block memory

  signal we : std_logic;

begin

  we <= not rw;

  process ( clk )

  begin

    if (rising_edge(clk)) then

           if (cs = '1') then

                  data_out <= ram_data(to_integer(unsigned(addr))); -- read port

                  if (we = '1') then

                    ram_data(to_integer(unsigned(addr))) <= data_in; -- write port

        end if;

      end if;

    end if;

  end process;

end architecture rtl;