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[/] [System09/] [trunk/] [src/] [Flex9/] [flex9ram.vhd] - Blame information for rev 182

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Line No. Rev Author Line
1 182 davidgb 
library IEEE;
2 
   use IEEE.std_logic_1164.all;
3 
   use IEEE.std_logic_arith.all;
4 
library unisim;
5 
   use unisim.vcomponents.all;
6 
 
7 
entity FLEX9_C000 is
8 
   port(
9 
      clk       : in  std_logic;
10 
      rst       : in  std_logic;
11 
      cs        : in  std_logic;
12 
      rw        : in  std_logic;
13 
      addr      : in  std_logic_vector(10 downto 0);
14 
      data_out  : out std_logic_vector(7 downto 0);
15 
      data_in   : in  std_logic_vector(7 downto 0)
16 
   );
17 
end FLEX9_C000;
18 
 
19 
architecture rtl of FLEX9_C000 is
20 
 
21 
   type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
22 
   signal xdata : data_array;
23 
   signal en : std_logic_vector(0 downto 0);
24 
   signal dp : std_logic_vector(0 downto 0);
25 
   signal we : std_logic;
26 
 
27 
   begin
28 
 
29 
   ROM00: RAMB16_S9
30 
      generic map (
31 
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
32 
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
33 
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
34 
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
35 
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
36 
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
37 
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
38 
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
39 
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
40 
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
41 
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
42 
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
43 
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
44 
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
45 
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
46 
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000",
47 
         INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
48 
         INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
49 
         INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
50 
         INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
51 
         INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
52 
         INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
53 
         INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
54 
         INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
55 
         INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
56 
         INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
57 
         INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000",
58 
         INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000",
59 
         INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000",
60 
         INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000",
61 
         INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000",
62 
         INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000",
63 
         INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
64 
         INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
65 
         INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
66 
         INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
67 
         INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
68 
         INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
69 
         INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
70 
         INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
71 
         INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
72 
         INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
73 
         INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000",
74 
         INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",
75 
         INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",
76 
         INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",
77 
         INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",
78 
         INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",
79 
         INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
80 
         INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
81 
         INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
82 
         INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
83 
         INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
84 
         INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
85 
         INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
86 
         INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
87 
         INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
88 
         INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
89 
         INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",
90 
         INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",
91 
         INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",
92 
         INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",
93 
         INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
94 
         INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000"
95 
      )
96 
      port map (
97 
         CLK     => clk,
98 
         SSR     => rst,
99 
         EN      => en(0),
100 
         WE      => we,
101 
         ADDR    => addr(10 downto 0),
102 
         DI      => data_in,
103 
         DIP(0)  => dp(0),
104 
         DO      => xdata(0),
105 
         DOP(0)  => dp(0)
106 
      );
107 
   rom_glue: process (cs, rw, addr, xdata)
108 
   begin
109 
      en(0)  <= cs;
110 
      data_out  <= xdata(0);
111 
      we <= not rw;
112 
   end process;
113 
end architecture rtl;
114 
 
115 
library IEEE;
116 
   use IEEE.std_logic_1164.all;
117 
   use IEEE.std_logic_arith.all;
118 
library unisim;
119 
   use unisim.vcomponents.all;
120 
 
121 
entity FLEX9_C800 is
122 
   port(
123 
      clk       : in  std_logic;
124 
      rst       : in  std_logic;
125 
      cs        : in  std_logic;
126 
      rw        : in  std_logic;
127 
      addr      : in  std_logic_vector(10 downto 0);
128 
      data_out  : out std_logic_vector(7 downto 0);
129 
      data_in   : in  std_logic_vector(7 downto 0)
130 
   );
131 
end FLEX9_C800;
132 
 
133 
architecture rtl of FLEX9_C800 is
134 
 
135 
   type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
136 
   signal xdata : data_array;
137 
   signal en : std_logic_vector(0 downto 0);
138 
   signal dp : std_logic_vector(0 downto 0);
139 
   signal we : std_logic;
140 
 
141 
   begin
142 
 
143 
   ROM00: RAMB16_S9
144 
      generic map (
145 
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
146 
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
147 
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
148 
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
149 
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
150 
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
151 
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
152 
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
153 
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
154 
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
155 
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
156 
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
157 
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
158 
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
159 
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
160 
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000",
161 
         INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
162 
         INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
163 
         INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
164 
         INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
165 
         INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
166 
         INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
167 
         INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
168 
         INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
169 
         INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
170 
         INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
171 
         INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000",
172 
         INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000",
173 
         INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000",
174 
         INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000",
175 
         INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000",
176 
         INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000",
177 
         INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
178 
         INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
179 
         INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
180 
         INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
181 
         INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
182 
         INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
183 
         INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
184 
         INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
185 
         INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
186 
         INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
187 
         INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000",
188 
         INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",
189 
         INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",
190 
         INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",
191 
         INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",
192 
         INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",
193 
         INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
194 
         INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
195 
         INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
196 
         INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
197 
         INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
198 
         INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
199 
         INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
200 
         INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
201 
         INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
202 
         INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
203 
         INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",
204 
         INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",
205 
         INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",
206 
         INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",
207 
         INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
208 
         INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000"
209 
      )
210 
      port map (
211 
         CLK     => clk,
212 
         SSR     => rst,
213 
         EN      => en(0),
214 
         WE      => we,
215 
         ADDR    => addr(10 downto 0),
216 
         DI      => data_in,
217 
         DIP(0)  => dp(0),
218 
         DO      => xdata(0),
219 
         DOP(0)  => dp(0)
220 
      );
221 
   rom_glue: process (cs, rw, addr, xdata)
222 
   begin
223 
      en(0)  <= cs;
224 
      data_out  <= xdata(0);
225 
      we <= not rw;
226 
   end process;
227 
end architecture rtl;
228 
 
229 
library IEEE;
230 
   use IEEE.std_logic_1164.all;
231 
   use IEEE.std_logic_arith.all;
232 
library unisim;
233 
   use unisim.vcomponents.all;
234 
 
235 
entity FLEX9_D000 is
236 
   port(
237 
      clk       : in  std_logic;
238 
      rst       : in  std_logic;
239 
      cs        : in  std_logic;
240 
      rw        : in  std_logic;
241 
      addr      : in  std_logic_vector(10 downto 0);
242 
      data_out  : out std_logic_vector(7 downto 0);
243 
      data_in   : in  std_logic_vector(7 downto 0)
244 
   );
245 
end FLEX9_D000;
246 
 
247 
architecture rtl of FLEX9_D000 is
248 
 
249 
   type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
250 
   signal xdata : data_array;
251 
   signal en : std_logic_vector(0 downto 0);
252 
   signal dp : std_logic_vector(0 downto 0);
253 
   signal we : std_logic;
254 
 
255 
   begin
256 
 
257 
   ROM00: RAMB16_S9
258 
      generic map (
259 
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
260 
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
261 
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
262 
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
263 
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
264 
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
265 
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
266 
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
267 
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
268 
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
269 
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
270 
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
271 
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
272 
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
273 
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
274 
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000",
275 
         INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
276 
         INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
277 
         INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
278 
         INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
279 
         INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
280 
         INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
281 
         INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
282 
         INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
283 
         INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
284 
         INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
285 
         INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000",
286 
         INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000",
287 
         INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000",
288 
         INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000",
289 
         INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000",
290 
         INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000",
291 
         INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
292 
         INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
293 
         INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
294 
         INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
295 
         INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
296 
         INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
297 
         INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
298 
         INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
299 
         INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
300 
         INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
301 
         INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000",
302 
         INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",
303 
         INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",
304 
         INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",
305 
         INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",
306 
         INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",
307 
         INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
308 
         INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
309 
         INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
310 
         INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
311 
         INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
312 
         INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
313 
         INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
314 
         INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
315 
         INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
316 
         INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
317 
         INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",
318 
         INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",
319 
         INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",
320 
         INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",
321 
         INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
322 
         INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000"
323 
      )
324 
      port map (
325 
         CLK     => clk,
326 
         SSR     => rst,
327 
         EN      => en(0),
328 
         WE      => we,
329 
         ADDR    => addr(10 downto 0),
330 
         DI      => data_in,
331 
         DIP(0)  => dp(0),
332 
         DO      => xdata(0),
333 
         DOP(0)  => dp(0)
334 
      );
335 
   rom_glue: process (cs, rw, addr, xdata)
336 
   begin
337 
      en(0)  <= cs;
338 
      data_out  <= xdata(0);
339 
      we <= not rw;
340 
   end process;
341 
end architecture rtl;
342 
 
343 
library IEEE;
344 
   use IEEE.std_logic_1164.all;
345 
   use IEEE.std_logic_arith.all;
346 
library unisim;
347 
   use unisim.vcomponents.all;
348 
 
349 
entity FLEX9_D800 is
350 
   port(
351 
      clk       : in  std_logic;
352 
      rst       : in  std_logic;
353 
      cs        : in  std_logic;
354 
      rw        : in  std_logic;
355 
      addr      : in  std_logic_vector(10 downto 0);
356 
      data_out  : out std_logic_vector(7 downto 0);
357 
      data_in   : in  std_logic_vector(7 downto 0)
358 
   );
359 
end FLEX9_D800;
360 
 
361 
architecture rtl of FLEX9_D800 is
362 
 
363 
   type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
364 
   signal xdata : data_array;
365 
   signal en : std_logic_vector(0 downto 0);
366 
   signal dp : std_logic_vector(0 downto 0);
367 
   signal we : std_logic;
368 
 
369 
   begin
370 
 
371 
   ROM00: RAMB16_S9
372 
      generic map (
373 
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
374 
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
375 
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
376 
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
377 
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
378 
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
379 
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
380 
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
381 
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
382 
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
383 
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
384 
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
385 
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
386 
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
387 
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
388 
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000",
389 
         INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
390 
         INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
391 
         INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
392 
         INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
393 
         INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
394 
         INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
395 
         INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
396 
         INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
397 
         INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
398 
         INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
399 
         INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000",
400 
         INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000",
401 
         INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000",
402 
         INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000",
403 
         INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000",
404 
         INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000",
405 
         INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
406 
         INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
407 
         INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
408 
         INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
409 
         INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
410 
         INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
411 
         INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
412 
         INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
413 
         INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
414 
         INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
415 
         INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000",
416 
         INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",
417 
         INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",
418 
         INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",
419 
         INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",
420 
         INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",
421 
         INIT_30 => x"0000C3007EBF007EA7007EA3007E9F007E6C007E63007E5F007E5B007E57007E",
422 
         INIT_31 => x"0000000000000000000000000000FFFF40100302010000000000000000000000",
423 
         INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
424 
         INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
425 
         INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
426 
         INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
427 
         INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
428 
         INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
429 
         INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
430 
         INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
431 
         INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",
432 
         INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",
433 
         INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",
434 
         INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",
435 
         INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
436 
         INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000"
437 
      )
438 
      port map (
439 
         CLK     => clk,
440 
         SSR     => rst,
441 
         EN      => en(0),
442 
         WE      => we,
443 
         ADDR    => addr(10 downto 0),
444 
         DI      => data_in,
445 
         DIP(0)  => dp(0),
446 
         DO      => xdata(0),
447 
         DOP(0)  => dp(0)
448 
      );
449 
   rom_glue: process (cs, rw, addr, xdata)
450 
   begin
451 
      en(0)  <= cs;
452 
      data_out  <= xdata(0);
453 
      we <= not rw;
454 
   end process;
455 
end architecture rtl;
456 
 
457 
--
458 
-- Flex9 O/S Initialised 8KByte RAM
459 
--
460 
-- v1.0 - 22 December 2006 - John Kent
461 
-- v1.1 -  1 February 2008 - David Burnette
462 
--        reworked to use autogenerated block ram utility
463 
 
464 
library IEEE;
465 
use IEEE.STD_LOGIC_1164.ALL;
466 
use IEEE.STD_LOGIC_ARITH.ALL;
467 
library unisim;
468 
        use unisim.vcomponents.all;
469 
 
470 
entity flex_ram is
471 
    Port (
472 
       clk   : in  std_logic;
473 
       rst   : in  std_logic;
474 
       cs    : in  std_logic;
475 
       rw    : in  std_logic;
476 
       addr  : in  std_logic_vector (12 downto 0);
477 
       data_out : out std_logic_vector (7 downto 0);
478 
       data_in : in  std_logic_vector (7 downto 0)
479 
    );
480 
end flex_ram;
481 
 
482 
architecture rtl of flex_ram is
483 
 
484 
  signal we     : std_logic;
485 
  signal cs0    : std_logic;
486 
  signal cs1    : std_logic;
487 
  signal cs2    : std_logic;
488 
  signal cs3    : std_logic;
489 
  signal dp0    : std_logic;
490 
  signal dp1    : std_logic;
491 
  signal dp2    : std_logic;
492 
  signal dp3    : std_logic;
493 
  signal rdata0 : std_logic_vector(7 downto 0);
494 
  signal rdata1 : std_logic_vector(7 downto 0);
495 
  signal rdata2 : std_logic_vector(7 downto 0);
496 
  signal rdata3 : std_logic_vector(7 downto 0);
497 
 
498 
component FLEX9_C000
499 
    Port (
500 
       clk   : in  std_logic;
501 
       rst   : in  std_logic;
502 
       cs    : in  std_logic;
503 
       rw    : in  std_logic;
504 
       addr  : in  std_logic_vector (10 downto 0);
505 
       data_out : out std_logic_vector (7 downto 0);
506 
       data_in : in  std_logic_vector (7 downto 0)
507 
    );
508 
end component;
509 
component FLEX9_C800
510 
    Port (
511 
       clk   : in  std_logic;
512 
       rst   : in  std_logic;
513 
       cs    : in  std_logic;
514 
       rw    : in  std_logic;
515 
       addr  : in  std_logic_vector (10 downto 0);
516 
       data_out : out std_logic_vector (7 downto 0);
517 
       data_in : in  std_logic_vector (7 downto 0)
518 
    );
519 
end component;
520 
component FLEX9_D000
521 
    Port (
522 
       clk   : in  std_logic;
523 
       rst   : in  std_logic;
524 
       cs    : in  std_logic;
525 
       rw    : in  std_logic;
526 
       addr  : in  std_logic_vector (10 downto 0);
527 
       data_out : out std_logic_vector (7 downto 0);
528 
       data_in : in  std_logic_vector (7 downto 0)
529 
    );
530 
end component;
531 
component FLEX9_D800
532 
    Port (
533 
       clk   : in  std_logic;
534 
       rst   : in  std_logic;
535 
       cs    : in  std_logic;
536 
       rw    : in  std_logic;
537 
       addr  : in  std_logic_vector (10 downto 0);
538 
       data_out : out std_logic_vector (7 downto 0);
539 
       data_in : in  std_logic_vector (7 downto 0)
540 
    );
541 
end component;
542 
 
543 
begin
544 
 
545 
   addr_c000 : FLEX9_C000 port map (
546 
       clk   => clk,
547 
       rst   => rst,
548 
       cs    => cs0,
549 
       rw    => rw,
550 
       addr  => addr(10 downto 0),
551 
       data_in => data_in,
552 
       data_out => rdata0
553 
    );
554 
 
555 
   addr_c800 : FLEX9_C800 port map (
556 
       clk   => clk,
557 
       rst   => rst,
558 
       cs    => cs1,
559 
       rw    => rw,
560 
       addr  => addr(10 downto 0),
561 
       data_in => data_in,
562 
       data_out => rdata1
563 
    );
564 
   addr_d000 : FLEX9_D000 port map (
565 
       clk   => clk,
566 
       rst   => rst,
567 
       cs    => cs2,
568 
       rw    => rw,
569 
       addr  => addr(10 downto 0),
570 
       data_in => data_in,
571 
       data_out => rdata2
572 
    );
573 
   addr_d800 : FLEX9_D800 port map (
574 
       clk   => clk,
575 
       rst   => rst,
576 
       cs    => cs3,
577 
       rw    => rw,
578 
       addr  => addr(10 downto 0),
579 
       data_in => data_in,
580 
       data_out => rdata3
581 
    );
582 
 
583 
my_flex : process ( rw, addr, cs, rdata0, rdata1, rdata2, rdata3 )
584 
begin
585 
         we    <= not rw;
586 
         case addr(12 downto 11) is
587 
         when "00" =>
588 
                cs0   <= cs;
589 
                cs1   <= '0';
590 
                cs2   <= '0';
591 
                cs3   <= '0';
592 
                data_out <= rdata0;
593 
    when "01" =>
594 
                cs0   <= '0';
595 
                cs1   <= cs;
596 
                cs2   <= '0';
597 
                cs3   <= '0';
598 
                data_out <= rdata1;
599 
         when "10" =>
600 
                cs0   <= '0';
601 
                cs1   <= '0';
602 
                cs2   <= cs;
603 
                cs3   <= '0';
604 
                data_out <= rdata2;
605 
    when "11" =>
606 
                cs0   <= '0';
607 
                cs1   <= '0';
608 
                cs2   <= '0';
609 
                cs3   <= cs;
610 
                data_out <= rdata3;
611 
    when others =>
612 
                null;
613 
    end case;
614 
 
615 
end process;
616 
 
617 
end architecture rtl;
618 
 

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