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[/] [System09/] [trunk/] [src/] [Flex9/] [flex_ram_vhd] - Blame information for rev 181

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Line No. Rev Author Line
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--
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-- Flex9 O/S Initialised 8KByte RAM
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--
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-- v1.0 - 22 December 2006 - John Kent
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-- v1.1 -  1 February 2008 - David Burnette
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--        reworked to use autogenerated block ram utility
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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library unisim;
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        use unisim.vcomponents.all;
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entity flex_ram is
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    Port (
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       clk   : in  std_logic;
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       rst   : in  std_logic;
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       cs    : in  std_logic;
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       rw    : in  std_logic;
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       addr  : in  std_logic_vector (12 downto 0);
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       data_out : out std_logic_vector (7 downto 0);
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       data_in : in  std_logic_vector (7 downto 0)
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    );
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end flex_ram;
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architecture rtl of flex_ram is
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  signal we     : std_logic;
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  signal cs0    : std_logic;
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  signal cs1    : std_logic;
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  signal cs2    : std_logic;
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  signal cs3    : std_logic;
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  signal dp0    : std_logic;
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  signal dp1    : std_logic;
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  signal dp2    : std_logic;
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  signal dp3    : std_logic;
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  signal rdata0 : std_logic_vector(7 downto 0);
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  signal rdata1 : std_logic_vector(7 downto 0);
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  signal rdata2 : std_logic_vector(7 downto 0);
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  signal rdata3 : std_logic_vector(7 downto 0);
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component FLEX9_C000
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    Port (
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       clk   : in  std_logic;
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       rst   : in  std_logic;
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       cs    : in  std_logic;
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       rw    : in  std_logic;
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       addr  : in  std_logic_vector (10 downto 0);
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       data_out : out std_logic_vector (7 downto 0);
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       data_in : in  std_logic_vector (7 downto 0)
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    );
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end component;
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component FLEX9_C800
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    Port (
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       clk   : in  std_logic;
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       rst   : in  std_logic;
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       cs    : in  std_logic;
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       rw    : in  std_logic;
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       addr  : in  std_logic_vector (10 downto 0);
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       data_out : out std_logic_vector (7 downto 0);
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       data_in : in  std_logic_vector (7 downto 0)
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    );
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end component;
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component FLEX9_D000
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    Port (
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       clk   : in  std_logic;
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       rst   : in  std_logic;
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       cs    : in  std_logic;
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       rw    : in  std_logic;
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       addr  : in  std_logic_vector (10 downto 0);
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       data_out : out std_logic_vector (7 downto 0);
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       data_in : in  std_logic_vector (7 downto 0)
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    );
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end component;
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component FLEX9_D800
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    Port (
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       clk   : in  std_logic;
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       rst   : in  std_logic;
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       cs    : in  std_logic;
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       rw    : in  std_logic;
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       addr  : in  std_logic_vector (10 downto 0);
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       data_out : out std_logic_vector (7 downto 0);
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       data_in : in  std_logic_vector (7 downto 0)
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    );
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end component;
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begin
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   addr_c000 : FLEX9_C000 port map (
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       clk   => clk,
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       rst   => rst,
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       cs    => cs0,
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       rw    => rw,
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       addr  => addr(10 downto 0),
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       data_in => data_in,
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       data_out => rdata0
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    );
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   addr_c800 : FLEX9_C800 port map (
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       clk   => clk,
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       rst   => rst,
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       cs    => cs1,
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       rw    => rw,
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       addr  => addr(10 downto 0),
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       data_in => data_in,
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       data_out => rdata1
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    );
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   addr_d000 : FLEX9_D000 port map (
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       clk   => clk,
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       rst   => rst,
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       cs    => cs2,
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       rw    => rw,
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       addr  => addr(10 downto 0),
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       data_in => data_in,
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       data_out => rdata2
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    );
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   addr_d800 : FLEX9_D800 port map (
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       clk   => clk,
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       rst   => rst,
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       cs    => cs3,
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       rw    => rw,
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       addr  => addr(10 downto 0),
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       data_in => data_in,
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       data_out => rdata3
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    );
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my_flex : process ( rw, addr, cs, rdata0, rdata1, rdata2, rdata3 )
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begin
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         we    <= not rw;
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         case addr(12 downto 11) is
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         when "00" =>
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                cs0   <= cs;
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                cs1   <= '0';
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                cs2   <= '0';
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                cs3   <= '0';
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                data_out <= rdata0;
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    when "01" =>
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                cs0   <= '0';
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                cs1   <= cs;
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                cs2   <= '0';
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                cs3   <= '0';
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                data_out <= rdata1;
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         when "10" =>
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                cs0   <= '0';
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                cs1   <= '0';
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                cs2   <= cs;
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                cs3   <= '0';
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                data_out <= rdata2;
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    when "11" =>
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                cs0   <= '0';
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                cs1   <= '0';
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                cs2   <= '0';
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                cs3   <= cs;
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                data_out <= rdata3;
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    when others =>
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                null;
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    end case;
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end process;
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end architecture rtl;
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