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[/] [System09/] [trunk/] [src/] [sys09bug/] [sys09swt.vhd] - Blame information for rev 183

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library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
library unisim;
   use unisim.vcomponents.all;
 
entity SYS09BUG_F000 is
   port(
      clk       : in  std_logic;
      rst       : in  std_logic;
      cs        : in  std_logic;
      rw        : in  std_logic;
      addr      : in  std_logic_vector(10 downto 0);
      data_out  : out std_logic_vector(7 downto 0);
      data_in   : in  std_logic_vector(7 downto 0)
   );
end SYS09BUG_F000;
 
architecture rtl of SYS09BUG_F000 is
 
   type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
   signal xdata : data_array;
   signal en : std_logic_vector(0 downto 0);
   signal dp : std_logic_vector(0 downto 0);
   signal we : std_logic;
 
   begin
 
   ROM00: RAMB16_S9
      generic map (
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000"
      )
      port map (
         CLK     => clk,
         SSR     => rst,
         EN      => en(0),
         WE      => we,
         ADDR    => addr(10 downto 0),
         DI      => data_in,
         DIP(0)  => dp(0),
         DO      => xdata(0),
         DOP(0)  => dp(0)
      );
   rom_glue: process (cs, rw, addr, xdata)
   begin
      en(0)  <= cs;
      data_out  <= xdata(0);
      we <= not rw;
   end process;
end architecture rtl;
 
library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
library unisim;
   use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
   port(
      clk       : in  std_logic;
      rst       : in  std_logic;
      cs        : in  std_logic;
      rw        : in  std_logic;
      addr      : in  std_logic_vector(10 downto 0);
      data_out  : out std_logic_vector(7 downto 0);
      data_in   : in  std_logic_vector(7 downto 0)
   );
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
   type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
   signal xdata : data_array;
   signal en : std_logic_vector(0 downto 0);
   signal dp : std_logic_vector(0 downto 0);
   signal we : std_logic;
 
   begin
 
   ROM00: RAMB16_S9
      generic map (
         INIT_00 => x"A780A610C6C0DF8E10A3FD8EB6FAA2FBA6FB17FC42FD34FD1FFD25FD61F814F8",
         INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
         INIT_02 => x"0317D2FD8E940417F62A5A19048B0327856D0DC64FD0DF8ECF0317B3FD8E1505",
         INIT_03 => x"17408B981FC704175E86092C2081891FF1270D817F84BB04173B0317D9FD8EB6",
         INIT_04 => x"20780317DBFD8EF526A3FD8C02300F2780E16AFD8E20C0022F60C1BB0417C004",
         INIT_05 => x"17A4A68304172D0417211FED0217E1FD8E121F2D29F303173B341FBC2094ADC0",
         INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E12708811128E603177B04172D04",
         INIT_07 => x"93031705201F30C0DF8E321F2A0317BE203F31C22021315904173F865C041708",
         INIT_08 => x"271504170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
         INIT_09 => x"265A020417B4031780A610C60A0417B60317E4AE760217E1FD8E103439623203",
         INIT_0a => x"293F0317BC20EE265AEB03172E8602237E810425208180A610C6E1AEFA0317F5",
         INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
         INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E10BA03163F86BD0317",
         INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16D00217068D",
         INIT_0e => x"013000008E14E07F18E07D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
         INIT_0f => x"8D18E0B78C86298D1AE0B70186F92601C518E0F6378D18E0B70F86F92600008C",
         INIT_10 => x"4AAF00C08E3901272CC5F02601C518E0F680A71BE0B6052702C5092000C08E22",
         INIT_11 => x"8610F07D16F0B715F0B710F0B714F0B7FF8624F0B7DE8639FD265A04C63B341F",
         INIT_12 => x"8ECA261085F926018520F0B689001720F0B70986FB2B20F0B696001720F0B7D8",
         INIT_13 => x"14F0B7FE8610F0B7FF8602F0BFFFFE8E00F0FD5343101F40F0B7108A528D00C0",
         INIT_14 => x"358A20F0265A0435F8265A0A2A10F07D5F04345F518D20F0B78C8622F0B70186",
         INIT_15 => x"8E104444444462A636343B341F4AAF00C08E24F0F7DEC63901271C8520F0B604",
         INIT_16 => x"C60434B63562E762EA62A70F8462A65858585853A6E6E4E754545454A6E6D0DF",
         INIT_17 => x"813D2739811F0217F9265381260217E2DF7F540217118657FDBD8435FD265A20",
         INIT_18 => x"8E01170434E46AE46AE4EBE0EBE0E61034212991011726290234A80117F12631",
         INIT_19 => x"86E2DF730602173F86BA27FFC102355FEB2080A70527E46AE0EB02340C290435",
         INIT_1a => x"A3E4ECE50117128657FDBDE4AF0130492562AC4D2930344A0117E26FFE011613",
         INIT_1b => x"EB68011762AE750117981F03CB2F001722FE8E64E720C6022320008310062762",
         INIT_1c => x"32A301171486C326E4AC62AF5B0117981F53F526646A65011780A684EB63EB62",
         INIT_1d => x"F68DF28D910017E50016F800168D01169035690017D3FD8E10347120028D3965",
         INIT_1e => x"8DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE78D618D394AAF0229",
         INIT_1f => x"B08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D498D3944AF0229D5",
         INIT_20 => x"FD8E39F726048180A62B011739C4A7808A0429A68DA58D5F8D3941A70229B18D",
         INIT_21 => x"D78DFDFD8EB4001643A6E18D03FE8EF42048AEEA8DF1FD8EBF0016311FF48DE5",
         INIT_22 => x"8ED92041A6BC8D09FE8ECF204AAEC58DEBFD8ED82046AECE8DF7FD8EE12044AE",
         INIT_23 => x"8DA98DA18D27FF17E1FD8E9000161AFE8EC4A6AA8D13FE8ED02042A6B38D0EFE",
         INIT_24 => x"0E8DA400172D86121F4D29098DD520CE8DC78DC08D17FF17E1FD8EBF8DB88DB0",
         INIT_25 => x"E0AB04342829078D891F484848483229118D903561A710343C29088D011F4229",
         INIT_26 => x"226681072561813937800322468112254181393080032239811D253081578D39",
         INIT_27 => x"2F3981308B0F840235048D4444444402340235028D0235103439021A39578003",
         INIT_28 => x"8D0627E2DF7D8235F1265A2B8D2F8D2D860225E46880A608C602343D20078B02",
         INIT_29 => x"008D82350185E0DF9FA60234903501A6F727018584A6E0DFBE10341D207F8404",
         INIT_2a => x"518684A70386E0DFBE903501A70235F6260885FA27028584A6E0DFBE12342086",
         INIT_2b => x"19DBFB18C5FB15B9FB10E6FB0407FC03F1FB02FCFB0139E2DFB7FF86016D84A7",
         INIT_2c => x"D5F94488F958F1F85375FC52A8F84D44FB50E6FA4CA5F847FDF8455CF942D0FB",
         INIT_2d => x"47554239305359530000000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F929FA55",
         INIT_2e => x"3F54414857043E040000000A0D4B04202D20435054575320524F4620372E3120",
         INIT_2f => x"492020043D59492020043D53552020043D43502020043D5053202004202D2004",
         INIT_30 => x"5A4E4948464504203A43432020043D422020043D412020043D50442020043D58",
         INIT_31 => x"0000000000000000000000000000000000000000000000000000000431534356",
         INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_38 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
         INIT_39 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
         INIT_3a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
         INIT_3b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
         INIT_3c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
         INIT_3d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
         INIT_3e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
         INIT_3f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
      )
      port map (
         CLK     => clk,
         SSR     => rst,
         EN      => en(0),
         WE      => we,
         ADDR    => addr(10 downto 0),
         DI      => data_in,
         DIP(0)  => dp(0),
         DO      => xdata(0),
         DOP(0)  => dp(0)
      );
   rom_glue: process (cs, rw, addr, xdata)
   begin
      en(0)  <= cs;
      data_out  <= xdata(0);
      we <= not rw;
   end process;
end architecture rtl;
 
--
-- SYS09BUG Monitor Program
-- v1.0 - 21 November 2006 - John Knet
--
-- v1.1 - 22 december 2006 - John Kent
--        made into 4K ROM/RAM.
-- 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
    use unisim.vcomponents.all;
 
entity mon_rom is
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (11 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       data_in : in  std_logic_vector (7 downto 0)
    );
end mon_rom;
 
architecture rtl of mon_rom is
 
  signal we     : std_logic;
  signal cs0    : std_logic;
  signal cs1    : std_logic;
  signal dp0    : std_logic;
  signal dp1    : std_logic;
  signal rdata0 : std_logic_vector(7 downto 0);
  signal rdata1 : std_logic_vector(7 downto 0);
 
component SYS09BUG_F000
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       data_in : in  std_logic_vector (7 downto 0)
    );
end component;
 
component SYS09BUG_F800
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       data_in : in  std_logic_vector (7 downto 0)
    );
end component;
 
begin
 
   addr_f000 : SYS09BUG_F000 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs0,
       rw    => rw,
       addr  => addr(10 downto 0),
       data_in => data_in,
       data_out => rdata0
    );
 
   addr_f800 : SYS09BUG_F800 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs1,
       rw    => rw,
       addr  => addr(10 downto 0),
       data_in => data_in,
       data_out => rdata1
    );
 
    my_mon : process ( rw, addr, cs, rdata0, rdata1 )
    begin
       we    <= not rw;
       case addr(11) is
           when '0' =>
               cs0   <= cs;
               cs1   <= '0';
               data_out <= rdata0;
           when '1' =>
               cs0   <= '0';
               cs1   <= cs;
               data_out <= rdata1;
           when others =>
               null;
       end case;
    end process;
 
end architecture rtl;
 

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Subversion Repositories System09

[/] [System09/] [trunk/] [src/] [sys09bug/] [sys09swt.vhd] - Blame information for rev 183

Line No.	Rev	Author	Line
1	181	davidgb	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3			`use IEEE.std_logic_arith.all;`
4			`library unisim;`
5			`use unisim.vcomponents.all;`
6
7			`entity SYS09BUG_F000 is`
8			`port(`
9			`clk : in std_logic;`
10			`rst : in std_logic;`
11			`cs : in std_logic;`
12			`rw : in std_logic;`
13			`addr : in std_logic_vector(10 downto 0);`
14			`data_out : out std_logic_vector(7 downto 0);`
15			`data_in : in std_logic_vector(7 downto 0)`
16			`);`
17			`end SYS09BUG_F000;`
18
19			`architecture rtl of SYS09BUG_F000 is`
20
21			`type data_array is array(0 to 0) of std_logic_vector(7 downto 0);`
22			`signal xdata : data_array;`
23			`signal en : std_logic_vector(0 downto 0);`
24			`signal dp : std_logic_vector(0 downto 0);`
25			`signal we : std_logic;`
26
27			`begin`
28
29			`ROM00: RAMB16_S9`
30			`generic map (`
31			`INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",`
32			`INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",`
33			`INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",`
34			`INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",`
35			`INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",`
36			`INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",`
37			`INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",`
38			`INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",`
39			`INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",`
40			`INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",`
41			`INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",`
42			`INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",`
43			`INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",`
44			`INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",`
45			`INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",`
46			`INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000",`
47			`INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",`
48			`INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",`
49			`INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",`
50			`INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",`
51			`INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",`
52			`INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",`
53			`INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",`
54			`INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",`
55			`INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",`
56			`INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",`
57			`INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000",`
58			`INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000",`
59			`INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000",`
60			`INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000",`
61			`INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000",`
62			`INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000",`
63			`INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",`
64			`INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",`
65			`INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",`
66			`INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",`
67			`INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",`
68			`INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",`
69			`INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",`
70			`INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",`
71			`INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",`
72			`INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",`
73			`INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000",`
74			`INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",`
75			`INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",`
76			`INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",`
77			`INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",`
78			`INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",`
79			`INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",`
80			`INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",`
81			`INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",`
82			`INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",`
83			`INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",`
84			`INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",`
85			`INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",`
86			`INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",`
87			`INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",`
88			`INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",`
89			`INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",`
90			`INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",`
91			`INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",`
92			`INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",`
93			`INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",`
94			`INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000"`
95			`)`
96			`port map (`
97			`CLK => clk,`
98			`SSR => rst,`
99			`EN => en(0),`
100			`WE => we,`
101			`ADDR => addr(10 downto 0),`
102			`DI => data_in,`
103			`DIP(0) => dp(0),`
104			`DO => xdata(0),`
105			`DOP(0) => dp(0)`
106			`);`
107			`rom_glue: process (cs, rw, addr, xdata)`
108			`begin`
109			`en(0) <= cs;`
110			`data_out <= xdata(0);`
111			`we <= not rw;`
112			`end process;`
113			`end architecture rtl;`
114
115			`library IEEE;`
116			`use IEEE.std_logic_1164.all;`
117			`use IEEE.std_logic_arith.all;`
118			`library unisim;`
119			`use unisim.vcomponents.all;`
120
121			`entity SYS09BUG_F800 is`
122			`port(`
123			`clk : in std_logic;`
124			`rst : in std_logic;`
125			`cs : in std_logic;`
126			`rw : in std_logic;`
127			`addr : in std_logic_vector(10 downto 0);`
128			`data_out : out std_logic_vector(7 downto 0);`
129			`data_in : in std_logic_vector(7 downto 0)`
130			`);`
131			`end SYS09BUG_F800;`
132
133			`architecture rtl of SYS09BUG_F800 is`
134
135			`type data_array is array(0 to 0) of std_logic_vector(7 downto 0);`
136			`signal xdata : data_array;`
137			`signal en : std_logic_vector(0 downto 0);`
138			`signal dp : std_logic_vector(0 downto 0);`
139			`signal we : std_logic;`
140
141			`begin`
142
143			`ROM00: RAMB16_S9`
144			`generic map (`
145			`INIT_00 => x"A780A610C6C0DF8E10A3FD8EB6FAA2FBA6FB17FC42FD34FD1FFD25FD61F814F8",`
146			`INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",`
147			`INIT_02 => x"0317D2FD8E940417F62A5A19048B0327856D0DC64FD0DF8ECF0317B3FD8E1505",`
148			`INIT_03 => x"17408B981FC704175E86092C2081891FF1270D817F84BB04173B0317D9FD8EB6",`
149			`INIT_04 => x"20780317DBFD8EF526A3FD8C02300F2780E16AFD8E20C0022F60C1BB0417C004",`
150			`INIT_05 => x"17A4A68304172D0417211FED0217E1FD8E121F2D29F303173B341FBC2094ADC0",`
151			`INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E12708811128E603177B04172D04",`
152			`INIT_07 => x"93031705201F30C0DF8E321F2A0317BE203F31C22021315904173F865C041708",`
153			`INIT_08 => x"271504170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",`
154			`INIT_09 => x"265A020417B4031780A610C60A0417B60317E4AE760217E1FD8E103439623203",`
155			`INIT_0a => x"293F0317BC20EE265AEB03172E8602237E810425208180A610C6E1AEFA0317F5",`
156			`INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",`
157			`INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E10BA03163F86BD0317",`
158			`INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16D00217068D",`
159			`INIT_0e => x"013000008E14E07F18E07D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",`
160			`INIT_0f => x"8D18E0B78C86298D1AE0B70186F92601C518E0F6378D18E0B70F86F92600008C",`
161			`INIT_10 => x"4AAF00C08E3901272CC5F02601C518E0F680A71BE0B6052702C5092000C08E22",`
162			`INIT_11 => x"8610F07D16F0B715F0B710F0B714F0B7FF8624F0B7DE8639FD265A04C63B341F",`
163			`INIT_12 => x"8ECA261085F926018520F0B689001720F0B70986FB2B20F0B696001720F0B7D8",`
164			`INIT_13 => x"14F0B7FE8610F0B7FF8602F0BFFFFE8E00F0FD5343101F40F0B7108A528D00C0",`
165			`INIT_14 => x"358A20F0265A0435F8265A0A2A10F07D5F04345F518D20F0B78C8622F0B70186",`
166			`INIT_15 => x"8E104444444462A636343B341F4AAF00C08E24F0F7DEC63901271C8520F0B604",`
167			`INIT_16 => x"C60434B63562E762EA62A70F8462A65858585853A6E6E4E754545454A6E6D0DF",`
168			`INIT_17 => x"813D2739811F0217F9265381260217E2DF7F540217118657FDBD8435FD265A20",`
169			`INIT_18 => x"8E01170434E46AE46AE4EBE0EBE0E61034212991011726290234A80117F12631",`
170			`INIT_19 => x"86E2DF730602173F86BA27FFC102355FEB2080A70527E46AE0EB02340C290435",`
171			`INIT_1a => x"A3E4ECE50117128657FDBDE4AF0130492562AC4D2930344A0117E26FFE011613",`
172			`INIT_1b => x"EB68011762AE750117981F03CB2F001722FE8E64E720C6022320008310062762",`
173			`INIT_1c => x"32A301171486C326E4AC62AF5B0117981F53F526646A65011780A684EB63EB62",`
174			`INIT_1d => x"F68DF28D910017E50016F800168D01169035690017D3FD8E10347120028D3965",`
175			`INIT_1e => x"8DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE78D618D394AAF0229",`
176			`INIT_1f => x"B08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D498D3944AF0229D5",`
177			`INIT_20 => x"FD8E39F726048180A62B011739C4A7808A0429A68DA58D5F8D3941A70229B18D",`
178			`INIT_21 => x"D78DFDFD8EB4001643A6E18D03FE8EF42048AEEA8DF1FD8EBF0016311FF48DE5",`
179			`INIT_22 => x"8ED92041A6BC8D09FE8ECF204AAEC58DEBFD8ED82046AECE8DF7FD8EE12044AE",`
180			`INIT_23 => x"8DA98DA18D27FF17E1FD8E9000161AFE8EC4A6AA8D13FE8ED02042A6B38D0EFE",`
181			`INIT_24 => x"0E8DA400172D86121F4D29098DD520CE8DC78DC08D17FF17E1FD8EBF8DB88DB0",`
182			`INIT_25 => x"E0AB04342829078D891F484848483229118D903561A710343C29088D011F4229",`
183			`INIT_26 => x"226681072561813937800322468112254181393080032239811D253081578D39",`
184			`INIT_27 => x"2F3981308B0F840235048D4444444402340235028D0235103439021A39578003",`
185			`INIT_28 => x"8D0627E2DF7D8235F1265A2B8D2F8D2D860225E46880A608C602343D20078B02",`
186			`INIT_29 => x"008D82350185E0DF9FA60234903501A6F727018584A6E0DFBE10341D207F8404",`
187			`INIT_2a => x"518684A70386E0DFBE903501A70235F6260885FA27028584A6E0DFBE12342086",`
188			`INIT_2b => x"19DBFB18C5FB15B9FB10E6FB0407FC03F1FB02FCFB0139E2DFB7FF86016D84A7",`
189			`INIT_2c => x"D5F94488F958F1F85375FC52A8F84D44FB50E6FA4CA5F847FDF8455CF942D0FB",`
190			`INIT_2d => x"47554239305359530000000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F929FA55",`
191			`INIT_2e => x"3F54414857043E040000000A0D4B04202D20435054575320524F4620372E3120",`
192			`INIT_2f => x"492020043D59492020043D53552020043D43502020043D5053202004202D2004",`
193			`INIT_30 => x"5A4E4948464504203A43432020043D422020043D412020043D50442020043D58",`
194			`INIT_31 => x"0000000000000000000000000000000000000000000000000000000431534356",`
195			`INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",`
196			`INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",`
197			`INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",`
198			`INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",`
199			`INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",`
200			`INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",`
201			`INIT_38 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",`
202			`INIT_39 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",`
203			`INIT_3a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",`
204			`INIT_3b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",`
205			`INIT_3c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",`
206			`INIT_3d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",`
207			`INIT_3e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",`
208			`INIT_3f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"`
209			`)`
210			`port map (`
211			`CLK => clk,`
212			`SSR => rst,`
213			`EN => en(0),`
214			`WE => we,`
215			`ADDR => addr(10 downto 0),`
216			`DI => data_in,`
217			`DIP(0) => dp(0),`
218			`DO => xdata(0),`
219			`DOP(0) => dp(0)`
220			`);`
221			`rom_glue: process (cs, rw, addr, xdata)`
222			`begin`
223			`en(0) <= cs;`
224			`data_out <= xdata(0);`
225			`we <= not rw;`
226			`end process;`
227			`end architecture rtl;`
228
229			`--`
230			`-- SYS09BUG Monitor Program`
231			`-- v1.0 - 21 November 2006 - John Knet`
232			`--`
233			`-- v1.1 - 22 december 2006 - John Kent`
234			`-- made into 4K ROM/RAM.`
235			`--`
236			`library IEEE;`
237			`use IEEE.STD_LOGIC_1164.ALL;`
238			`use IEEE.STD_LOGIC_ARITH.ALL;`
239			`library unisim;`
240			`use unisim.vcomponents.all;`
241
242			`entity mon_rom is`
243			`Port (`
244			`clk : in std_logic;`
245			`rst : in std_logic;`
246			`cs : in std_logic;`
247			`rw : in std_logic;`
248			`addr : in std_logic_vector (11 downto 0);`
249			`data_out : out std_logic_vector (7 downto 0);`
250			`data_in : in std_logic_vector (7 downto 0)`
251			`);`
252			`end mon_rom;`
253
254			`architecture rtl of mon_rom is`
255
256			`signal we : std_logic;`
257			`signal cs0 : std_logic;`
258			`signal cs1 : std_logic;`
259			`signal dp0 : std_logic;`
260			`signal dp1 : std_logic;`
261			`signal rdata0 : std_logic_vector(7 downto 0);`
262			`signal rdata1 : std_logic_vector(7 downto 0);`
263
264			`component SYS09BUG_F000`
265			`Port (`
266			`clk : in std_logic;`
267			`rst : in std_logic;`
268			`cs : in std_logic;`
269			`rw : in std_logic;`
270			`addr : in std_logic_vector (10 downto 0);`
271			`data_out : out std_logic_vector (7 downto 0);`
272			`data_in : in std_logic_vector (7 downto 0)`
273			`);`
274			`end component;`
275
276			`component SYS09BUG_F800`
277			`Port (`
278			`clk : in std_logic;`
279			`rst : in std_logic;`
280			`cs : in std_logic;`
281			`rw : in std_logic;`
282			`addr : in std_logic_vector (10 downto 0);`
283			`data_out : out std_logic_vector (7 downto 0);`
284			`data_in : in std_logic_vector (7 downto 0)`
285			`);`
286			`end component;`
287
288			`begin`
289
290			`addr_f000 : SYS09BUG_F000 port map (`
291			`clk => clk,`
292			`rst => rst,`
293			`cs => cs0,`
294			`rw => rw,`
295			`addr => addr(10 downto 0),`
296			`data_in => data_in,`
297			`data_out => rdata0`
298			`);`
299
300			`addr_f800 : SYS09BUG_F800 port map (`
301			`clk => clk,`
302			`rst => rst,`
303			`cs => cs1,`
304			`rw => rw,`
305			`addr => addr(10 downto 0),`
306			`data_in => data_in,`
307			`data_out => rdata1`
308			`);`
309
310			`my_mon : process ( rw, addr, cs, rdata0, rdata1 )`
311			`begin`
312			`we <= not rw;`
313			`case addr(11) is`
314			`when '0' =>`
315			`cs0 <= cs;`
316			`cs1 <= '0';`
317			`data_out <= rdata0;`
318			`when '1' =>`
319			`cs0 <= '0';`
320			`cs1 <= cs;`
321			`data_out <= rdata1;`
322			`when others =>`
323			`null;`
324			`end case;`
325			`end process;`
326
327			`end architecture rtl;`
328