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[/] [System11/] [trunk/] [rtl/] [vhdl/] [System11.vhd] - Blame information for rev 2

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--===========================================================================--
--
--  S Y N T H E Z I A B L E    System11 - System on a Chip
--
--  www.OpenCores.Org - September 2003
--  This core adheres to the GNU public license  
--
-- File name      : system11.vhd
--
-- Entity name    : system11
--
-- Purpose        : SWTBUG Monitor modified for the 68HC11
--                  ROM sits at $E000
--                  Assumes an 6850 ACIA sits at $8004
--                  Assumes RAM at $A000 - $BFFF for Flex 2
--                  1024 byte x 8 bit
--                  Modified stack to allow for Y register
--                  This SOC does not include any 68HC11 
--                  on chip peripherals
--
-- Dependencies   : ieee.std_logic_1164
--                  ieee.std_logic_arith
--                  ieee.std_logic_unsigned
--
-- Uses            : cpu11      (cpu11.vhd)     CPU core
--                   boot_rom   (swtbug11.vhd)  Monitor ROM
--                   dat_ram    (datram.vhd)    Dynamic Address Translation
--                   miniuart   (miniUART.vhd)  UART
--                      clkunit (clkunit.vhd)
--                      rxunit  (rxunit.vhd)
--                      txunit  (txunit.vhd)
--                   ioport     (ioport.vhd)    parallel i/o port
--                   timer      (timer.vhd)     small counter timer
--
-------------------------------------------------------------------------------
-- Revision list
-- Version   Author         Date                Changes
-- 1.0       John Kent      6 September 2003    Initial release to open corse
--
library ieee;
   use ieee.std_logic_1164.all;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
   use ieee.numeric_std.all;
 
entity System11 is
  port(
    SysClk      : in  Std_Logic;  -- System Clock input
         Reset_n     : in  Std_logic;  -- Master Reset input (active low)
    LED         : out std_logic;  -- Diagnostic LED Flasher
 
    -- Memory Interface signals
    ram_csn     : out Std_Logic;
    ram_wrln    : out Std_Logic;
    ram_wrun    : out Std_Logic;
    ram_addr    : out Std_Logic_Vector(16 downto 0);
    ram_data    : inout Std_Logic_Vector(15 downto 0);
 
         -- Stuff on the peripheral board
--  aux_clock   : in  Std_Logic;  -- FPGA-CPU-IO clock
 
         -- PS/2 Mouse interface
--       mouse_clock : in  Std_Logic;
--       mouse_data  : in  Std_Logic;
 
         -- Uart Interface
    rxbit       : in  Std_Logic;
         txbit       : out Std_Logic;
    rts_n       : out Std_Logic;
    cts_n       : in  Std_Logic;
 
         -- CRTC output signals
--       v_drive     : out Std_Logic;
--    h_drive     : out Std_Logic;
--    blue_lo     : out std_logic;
--    blue_hi     : out std_logic;
--    green_lo    : out std_logic;
--    green_hi    : out std_logic;
--    red_lo      : out std_logic;
--    red_hi      : out std_logic;
--       buzzer      : out std_logic;
 
-- I/O Ports
    PortA        : inout std_logic_vector(7 downto 0);
    PortB        : inout std_logic_vector(7 downto 0);
--    PortC        : inout std_logic_vector(7 downto 0);
--    PortD        : inout std_logic_vector(7 downto 0);
 
-- Timer I/O
         timer_out    : out std_logic;
 
    -- Compact Flash B5-CF Module
    cf_rst_n     : out std_logic;
         cf_cs0_n     : out std_logic;
         cf_cs1_n     : out std_logic;
    cf_rd_n      : out std_logic;
    cf_wr_n      : out std_logic;
         cf_cs16_n    : out std_logic;
    cf_a         : out std_logic_vector(2 downto 0);
    cf_d         : inout std_logic_vector(15 downto 0);
--    cf_intrq     : in std_logic;
--    cf_iordy     : in std_logic;
--      cf_dase      : in std_logic;
--         cf_pdiag     : in std_logic;
--         cf_present   : in std_logic;
 
-- test signals
         test_alu    : out std_logic_vector(15 downto 0);
         test_cc     : out std_logic_vector(7 downto 0)
         );
end;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture my_computer of System11 is
  -----------------------------------------------------------------------------
  -- Signals
  -----------------------------------------------------------------------------
  -- CPU Interface signals
  signal cpu_reset   : Std_Logic;
  signal cpu_clk     : Std_Logic;
  signal cpu_rw      : std_logic;
  signal cpu_vma     : std_logic;
  signal cpu_irq     : std_logic;
  signal cpu_xirq    : std_logic;
  signal cpu_addr    : Std_Logic_Vector(15 downto 0);
  signal cpu_data_in : Std_Logic_Vector(7 downto 0);
  signal cpu_data_out: Std_Logic_Vector(7 downto 0);
 
  -- BOOT ROM
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
 
  -- UART Interface signals
  signal uart_data_out : Std_Logic_Vector(7 downto 0);
  signal uart_cs       : Std_Logic;
  signal uart_irq      : Std_Logic;
 
  -- timer
  signal timer_data_out : std_logic_vector(7 downto 0);
  signal timer_cs    : std_logic;
  signal timer_irq   : std_logic;
 
  -- i/o port
  signal ioport_data_out : std_logic_vector(7 downto 0);
  signal ioport_cs   : std_logic;
 
  -- RAM
  signal ram_cs      : std_logic; -- memory chip select
  signal ram_wrl     : std_logic; -- memory write lower
  signal ram_wru     : std_logic; -- memory write upper
  signal ram_data_out    : std_logic_vector(7 downto 0);
 
  -- compact flash port
  signal cf_cs       : std_logic;
  signal cf_rd       : std_logic;
  signal cf_wr       : std_logic;
  signal cf_data_out : std_logic_vector(7 downto 0);
 
  -- Dynamic Address Translation RAM
  signal dat_cs      : std_logic;
  signal dat_data_out: std_logic_vector(7 downto 0);
 
  -- Flashing Led test signals
  signal countL      : std_logic_vector(23 downto 0);
 
 
-----------------------------------------------------------------
--
-- Open Cores Mini UART
--
-----------------------------------------------------------------
 
component miniUART
  port (
     SysClk   : in  Std_Logic;  -- System Clock
     rst      : in  Std_Logic;  -- Reset input
     cs       : in  Std_Logic;
     rw       : in  Std_Logic;
     RxD      : in  Std_Logic;
     TxD      : out Std_Logic;
     CTS_n    : in  Std_Logic;
     RTS_n    : out Std_Logic;
     Irq      : out Std_logic;
     Addr     : in  Std_Logic;
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- 
     DataOut  : out Std_Logic_Vector(7 downto 0)); -- 
end component;
 
--------------------------------------
--
-- Three port parallel I/O
--
---------------------------------------
 
component ioport
  port (
     clk      : in std_logic;
          rst      : in std_logic;
          cs       : in std_logic;
          rw       : in std_logic;
          addr     : in std_logic_vector(1 downto 0);
          data_in  : in std_logic_vector(7 downto 0);
          data_out : out std_logic_vector(7 downto 0);
          porta_io : inout std_logic_vector(7 downto 0);
          portb_io : inout std_logic_vector(7 downto 0)
          );
end component;
 
----------------------------------------
--
-- Timer module
--
----------------------------------------
 
component timer
  port (
     clk       : in std_logic;
          rst       : in std_logic;
          cs        : in std_logic;
          rw        : in std_logic;
          addr      : in std_logic;
          data_in   : in std_logic_vector(7 downto 0);
          data_out  : out std_logic_vector(7 downto 0);
          irq       : out std_logic;
     timer_in  : in std_logic;
          timer_out : out std_logic
          );
end component;
 
component cpu11
  port (
         clk:        in std_logic;
    rst:      in        std_logic;
    rw:      out        std_logic;              -- Asynchronous memory interface
    vma:             out        std_logic;
    address:  out       std_logic_vector(15 downto 0);
    data_in:  in        std_logic_vector(7 downto 0);
         data_out: out std_logic_vector(7 downto 0);
         irq:      in  std_logic;
         xirq:     in  std_logic;
         test_alu: out std_logic_vector(15 downto 0);
         test_cc:  out std_logic_vector(7 downto 0)
  );
end component;
 
component dat_ram
  port (
    clk:      in  std_logic;
         rst:      in  std_logic;
         cs:       in  std_logic;
         rw:       in  std_logic;
         addr_lo:  in  std_logic_vector(3 downto 0);
         addr_hi:  in  std_logic_vector(3 downto 0);
    data_in:  in  std_logic_vector(7 downto 0);
         data_out: out std_logic_vector(7 downto 0)
         );
end component;
 
component boot_rom
  port (
    addr  : in  Std_Logic_Vector(9 downto 0);  -- 1K byte boot rom
         data  : out Std_Logic_Vector(7 downto 0)
  );
end component;
 
-- component BUFG is 
--  port (
--     i: in std_logic;
--        o: out std_logic
--  );
-- end component;
 
begin
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
 
my_uart  : miniUART port map (
    SysClk    => SysClk,
         rst       => cpu_reset,
    cs        => uart_cs,
         rw        => cpu_rw,
         RxD       => rxbit,
         TxD       => txbit,
         CTS_n     => cts_n,
         RTS_n     => rts_n,
    Irq       => uart_irq,
    Addr      => cpu_addr(0),
         Datain    => cpu_data_out,
         DataOut   => uart_data_out
         );
 
my_ioport  : ioport port map (
    clk       => SysClk,
         rst       => cpu_reset,
    cs        => ioport_cs,
         rw        => cpu_rw,
    addr      => cpu_addr(1 downto 0),
         data_in   => cpu_data_out,
         data_out  => ioport_data_out,
         porta_io  => porta,
         portb_io  => portb
    );
 
my_timer  : timer port map (
    clk       => SysClk,
         rst       => cpu_reset,
    cs        => timer_cs,
         rw        => cpu_rw,
    addr      => cpu_addr(0),
         data_in   => cpu_data_out,
         data_out  => timer_data_out,
    irq       => timer_irq,
         timer_in  => CountL(5),
         timer_out => timer_out
    );
 
my_cpu : cpu11  port map (
         clk         => SysClk,
    rst       => cpu_reset,
    rw       => cpu_rw,
    vma       => cpu_vma,
    address   => cpu_addr(15 downto 0),
    data_in   => cpu_data_in,
         data_out  => cpu_data_out,
         irq       => cpu_irq,
         xirq      => cpu_xirq,
         test_alu  => test_alu,
         test_cc   => test_cc
  );
 
 
my_dat : dat_ram port map (
    clk        => SysClk,
         rst        => cpu_reset,
         cs         => dat_cs,
         rw         => cpu_rw,
         addr_hi    => cpu_addr(15 downto 12),
         addr_lo    => cpu_addr(3 downto 0),
    data_in    => cpu_data_out,
         data_out   => dat_data_out(7 downto 0)
         );
 
  rom : boot_rom port map (
         addr       => cpu_addr(9 downto 0),
    data       => rom_data_out
         );
 
--  clk_buffer : BUFG port map(
--    i => e_clk,
--       o => cpu_clk
--  );   
 
----------------------------------------------------------------------
--
--  Processes to read and write memory based on bus signals
--
----------------------------------------------------------------------
 
my_decoder: process(
                 cpu_addr, cpu_vma,
                                          rom_data_out, ram_data_out,
                                          ioport_data_out, timer_data_out, uart_data_out, cf_data_out )
begin
    case cpu_addr(15 downto 13) is
           --
                -- ROM & DAT Space $E000 - $FFFF
                --
                when "111" => -- $E000 - $FFFF
                   cpu_data_in <= rom_data_out;
                        dat_cs      <= cpu_vma;
                        ram_cs      <= '0';
                        uart_cs     <= '0';
                        cf_cs       <= '0';
                        timer_cs    <= '0';
                        ioport_cs   <= '0';
                --
                -- I/O Space at $8000 - $9FFF
                --
                when "100" => -- $8000 - $9FFF
                        dat_cs      <= '0';
                        ram_cs      <= '0';
                   case cpu_addr(6 downto 4) is
                        --
                        -- UART $8004
                        --
                        when "000" => -- $8000 - $800F
                     cpu_data_in <= uart_data_out;
                          uart_cs     <= cpu_vma;
                          cf_cs       <= '0';
                          timer_cs    <= '0';
                          ioport_cs   <= '0';
                        --
                        -- Compact Flash $8010
                        --
                        when "001" => -- $8010 - $801F
           cpu_data_in <= cf_data_out;
                          uart_cs     <= '0';
                          cf_cs       <= cpu_vma;
                          timer_cs    <= '0';
           ioport_cs   <= '0';
         --
                        -- Timer $8020
                        --
                        when "010" => -- $8020 - $802F
           cpu_data_in <= timer_data_out;
                          uart_cs     <= '0';
                          cf_cs       <= '0';
           timer_cs    <= cpu_vma;
                          ioport_cs   <= '0';
                        --
                        -- I/O Port $8030
                        --
                        when "011" => -- $8030 - $803F
           cpu_data_in <= ioport_data_out;
                          uart_cs     <= '0';
                          cf_cs       <= '0';
                          timer_cs    <= '0';
           ioport_cs   <= cpu_vma;
                        --
                        -- Empty
                        --
                        when others => -- $8040 to $9FFF
           cpu_data_in <= "00000000";
                          uart_cs     <= '0';
                          cf_cs       <= '0';
                          timer_cs    <= '0';
                          ioport_cs   <= '0';
                   end case;
                --
                -- The rest is all RAM
                --
                when others =>
                  cpu_data_in <= ram_data_out;
                  ram_cs      <= cpu_vma;
                  dat_cs      <= '0';
                  uart_cs     <= '0';
                  cf_cs       <= '0';
                  timer_cs    <= '0';
                  ioport_cs   <= '0';
         end case;
end process;
 
----------------------------------------------------------------------
--
--  Processes to read and write external RAM
--
----------------------------------------------------------------------
 
my_ram: process( SysClk, Reset_n,
                 cpu_addr, cpu_rw, cpu_data_out,
                 ram_cs, ram_wrl, ram_wru,
                                          ram_data, dat_data_out )
begin
    ram_csn <= not( ram_cs and Reset_n );
         ram_wrl  <= (not dat_data_out(5)) and (not cpu_rw) and SysClk;
         ram_wrln <= not ram_wrl;
    ram_wru  <= dat_data_out(5) and (not cpu_rw) and SysClk;
         ram_wrun <= not ram_wru;
         ram_addr(16 downto 12) <= dat_data_out(4 downto 0);
         ram_addr(11 downto 0) <= cpu_addr(11 downto 0);
 
    if ram_wrl = '1' then
                ram_data(7 downto 0) <= cpu_data_out;
         else
      ram_data(7 downto 0)  <= "ZZZZZZZZ";
         end if;
 
         if ram_wru = '1' then
                ram_data(15 downto 8) <= cpu_data_out;
         else
      ram_data(15 downto 8)  <= "ZZZZZZZZ";
    end if;
 
         if dat_data_out(5) = '1' then
      ram_data_out <= ram_data(15 downto 8);
         else
      ram_data_out <= ram_data(7 downto 0);
    end if;
end process;
 
 
--
-- B5-CF Compact Flash Control
--
b5_cf: process( Reset_n,
                cpu_addr, cpu_rw, cpu_data_out,
                                         cf_cs, cf_rd, cf_wr, cf_d )
begin
         cf_rst_n  <= Reset_n;
         cf_cs0_n  <= not( cf_cs ) or cpu_addr(3);
         cf_cs1_n  <= not( cf_cs and cpu_addr(3));
         cf_cs16_n <= '1';
         cf_wr     <= cf_cs and (not cpu_rw);
         cf_rd     <= cf_cs and cpu_rw;
         cf_wr_n   <= not cf_wr;
         cf_rd_n   <= not cf_rd;
         cf_a      <= cpu_addr(2 downto 0);
         if cf_wr = '1' then
           cf_d(7 downto 0) <= cpu_data_out;
         else
           cf_d(7 downto 0) <= "ZZZZZZZZ";
         end if;
         cf_data_out <= cf_d(7 downto 0);
         cf_d(15 downto 8) <= "ZZZZZZZZ";
end process;
 
--
-- tie together interrupts
--
interrupts : process( Reset_n, timer_irq, uart_irq )
begin
         cpu_reset <= not Reset_n; -- CPU reset is active high
    cpu_irq   <= uart_irq;
         cpu_xirq  <= timer_irq;
end process;
 
--
--
--clock_gen : process( SysClk, e_clk )
--begin
--  if SysClk'event and SysClk='0' then
--    e_clk <= not e_clk;
--  end if;
--end process;
 
  --
  -- flash led to indicate code is working
  --
  increment: process (SysClk, CountL )
  begin
    if(SysClk'event and SysClk = '0') then
      countL <= countL + 1;
    end if;
         LED <= countL(21);
  end process;
 
 
 
  --
  -- CRTC output signals
  --
--       v_drive     <= '0';
--    h_drive     <= '0';
--    blue_lo     <= '0';
--    blue_hi     <= '0';
--    green_lo    <= '0';
--    green_hi    <= '0';
--    red_lo      <= '0';
--    red_hi      <= '0';
--       buzzer      <= '0';
 
end my_computer; --===================== End of architecture =======================--
 

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Subversion Repositories System11

[/] [System11/] [trunk/] [rtl/] [vhdl/] [System11.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dilbert57	`--===========================================================================--`
2			`--`
3			`-- S Y N T H E Z I A B L E System11 - System on a Chip`
4			`--`
5			`-- www.OpenCores.Org - September 2003`
6			`-- This core adheres to the GNU public license`
7			`--`
8			`-- File name : system11.vhd`
9			`--`
10			`-- Entity name : system11`
11			`--`
12			`-- Purpose : SWTBUG Monitor modified for the 68HC11`
13			`-- ROM sits at $E000`
14			`-- Assumes an 6850 ACIA sits at $8004`
15			`-- Assumes RAM at $A000 - $BFFF for Flex 2`
16			`-- 1024 byte x 8 bit`
17			`-- Modified stack to allow for Y register`
18			`-- This SOC does not include any 68HC11`
19			`-- on chip peripherals`
20			`--`
21			`-- Dependencies : ieee.std_logic_1164`
22			`-- ieee.std_logic_arith`
23			`-- ieee.std_logic_unsigned`
24			`--`
25			`-- Uses : cpu11 (cpu11.vhd) CPU core`
26			`-- boot_rom (swtbug11.vhd) Monitor ROM`
27			`-- dat_ram (datram.vhd) Dynamic Address Translation`
28			`-- miniuart (miniUART.vhd) UART`
29			`-- clkunit (clkunit.vhd)`
30			`-- rxunit (rxunit.vhd)`
31			`-- txunit (txunit.vhd)`
32			`-- ioport (ioport.vhd) parallel i/o port`
33			`-- timer (timer.vhd) small counter timer`
34			`--`
35			`-------------------------------------------------------------------------------`
36			`-- Revision list`
37			`-- Version Author Date Changes`
38			`-- 1.0 John Kent 6 September 2003 Initial release to open corse`
39			`--`
40			`library ieee;`
41			`use ieee.std_logic_1164.all;`
42			`use IEEE.STD_LOGIC_ARITH.ALL;`
43			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
44			`use ieee.numeric_std.all;`
45
46			`entity System11 is`
47			`port(`
48			`SysClk : in Std_Logic; -- System Clock input`
49			`Reset_n : in Std_logic; -- Master Reset input (active low)`
50			`LED : out std_logic; -- Diagnostic LED Flasher`
51
52			`-- Memory Interface signals`
53			`ram_csn : out Std_Logic;`
54			`ram_wrln : out Std_Logic;`
55			`ram_wrun : out Std_Logic;`
56			`ram_addr : out Std_Logic_Vector(16 downto 0);`
57			`ram_data : inout Std_Logic_Vector(15 downto 0);`
58
59			`-- Stuff on the peripheral board`
60			`-- aux_clock : in Std_Logic; -- FPGA-CPU-IO clock`
61
62			`-- PS/2 Mouse interface`
63			`-- mouse_clock : in Std_Logic;`
64			`-- mouse_data : in Std_Logic;`
65
66			`-- Uart Interface`
67			`rxbit : in Std_Logic;`
68			`txbit : out Std_Logic;`
69			`rts_n : out Std_Logic;`
70			`cts_n : in Std_Logic;`
71
72			`-- CRTC output signals`
73			`-- v_drive : out Std_Logic;`
74			`-- h_drive : out Std_Logic;`
75			`-- blue_lo : out std_logic;`
76			`-- blue_hi : out std_logic;`
77			`-- green_lo : out std_logic;`
78			`-- green_hi : out std_logic;`
79			`-- red_lo : out std_logic;`
80			`-- red_hi : out std_logic;`
81			`-- buzzer : out std_logic;`
82
83			`-- I/O Ports`
84			`PortA : inout std_logic_vector(7 downto 0);`
85			`PortB : inout std_logic_vector(7 downto 0);`
86			`-- PortC : inout std_logic_vector(7 downto 0);`
87			`-- PortD : inout std_logic_vector(7 downto 0);`
88
89			`-- Timer I/O`
90			`timer_out : out std_logic;`
91
92			`-- Compact Flash B5-CF Module`
93			`cf_rst_n : out std_logic;`
94			`cf_cs0_n : out std_logic;`
95			`cf_cs1_n : out std_logic;`
96			`cf_rd_n : out std_logic;`
97			`cf_wr_n : out std_logic;`
98			`cf_cs16_n : out std_logic;`
99			`cf_a : out std_logic_vector(2 downto 0);`
100			`cf_d : inout std_logic_vector(15 downto 0);`
101			`-- cf_intrq : in std_logic;`
102			`-- cf_iordy : in std_logic;`
103			`-- cf_dase : in std_logic;`
104			`-- cf_pdiag : in std_logic;`
105			`-- cf_present : in std_logic;`
106
107			`-- test signals`
108			`test_alu : out std_logic_vector(15 downto 0);`
109			`test_cc : out std_logic_vector(7 downto 0)`
110			`);`
111			`end;`
112
113			`-------------------------------------------------------------------------------`
114			`-- Architecture for memio Controller Unit`
115			`-------------------------------------------------------------------------------`
116			`architecture my_computer of System11 is`
117			`-----------------------------------------------------------------------------`
118			`-- Signals`
119			`-----------------------------------------------------------------------------`
120			`-- CPU Interface signals`
121			`signal cpu_reset : Std_Logic;`
122			`signal cpu_clk : Std_Logic;`
123			`signal cpu_rw : std_logic;`
124			`signal cpu_vma : std_logic;`
125			`signal cpu_irq : std_logic;`
126			`signal cpu_xirq : std_logic;`
127			`signal cpu_addr : Std_Logic_Vector(15 downto 0);`
128			`signal cpu_data_in : Std_Logic_Vector(7 downto 0);`
129			`signal cpu_data_out: Std_Logic_Vector(7 downto 0);`
130
131			`-- BOOT ROM`
132			`signal rom_data_out : Std_Logic_Vector(7 downto 0);`
133
134			`-- UART Interface signals`
135			`signal uart_data_out : Std_Logic_Vector(7 downto 0);`
136			`signal uart_cs : Std_Logic;`
137			`signal uart_irq : Std_Logic;`
138
139			`-- timer`
140			`signal timer_data_out : std_logic_vector(7 downto 0);`
141			`signal timer_cs : std_logic;`
142			`signal timer_irq : std_logic;`
143
144			`-- i/o port`
145			`signal ioport_data_out : std_logic_vector(7 downto 0);`
146			`signal ioport_cs : std_logic;`
147
148			`-- RAM`
149			`signal ram_cs : std_logic; -- memory chip select`
150			`signal ram_wrl : std_logic; -- memory write lower`
151			`signal ram_wru : std_logic; -- memory write upper`
152			`signal ram_data_out : std_logic_vector(7 downto 0);`
153
154			`-- compact flash port`
155			`signal cf_cs : std_logic;`
156			`signal cf_rd : std_logic;`
157			`signal cf_wr : std_logic;`
158			`signal cf_data_out : std_logic_vector(7 downto 0);`
159
160			`-- Dynamic Address Translation RAM`
161			`signal dat_cs : std_logic;`
162			`signal dat_data_out: std_logic_vector(7 downto 0);`
163
164			`-- Flashing Led test signals`
165			`signal countL : std_logic_vector(23 downto 0);`
166
167
168			`-----------------------------------------------------------------`
169			`--`
170			`-- Open Cores Mini UART`
171			`--`
172			`-----------------------------------------------------------------`
173
174			`component miniUART`
175			`port (`
176			`SysClk : in Std_Logic; -- System Clock`
177			`rst : in Std_Logic; -- Reset input`
178			`cs : in Std_Logic;`
179			`rw : in Std_Logic;`
180			`RxD : in Std_Logic;`
181			`TxD : out Std_Logic;`
182			`CTS_n : in Std_Logic;`
183			`RTS_n : out Std_Logic;`
184			`Irq : out Std_logic;`
185			`Addr : in Std_Logic;`
186			`DataIn : in Std_Logic_Vector(7 downto 0); --`
187			`DataOut : out Std_Logic_Vector(7 downto 0)); --`
188			`end component;`
189
190			`--------------------------------------`
191			`--`
192			`-- Three port parallel I/O`
193			`--`
194			`---------------------------------------`
195
196			`component ioport`
197			`port (`
198			`clk : in std_logic;`
199			`rst : in std_logic;`
200			`cs : in std_logic;`
201			`rw : in std_logic;`
202			`addr : in std_logic_vector(1 downto 0);`
203			`data_in : in std_logic_vector(7 downto 0);`
204			`data_out : out std_logic_vector(7 downto 0);`
205			`porta_io : inout std_logic_vector(7 downto 0);`
206			`portb_io : inout std_logic_vector(7 downto 0)`
207			`);`
208			`end component;`
209
210			`----------------------------------------`
211			`--`
212			`-- Timer module`
213			`--`
214			`----------------------------------------`
215
216			`component timer`
217			`port (`
218			`clk : in std_logic;`
219			`rst : in std_logic;`
220			`cs : in std_logic;`
221			`rw : in std_logic;`
222			`addr : in std_logic;`
223			`data_in : in std_logic_vector(7 downto 0);`
224			`data_out : out std_logic_vector(7 downto 0);`
225			`irq : out std_logic;`
226			`timer_in : in std_logic;`
227			`timer_out : out std_logic`
228			`);`
229			`end component;`
230
231			`component cpu11`
232			`port (`
233			`clk: in std_logic;`
234			`rst: in std_logic;`
235			`rw: out std_logic; -- Asynchronous memory interface`
236			`vma: out std_logic;`
237			`address: out std_logic_vector(15 downto 0);`
238			`data_in: in std_logic_vector(7 downto 0);`
239			`data_out: out std_logic_vector(7 downto 0);`
240			`irq: in std_logic;`
241			`xirq: in std_logic;`
242			`test_alu: out std_logic_vector(15 downto 0);`
243			`test_cc: out std_logic_vector(7 downto 0)`
244			`);`
245			`end component;`
246
247			`component dat_ram`
248			`port (`
249			`clk: in std_logic;`
250			`rst: in std_logic;`
251			`cs: in std_logic;`
252			`rw: in std_logic;`
253			`addr_lo: in std_logic_vector(3 downto 0);`
254			`addr_hi: in std_logic_vector(3 downto 0);`
255			`data_in: in std_logic_vector(7 downto 0);`
256			`data_out: out std_logic_vector(7 downto 0)`
257			`);`
258			`end component;`
259
260			`component boot_rom`
261			`port (`
262			`addr : in Std_Logic_Vector(9 downto 0); -- 1K byte boot rom`
263			`data : out Std_Logic_Vector(7 downto 0)`
264			`);`
265			`end component;`
266
267			`-- component BUFG is`
268			`-- port (`
269			`-- i: in std_logic;`
270			`-- o: out std_logic`
271			`-- );`
272			`-- end component;`
273
274			`begin`
275			`-----------------------------------------------------------------------------`
276			`-- Instantiation of internal components`
277			`-----------------------------------------------------------------------------`
278
279			`my_uart : miniUART port map (`
280			`SysClk => SysClk,`
281			`rst => cpu_reset,`
282			`cs => uart_cs,`
283			`rw => cpu_rw,`
284			`RxD => rxbit,`
285			`TxD => txbit,`
286			`CTS_n => cts_n,`
287			`RTS_n => rts_n,`
288			`Irq => uart_irq,`
289			`Addr => cpu_addr(0),`
290			`Datain => cpu_data_out,`
291			`DataOut => uart_data_out`
292			`);`
293
294			`my_ioport : ioport port map (`
295			`clk => SysClk,`
296			`rst => cpu_reset,`
297			`cs => ioport_cs,`
298			`rw => cpu_rw,`
299			`addr => cpu_addr(1 downto 0),`
300			`data_in => cpu_data_out,`
301			`data_out => ioport_data_out,`
302			`porta_io => porta,`
303			`portb_io => portb`
304			`);`
305
306			`my_timer : timer port map (`
307			`clk => SysClk,`
308			`rst => cpu_reset,`
309			`cs => timer_cs,`
310			`rw => cpu_rw,`
311			`addr => cpu_addr(0),`
312			`data_in => cpu_data_out,`
313			`data_out => timer_data_out,`
314			`irq => timer_irq,`
315			`timer_in => CountL(5),`
316			`timer_out => timer_out`
317			`);`
318
319			`my_cpu : cpu11 port map (`
320			`clk => SysClk,`
321			`rst => cpu_reset,`
322			`rw => cpu_rw,`
323			`vma => cpu_vma,`
324			`address => cpu_addr(15 downto 0),`
325			`data_in => cpu_data_in,`
326			`data_out => cpu_data_out,`
327			`irq => cpu_irq,`
328			`xirq => cpu_xirq,`
329			`test_alu => test_alu,`
330			`test_cc => test_cc`
331			`);`
332
333
334			`my_dat : dat_ram port map (`
335			`clk => SysClk,`
336			`rst => cpu_reset,`
337			`cs => dat_cs,`
338			`rw => cpu_rw,`
339			`addr_hi => cpu_addr(15 downto 12),`
340			`addr_lo => cpu_addr(3 downto 0),`
341			`data_in => cpu_data_out,`
342			`data_out => dat_data_out(7 downto 0)`
343			`);`
344
345			`rom : boot_rom port map (`
346			`addr => cpu_addr(9 downto 0),`
347			`data => rom_data_out`
348			`);`
349
350			`-- clk_buffer : BUFG port map(`
351			`-- i => e_clk,`
352			`-- o => cpu_clk`
353			`-- );`
354
355			`----------------------------------------------------------------------`
356			`--`
357			`-- Processes to read and write memory based on bus signals`
358			`--`
359			`----------------------------------------------------------------------`
360
361			`my_decoder: process(`
362			`cpu_addr, cpu_vma,`
363			`rom_data_out, ram_data_out,`
364			`ioport_data_out, timer_data_out, uart_data_out, cf_data_out )`
365			`begin`
366			`case cpu_addr(15 downto 13) is`
367			`--`
368			`-- ROM & DAT Space $E000 - $FFFF`
369			`--`
370			`when "111" => -- $E000 - $FFFF`
371			`cpu_data_in <= rom_data_out;`
372			`dat_cs <= cpu_vma;`
373			`ram_cs <= '0';`
374			`uart_cs <= '0';`
375			`cf_cs <= '0';`
376			`timer_cs <= '0';`
377			`ioport_cs <= '0';`
378			`--`
379			`-- I/O Space at $8000 - $9FFF`
380			`--`
381			`when "100" => -- $8000 - $9FFF`
382			`dat_cs <= '0';`
383			`ram_cs <= '0';`
384			`case cpu_addr(6 downto 4) is`
385			`--`
386			`-- UART $8004`
387			`--`
388			`when "000" => -- $8000 - $800F`
389			`cpu_data_in <= uart_data_out;`
390			`uart_cs <= cpu_vma;`
391			`cf_cs <= '0';`
392			`timer_cs <= '0';`
393			`ioport_cs <= '0';`
394			`--`
395			`-- Compact Flash $8010`
396			`--`
397			`when "001" => -- $8010 - $801F`
398			`cpu_data_in <= cf_data_out;`
399			`uart_cs <= '0';`
400			`cf_cs <= cpu_vma;`
401			`timer_cs <= '0';`
402			`ioport_cs <= '0';`
403			`--`
404			`-- Timer $8020`
405			`--`
406			`when "010" => -- $8020 - $802F`
407			`cpu_data_in <= timer_data_out;`
408			`uart_cs <= '0';`
409			`cf_cs <= '0';`
410			`timer_cs <= cpu_vma;`
411			`ioport_cs <= '0';`
412			`--`
413			`-- I/O Port $8030`
414			`--`
415			`when "011" => -- $8030 - $803F`
416			`cpu_data_in <= ioport_data_out;`
417			`uart_cs <= '0';`
418			`cf_cs <= '0';`
419			`timer_cs <= '0';`
420			`ioport_cs <= cpu_vma;`
421			`--`
422			`-- Empty`
423			`--`
424			`when others => -- $8040 to $9FFF`
425			`cpu_data_in <= "00000000";`
426			`uart_cs <= '0';`
427			`cf_cs <= '0';`
428			`timer_cs <= '0';`
429			`ioport_cs <= '0';`
430			`end case;`
431			`--`
432			`-- The rest is all RAM`
433			`--`
434			`when others =>`
435			`cpu_data_in <= ram_data_out;`
436			`ram_cs <= cpu_vma;`
437			`dat_cs <= '0';`
438			`uart_cs <= '0';`
439			`cf_cs <= '0';`
440			`timer_cs <= '0';`
441			`ioport_cs <= '0';`
442			`end case;`
443			`end process;`
444
445			`----------------------------------------------------------------------`
446			`--`
447			`-- Processes to read and write external RAM`
448			`--`
449			`----------------------------------------------------------------------`
450
451			`my_ram: process( SysClk, Reset_n,`
452			`cpu_addr, cpu_rw, cpu_data_out,`
453			`ram_cs, ram_wrl, ram_wru,`
454			`ram_data, dat_data_out )`
455			`begin`
456			`ram_csn <= not( ram_cs and Reset_n );`
457			`ram_wrl <= (not dat_data_out(5)) and (not cpu_rw) and SysClk;`
458			`ram_wrln <= not ram_wrl;`
459			`ram_wru <= dat_data_out(5) and (not cpu_rw) and SysClk;`
460			`ram_wrun <= not ram_wru;`
461			`ram_addr(16 downto 12) <= dat_data_out(4 downto 0);`
462			`ram_addr(11 downto 0) <= cpu_addr(11 downto 0);`
463
464			`if ram_wrl = '1' then`
465			`ram_data(7 downto 0) <= cpu_data_out;`
466			`else`
467			`ram_data(7 downto 0) <= "ZZZZZZZZ";`
468			`end if;`
469
470			`if ram_wru = '1' then`
471			`ram_data(15 downto 8) <= cpu_data_out;`
472			`else`
473			`ram_data(15 downto 8) <= "ZZZZZZZZ";`
474			`end if;`
475
476			`if dat_data_out(5) = '1' then`
477			`ram_data_out <= ram_data(15 downto 8);`
478			`else`
479			`ram_data_out <= ram_data(7 downto 0);`
480			`end if;`
481			`end process;`
482
483
484			`--`
485			`-- B5-CF Compact Flash Control`
486			`--`
487			`b5_cf: process( Reset_n,`
488			`cpu_addr, cpu_rw, cpu_data_out,`
489			`cf_cs, cf_rd, cf_wr, cf_d )`
490			`begin`
491			`cf_rst_n <= Reset_n;`
492			`cf_cs0_n <= not( cf_cs ) or cpu_addr(3);`
493			`cf_cs1_n <= not( cf_cs and cpu_addr(3));`
494			`cf_cs16_n <= '1';`
495			`cf_wr <= cf_cs and (not cpu_rw);`
496			`cf_rd <= cf_cs and cpu_rw;`
497			`cf_wr_n <= not cf_wr;`
498			`cf_rd_n <= not cf_rd;`
499			`cf_a <= cpu_addr(2 downto 0);`
500			`if cf_wr = '1' then`
501			`cf_d(7 downto 0) <= cpu_data_out;`
502			`else`
503			`cf_d(7 downto 0) <= "ZZZZZZZZ";`
504			`end if;`
505			`cf_data_out <= cf_d(7 downto 0);`
506			`cf_d(15 downto 8) <= "ZZZZZZZZ";`
507			`end process;`
508
509			`--`
510			`-- tie together interrupts`
511			`--`
512			`interrupts : process( Reset_n, timer_irq, uart_irq )`
513			`begin`
514			`cpu_reset <= not Reset_n; -- CPU reset is active high`
515			`cpu_irq <= uart_irq;`
516			`cpu_xirq <= timer_irq;`
517			`end process;`
518
519			`--`
520			`--`
521			`--clock_gen : process( SysClk, e_clk )`
522			`--begin`
523			`-- if SysClk'event and SysClk='0' then`
524			`-- e_clk <= not e_clk;`
525			`-- end if;`
526			`--end process;`
527
528			`--`
529			`-- flash led to indicate code is working`
530			`--`
531			`increment: process (SysClk, CountL )`
532			`begin`
533			`if(SysClk'event and SysClk = '0') then`
534			`countL <= countL + 1;`
535			`end if;`
536			`LED <= countL(21);`
537			`end process;`
538
539
540
541			`--`
542			`-- CRTC output signals`
543			`--`
544			`-- v_drive <= '0';`
545			`-- h_drive <= '0';`
546			`-- blue_lo <= '0';`
547			`-- blue_hi <= '0';`
548			`-- green_lo <= '0';`
549			`-- green_hi <= '0';`
550			`-- red_lo <= '0';`
551			`-- red_hi <= '0';`
552			`-- buzzer <= '0';`
553
554			`end my_computer; --===================== End of architecture =======================--`
555