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1 2 dilbert57 
--===========================================================================--
2 
--
3 
--  S Y N T H E Z I A B L E    cpu11 - HC11 compatible CPU core
4 
--
5 
--  www.OpenCores.Org - September 2003
6 
--  This core adheres to the GNU public license
7 
--
8 
-- File name      : cpu11.vhd
9 
--
10 
-- Entity name    : cpu11
11 
--
12 
-- Purpose        : HC11 instruction set compatible CPU core
13 
--
14 
-- Dependencies   : ieee.std_logic_1164
15 
--                  ieee.std_logic_unsigned
16 
--
17 
-- Uses           : Nothing
18 
--
19 
-- Author         : John Kent - dilbert57@opencores.org
20 
--
21 
-------------------------------------------------------------------------------
22 
-- Revision list
23 
--
24 
-- Version 0.1 - 13 November 2002 - John Kent
25 
-- revamped 6801 CPU into 68HC11 CPU.
26 
-- Added Y index register
27 
-- Added Y indexing prebyte
28 
-- Added CMPD with prebyte
29 
-- Added bit operators
30 
-- Updated stack operations
31 
--
32 
-- Version 0.3 - 15 December 2002 - John Kent
33 
-- implemented FDIV
34 
-- implemented IDIV
35 
--
36 
-- Version 1.0 - 7 September 2003 - John Kent
37 
-- Released to Open Cores
38 
-- Basic 6800 instructions working
39 
-- but not Divide and bit operations.
40 
--
41 4 dilbert57 
-- Version 1.1 - 4 April 2004
42 
-- Removed Test_alu and Test_cc signals
43 
--      Moved Dual operand execution into fetch state
44 
-- Fixed Indexed bit operators
45 
--
46 2 dilbert57 
 
47 
library ieee;
48 
use ieee.std_logic_1164.all;
49 
use ieee.std_logic_unsigned.all;
50 
 
51 
entity cpu11 is
52 
        port (
53 
                clk:        in  std_logic;
54 
                rst:        in  std_logic;
55 
                rw:         out std_logic;
56 
                vma:        out std_logic;
57 
                address:         out std_logic_vector(15 downto 0);
58 
           data_in:      in  std_logic_vector(7 downto 0);
59 
           data_out: out std_logic_vector(7 downto 0);
60 
                irq:      in  std_logic;
61 4 dilbert57 
                xirq:     in  std_logic
62 2 dilbert57 
                );
63 
end;
64 
 
65 
architecture CPU_ARCH of cpu11 is
66 
 
67 
  constant SBIT : integer := 7;
68 
  constant XBIT : integer := 6;
69 
  constant HBIT : integer := 5;
70 
  constant IBIT : integer := 4;
71 
  constant NBIT : integer := 3;
72 
  constant ZBIT : integer := 2;
73 
  constant VBIT : integer := 1;
74 
  constant CBIT : integer := 0;
75 
 
76 
        type state_type is (reset_state, fetch_state, decode_state,
77 4 dilbert57 
                       extended_state, indexed_state, read8_state, read16_state, immediate16_state,
78 2 dilbert57 
                            write8_state, write16_state,
79 
                                                     execute_state, halt_state, spin_state,
80 4 dilbert57 
                                                     exchange_state,
81 2 dilbert57 
                                                     mul_state, mulea_state, muld_state, mul0_state,
82 
                                                          idiv_state,
83 
                                                          div1_state, div2_state, div3_state, div4_state, div5_state,
84 
                                                          jmp_state, jsr_state, jsr1_state,
85 
                                                     branch_state, bsr_state, bsr1_state,
86 4 dilbert57 
                                                          bitmask_state, brset_state, brclr_state,
87 2 dilbert57 
                                                          rts_hi_state, rts_lo_state,
88 
                                                          int_pcl_state, int_pch_state,
89 
                                                     int_ixl_state, int_ixh_state,
90 
                                                     int_iyl_state, int_iyh_state,
91 
                                                     int_cc_state, int_acca_state, int_accb_state,
92 
                                                     int_wai_state, int_maski_state, int_maskx_state,
93 
                                                     rti_state, rti_cc_state, rti_acca_state, rti_accb_state,
94 
                                                     rti_ixl_state, rti_ixh_state,
95 
                                                     rti_iyl_state, rti_iyh_state,
96 
                                                     rti_pcl_state, rti_pch_state,
97 
                                                          pula_state, psha_state, pulb_state, pshb_state,
98 4 dilbert57 
                                                     pulxy_lo_state, pulxy_hi_state, pshxy_lo_state, pshxy_hi_state,
99 2 dilbert57 
                                                          vect_lo_state, vect_hi_state );
100 
        type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, push_ad, pull_ad, int_hi_ad, int_lo_ad );
101 
        type dout_type is ( acca_dout, accb_dout, cc_dout,
102 
                       ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
103 
                                                          md_lo_dout, md_hi_dout, pc_lo_dout, pc_hi_dout );
104 
   type op_type is (reset_op, fetch_op, latch_op );
105 
   type pre_type is (reset_pre, fetch_pre, latch_pre );
106 
   type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
107 
   type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
108 
   type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
109 
        type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
110 
        type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
111 
        type sp_type is (reset_sp, latch_sp, load_sp );
112 4 dilbert57 
        type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
113 2 dilbert57 
   type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
114 4 dilbert57 
   type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea, add_ix_ea, add_iy_ea );
115 2 dilbert57 
        type iv_type is (reset_iv, latch_iv, swi_iv, xirq_iv, irq_iv );
116 
        type count_type is (reset_count, latch_count, inc_count );
117 
        type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, iy_left, pc_left, sp_left, ea_left );
118 
        type right_type is (md_right, zero_right, one_right, accb_right, pre_right, ea_right, sexea_right );
119 
   type alu_type   is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
120 
                       alu_and, alu_ora, alu_eor,
121 
                       alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
122 
                                                          alu_inc16, alu_dec16,
123 
                                                     alu_lsr16, alu_lsl16,
124 
                                                     alu_ror8, alu_rol8, alu_rol16,
125 
                                                     alu_asr8, alu_asl8, alu_lsr8,
126 
                                                     alu_sei, alu_cli, alu_sec, alu_clc, alu_sev, alu_clv,
127 
                                                     alu_sex, alu_clx, alu_tpa, alu_tap,
128 
                                                     alu_ld8, alu_st8, alu_ld16, alu_st16, alu_nop, alu_daa,
129 
                                                     alu_bset, alu_bclr );
130 
 
131 
        signal op_code:     std_logic_vector(7 downto 0);
132 
        signal pre_byte:    std_logic_vector(7 downto 0);
133 
        signal acca:        std_logic_vector(7 downto 0);
134 
        signal accb:        std_logic_vector(7 downto 0);
135 
   signal cc:          std_logic_vector(7 downto 0);
136 
        signal cc_out:      std_logic_vector(7 downto 0);
137 
        signal xreg:        std_logic_vector(15 downto 0);
138 
        signal yreg:        std_logic_vector(15 downto 0);
139 
        signal sp:          std_logic_vector(15 downto 0);
140 
        signal ea:          std_logic_vector(15 downto 0);
141 
        signal pc:              std_logic_vector(15 downto 0);
142 
        signal md:          std_logic_vector(15 downto 0);
143 
   signal left:        std_logic_vector(15 downto 0);
144 
   signal right:       std_logic_vector(15 downto 0);
145 
        signal out_alu:     std_logic_vector(15 downto 0);
146 
        signal iv:          std_logic_vector(1 downto 0);
147 
        signal ea_bit:      std_logic;
148 
        signal count:       std_logic_vector(4 downto 0);
149 
 
150 
        signal state:       state_type;
151 
        signal next_state:  state_type;
152 
   signal pc_ctrl:     pc_type;
153 
   signal ea_ctrl:     ea_type;
154 
   signal op_ctrl:     op_type;
155 
   signal pre_ctrl:    pre_type;
156 
        signal md_ctrl:     md_type;
157 
        signal acca_ctrl:   acca_type;
158 
        signal accb_ctrl:   accb_type;
159 
        signal ix_ctrl:     ix_type;
160 
        signal iy_ctrl:     iy_type;
161 
        signal cc_ctrl:     cc_type;
162 
        signal sp_ctrl:     sp_type;
163 
        signal iv_ctrl:     iv_type;
164 
        signal left_ctrl:   left_type;
165 
        signal right_ctrl:  right_type;
166 
   signal alu_ctrl:    alu_type;
167 
   signal addr_ctrl:   addr_type;
168 
   signal dout_ctrl:   dout_type;
169 
   signal count_ctrl:  count_type;
170 
 
171 
 
172 
begin
173 
 
174 
--------------------------------
175 
--
176 
-- Accumulator A
177 
--
178 
--------------------------------
179 
acca_reg : process( clk, acca_ctrl, out_alu, acca, data_in )
180 
begin
181 
  if clk'event and clk = '0' then
182 
    case acca_ctrl is
183 
    when reset_acca =>
184 
           acca <= "00000000";
185 
         when load_acca =>
186 
           acca <= out_alu(7 downto 0);
187 
         when load_hi_acca =>
188 
           acca <= out_alu(15 downto 8);
189 
         when pull_acca =>
190 
           acca <= data_in;
191 
         when others =>
192 
--       when latch_acca =>
193 
           acca <= acca;
194 
    end case;
195 
  end if;
196 
end process;
197 
 
198 
--------------------------------
199 
--
200 
-- Accumulator B
201 
--
202 
--------------------------------
203 
accb_reg : process( clk, accb_ctrl, out_alu, accb, data_in )
204 
begin
205 
  if clk'event and clk = '0' then
206 
    case accb_ctrl is
207 
    when reset_accb =>
208 
           accb <= "00000000";
209 
         when load_accb =>
210 
           accb <= out_alu(7 downto 0);
211 
         when pull_accb =>
212 
           accb <= data_in;
213 
         when others =>
214 
--       when latch_accb =>
215 
           accb <= accb;
216 
    end case;
217 
  end if;
218 
end process;
219 
 
220 
----------------------------------
221 
--
222 
-- Condition Codes
223 
--
224 
----------------------------------
225 
 
226 
cc_reg: process( clk, cc_ctrl, cc_out, cc, data_in )
227 
begin
228 
  if clk'event and clk = '0' then
229 
    case cc_ctrl is
230 
         when reset_cc =>
231 
           cc <= "11000000";
232 
         when load_cc =>
233 
           cc <= cc_out;
234 
         when pull_cc =>
235 
      cc <= data_in;
236 
         when others =>
237 
--  when latch_cc =>
238 
      cc <= cc;
239 
    end case;
240 
  end if;
241 
end process;
242 
 
243 
--------------------------------
244 
--
245 
-- X Index register
246 
--
247 
--------------------------------
248 
ix_reg : process( clk, ix_ctrl, out_alu, xreg, data_in )
249 
begin
250 
  if clk'event and clk = '0' then
251 
    case ix_ctrl is
252 
    when reset_ix =>
253 
           xreg <= "0000000000000000";
254 
         when load_ix =>
255 
           xreg <= out_alu(15 downto 0);
256 
         when pull_hi_ix =>
257 
           xreg(15 downto 8) <= data_in;
258 
         when pull_lo_ix =>
259 
           xreg(7 downto 0) <= data_in;
260 
         when others =>
261 
--       when latch_ix =>
262 
           xreg <= xreg;
263 
    end case;
264 
  end if;
265 
end process;
266 
 
267 
--------------------------------
268 
--
269 
-- Y Index register
270 
--
271 
--------------------------------
272 
iy_reg : process( clk, iy_ctrl, out_alu, yreg, data_in )
273 
begin
274 
  if clk'event and clk = '0' then
275 
    case iy_ctrl is
276 
    when reset_iy =>
277 
           yreg <= "0000000000000000";
278 
         when load_iy =>
279 
           yreg <= out_alu(15 downto 0);
280 
         when pull_hi_iy =>
281 
           yreg(15 downto 8) <= data_in;
282 
         when pull_lo_iy =>
283 
           yreg(7 downto 0) <= data_in;
284 
         when others =>
285 
--       when latch_iy =>
286 
           yreg <= yreg;
287 
    end case;
288 
  end if;
289 
end process;
290 
 
291 
--------------------------------
292 
--
293 
-- stack pointer
294 
--
295 
--------------------------------
296 
sp_reg : process( clk, sp_ctrl, out_alu )
297 
begin
298 
  if clk'event and clk = '0' then
299 
    case sp_ctrl is
300 
    when reset_sp =>
301 
           sp <= "0000000000000000";
302 
         when load_sp =>
303 
           sp <= out_alu(15 downto 0);
304 
         when others =>
305 
--       when latch_sp =>
306 
           sp <= sp;
307 
    end case;
308 
  end if;
309 
end process;
310 
 
311 
----------------------------------
312 
--
313 
-- Program Counter Control
314 
--
315 
----------------------------------
316 
 
317 
pc_reg: process( clk, pc_ctrl, pc, out_alu, data_in )
318 
begin
319 
  if clk'event and clk = '0' then
320 
    case pc_ctrl is
321 
         when reset_pc =>
322 
           pc <= "0000000000000000";
323 4 dilbert57 
         when incr_pc =>
324 
           pc <= pc + "0000000000000001";
325 2 dilbert57 
         when load_pc =>
326 
           pc <= out_alu(15 downto 0);
327 
         when pull_lo_pc =>
328 
           pc(7 downto 0) <= data_in;
329 
         when pull_hi_pc =>
330 
           pc(15 downto 8) <= data_in;
331 
         when others =>
332 
--       when latch_pc =>
333 
      pc <= pc;
334 
    end case;
335 
  end if;
336 
end process;
337 
 
338 
----------------------------------
339 
--
340 
-- Effective Address  Control
341 
--
342 
----------------------------------
343 
 
344 4 dilbert57 
ea_reg: process( clk, ea_ctrl, ea, out_alu, data_in, xreg, yreg )
345 2 dilbert57 
begin
346 
 
347 
  if clk'event and clk = '0' then
348 
    case ea_ctrl is
349 
         when reset_ea =>
350 
           ea <= "0000000000000000";
351 
         when fetch_first_ea =>
352 
           ea(7 downto 0) <= data_in;
353 
      ea(15 downto 8) <= "00000000";
354 
         when fetch_next_ea =>
355 
           ea(15 downto 8) <= ea(7 downto 0);
356 
      ea(7 downto 0)  <= data_in;
357 4 dilbert57 
    when add_ix_ea =>
358 
           ea <= ea + xreg;
359 
    when add_iy_ea =>
360 
           ea <= ea + yreg;
361 2 dilbert57 
         when load_ea =>
362 
           ea <= out_alu(15 downto 0);
363 
         when others =>
364 
--       when latch_ea =>
365 
      ea <= ea;
366 
    end case;
367 
  end if;
368 
end process;
369 
 
370 
--------------------------------
371 
--
372 
-- Memory Data
373 
--
374 
--------------------------------
375 
md_reg : process( clk, md_ctrl, out_alu, data_in, md )
376 
begin
377 
  if clk'event and clk = '0' then
378 
    case md_ctrl is
379 
    when reset_md =>
380 
           md <= "0000000000000000";
381 
         when load_md =>
382 
           md <= out_alu(15 downto 0);
383 
         when fetch_first_md =>
384 
           md(15 downto 8) <= "00000000";
385 
           md(7 downto 0) <= data_in;
386 
         when fetch_next_md =>
387 
           md(15 downto 8) <= md(7 downto 0);
388 
                md(7 downto 0) <= data_in;
389 
         when shiftl_md =>
390 
           md(15 downto 1) <= md(14 downto 0);
391 
                md(0) <= '0';
392 
         when others =>
393 
--       when latch_md =>
394 
           md <= md;
395 
    end case;
396 
  end if;
397 
end process;
398 
 
399 
----------------------------------
400 
--
401 
-- interrupt vector
402 
--
403 
----------------------------------
404 
 
405 
iv_reg: process( clk, iv_ctrl )
406 
begin
407 
  if clk'event and clk = '0' then
408 
    case iv_ctrl is
409 
         when reset_iv =>
410 
           iv <= "11";
411 
         when xirq_iv =>
412 
      iv <= "10";
413 
         when swi_iv =>
414 
      iv <= "01";
415 
         when irq_iv =>
416 
      iv <= "00";
417 
         when others =>
418 
           iv <= iv;
419 
    end case;
420 
  end if;
421 
end process;
422 
 
423 
----------------------------------
424 
--
425 
-- op code register
426 
--
427 
----------------------------------
428 
 
429 
op_reg: process( clk, data_in, op_ctrl, op_code )
430 
begin
431 
  if clk'event and clk = '0' then
432 
    case op_ctrl is
433 
         when reset_op =>
434 4 dilbert57 
           op_code <= "00000001";       -- nop
435 2 dilbert57 
         when fetch_op =>
436 
      op_code <= data_in;
437 
         when others =>
438 
--       when latch_op =>
439 
           op_code <= op_code;
440 
    end case;
441 
  end if;
442 
end process;
443 
 
444 
----------------------------------
445 
--
446 
-- pre byte register
447 
--
448 
----------------------------------
449 
 
450 
pre_reg: process( clk, pre_ctrl, data_in, pre_byte )
451 
begin
452 
  if clk'event and clk = '0' then
453 
    case pre_ctrl is
454 
         when reset_pre =>
455 
           pre_byte <= "00000000";
456 
         when fetch_pre =>
457 
      pre_byte <= data_in;
458 
         when others =>
459 
--       when latch_op =>
460 
           pre_byte <= pre_byte;
461 
    end case;
462 
  end if;
463 
end process;
464 
 
465 
----------------------------------
466 
--
467 
-- counter
468 
--
469 
----------------------------------
470 
 
471 
count_reg: process( clk, count_ctrl, count )
472 
begin
473 
  if clk'event and clk = '0' then
474 
    case count_ctrl is
475 
         when reset_count =>
476 
           count <= "00000";
477 
         when inc_count =>
478 
      count <= count + "00001";
479 
         when others =>
480 
--       when latch_count =>
481 
           count <= count;
482 
    end case;
483 
  end if;
484 
end process;
485 
 
486 
----------------------------------
487 
--
488 
-- Address output multiplexer
489 
--
490 
----------------------------------
491 
 
492 
addr_mux: process( clk, addr_ctrl, pc, ea, sp, iv )
493 
begin
494 
  case addr_ctrl is
495 
    when idle_ad =>
496 
           address <= "1111111111111111";
497 
                vma     <= '0';
498 
                rw      <= '1';
499 
    when fetch_ad =>
500 
           address <= pc;
501 
                vma     <= '1';
502 
                rw      <= '1';
503 
         when read_ad =>
504 
           address <= ea;
505 
                vma     <= '1';
506 
                rw      <= '1';
507 
    when write_ad =>
508 
           address <= ea;
509 
                vma     <= '1';
510 
                rw      <= '0';
511 
         when push_ad =>
512 
           address <= sp;
513 
                vma     <= '1';
514 
                rw      <= '0';
515 
    when pull_ad =>
516 
           address <= sp;
517 
                vma     <= '1';
518 
                rw      <= '1';
519 
         when int_hi_ad =>
520 
           address <= "1111111111111" & iv & "0";
521 
                vma     <= '1';
522 
                rw      <= '1';
523 
    when int_lo_ad =>
524 
           address <= "1111111111111" & iv & "1";
525 
                vma     <= '1';
526 
                rw      <= '1';
527 
         when others =>
528 
           address <= "1111111111111111";
529 
                vma     <= '0';
530 
                rw      <= '1';
531 
  end case;
532 
end process;
533 
 
534 
--------------------------------
535 
--
536 
-- Data Bus output
537 
--
538 
--------------------------------
539 
dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, yreg, pc, cc )
540 
begin
541 
    case dout_ctrl is
542 
         when acca_dout => -- accumulator a
543 
           data_out <= acca;
544 
         when accb_dout => -- accumulator b
545 
           data_out <= accb;
546 
         when cc_dout => -- condition codes
547 
           data_out <= cc;
548 
         when ix_lo_dout => -- X index reg
549 
           data_out <= xreg(7 downto 0);
550 
         when ix_hi_dout => -- X index reg
551 
           data_out <= xreg(15 downto 8);
552 
         when iy_lo_dout => -- Y index reg
553 
           data_out <= yreg(7 downto 0);
554 
         when iy_hi_dout => -- Y index reg
555 
           data_out <= yreg(15 downto 8);
556 
         when md_lo_dout => -- memory data (ALU)
557 
           data_out <= md(7 downto 0);
558 
         when md_hi_dout => -- memory data (ALU)
559 
           data_out <= md(15 downto 8);
560 
         when pc_lo_dout => -- low order pc
561 
           data_out <= pc(7 downto 0);
562 
         when pc_hi_dout => -- high order pc
563 
           data_out <= pc(15 downto 8);
564 
         when others =>
565 
           data_out <= "00000000";
566 
    end case;
567 
end process;
568 
 
569 
----------------------------------
570 
--
571 
-- ea bit mutiplexer (used by multiply)
572 
--
573 
----------------------------------
574 
 
575 
ea_bit_mux: process( count, ea )
576 
begin
577 
  case count(3 downto 0) is
578 
         when "0000" =>
579 
           ea_bit <= ea(0);
580 
         when "0001" =>
581 
           ea_bit <= ea(1);
582 
         when "0010" =>
583 
           ea_bit <= ea(2);
584 
         when "0011" =>
585 
           ea_bit <= ea(3);
586 
         when "0100" =>
587 
           ea_bit <= ea(4);
588 
         when "0101" =>
589 
           ea_bit <= ea(5);
590 
         when "0110" =>
591 
           ea_bit <= ea(6);
592 
         when "0111" =>
593 
           ea_bit <= ea(7);
594 
         when "1000" =>
595 
           ea_bit <= ea(8);
596 
         when "1001" =>
597 
           ea_bit <= ea(9);
598 
         when "1010" =>
599 
           ea_bit <= ea(10);
600 
         when "1011" =>
601 
           ea_bit <= ea(11);
602 
         when "1100" =>
603 
           ea_bit <= ea(12);
604 
         when "1101" =>
605 
           ea_bit <= ea(13);
606 
         when "1110" =>
607 
           ea_bit <= ea(14);
608 
         when "1111" =>
609 
           ea_bit <= ea(15);
610 
         when others =>
611 
      null;
612 
  end case;
613 
end process;
614 
 
615 
----------------------------------
616 
--
617 
-- Left Mux
618 
--
619 
----------------------------------
620 
 
621 
left_mux: process( left_ctrl, acca, accb, xreg, yreg, sp, pc, ea, md )
622 
begin
623 
  case left_ctrl is
624 
         when acca_left =>
625 
           left(15 downto 8) <= "00000000";
626 
                left(7 downto 0)  <= acca;
627 
         when accb_left =>
628 
           left(15 downto 8) <= "00000000";
629 
                left(7 downto 0)  <= accb;
630 
         when accd_left =>
631 
           left(15 downto 8) <= acca;
632 
                left(7 downto 0)  <= accb;
633 
         when md_left =>
634 
           left <= md;
635 
         when ix_left =>
636 
           left <= xreg;
637 
         when iy_left =>
638 
           left <= yreg;
639 
         when sp_left =>
640 
           left <= sp;
641 
         when pc_left =>
642 
           left <= pc;
643 
         when others =>
644 
--       when ea_left =>
645 
           left <= ea;
646 
    end case;
647 
end process;
648 
 
649 
----------------------------------
650 
--
651 
-- Right Mux
652 
--
653 
----------------------------------
654 
 
655 
right_mux: process( right_ctrl, data_in, md, accb, pre_byte, ea )
656 
begin
657 
  case right_ctrl is
658 
         when zero_right =>
659 
           right <= "0000000000000000";
660 
         when one_right =>
661 
           right <= "0000000000000001";
662 
         when accb_right =>
663 
           right <= "00000000" & accb; -- for abx / aby instructions
664 
         when pre_right =>
665 
           right <= "00000000" & pre_byte; -- prebyte register doubles as bit mask
666 
         when ea_right =>
667 
           right <= ea;
668 
         when sexea_right =>
669 
           if ea(7) = '0' then
670 
             right <= "00000000" & ea(7 downto 0);
671 
                else
672 
                  right <= "11111111" & ea(7 downto 0);
673 
                end if;
674 
         when others =>
675 
--       when md_right =>
676 
           right <= md;
677 
    end case;
678 
end process;
679 
 
680 
----------------------------------
681 
--
682 
-- Arithmetic Logic Unit
683 
--
684 
----------------------------------
685 
 
686 
alu_logic: process( alu_ctrl, cc, left, right, out_alu, cc_out )
687 
variable valid_lo, valid_hi : boolean;
688 
variable carry_in : std_logic;
689 
variable daa_reg : std_logic_vector(7 downto 0);
690 
begin
691 
 
692 
  case alu_ctrl is
693 
         when alu_adc | alu_sbc |
694 
              alu_rol8 | alu_ror8 | alu_rol16 =>
695 
           carry_in := cc(CBIT);
696 
         when others =>
697 
           carry_in := '0';
698 
  end case;
699 
 
700 
  valid_lo := left(3 downto 0) <= 9;
701 
  valid_hi := left(7 downto 4) <= 9;
702 
 
703 
  if (cc(CBIT) = '0') then
704 
    if( cc(HBIT) = '1' ) then
705 
                if valid_hi then
706 
                  daa_reg := "00000110";
707 
                else
708 
                  daa_reg := "01100110";
709 
           end if;
710 
    else
711 
                if valid_lo then
712 
                  if valid_hi then
713 
                    daa_reg := "00000000";
714 
                  else
715 
                    daa_reg := "01100000";
716 
                  end if;
717 
                else
718 
             if( left(7 downto 4) <= 8 ) then
719 
                    daa_reg := "00000110";
720 
                  else
721 
                         daa_reg := "01100110";
722 
                  end if;
723 
                end if;
724 
         end if;
725 
  else
726 
    if ( cc(HBIT) = '1' )then
727 
                daa_reg := "01100110";
728 
         else
729 
                if valid_lo then
730 
                  daa_reg := "01100000";
731 
           else
732 
                  daa_reg := "01100110";
733 
                end if;
734 
         end if;
735 
  end if;
736 
 
737 
  case alu_ctrl is
738 
         when alu_add8  | alu_adc | alu_inc |
739 
              alu_add16 | alu_inc16 =>
740 
                out_alu <= left + right + ("000000000000000" & carry_in);
741 
         when alu_sub8  | alu_sbc | alu_dec |
742 
              alu_sub16 | alu_dec16 =>
743 
           out_alu <= left - right - ("000000000000000" & carry_in);
744 
         when alu_and =>
745 
           out_alu   <= left and right;         -- and/bit
746 
         when alu_bclr =>
747 
           out_alu   <= left and (not right);   -- bclr
748 
         when alu_ora | alu_bset =>
749 
           out_alu   <= left or right;  -- or
750 
         when alu_eor =>
751 
           out_alu   <= left xor right;         -- eor/xor
752 
         when alu_lsl16 | alu_asl8 | alu_rol8 | alu_rol16 =>
753 
           out_alu   <= left(14 downto 0) & carry_in;    -- rol8/rol16/asl8/lsl16
754 
         when alu_lsr16 | alu_lsr8 =>
755 
           out_alu   <= carry_in & left(15 downto 1);   -- lsr
756 
         when alu_ror8 =>
757 
           out_alu   <= "00000000" & carry_in & left(7 downto 1);       -- ror
758 
         when alu_asr8 =>
759 
           out_alu   <= "00000000" & left(7) & left(7 downto 1);        -- asr
760 
         when alu_neg =>
761 
           out_alu   <= right - left;   -- neg (right=0)
762 
         when alu_com =>
763 
           out_alu   <= not left;
764 
         when alu_clr | alu_ld8 | alu_ld16 =>
765 
           out_alu   <= right;           -- clr, ld
766 
         when alu_st8 | alu_st16 =>
767 
           out_alu   <= left;
768 
         when alu_daa =>
769 
           out_alu   <= left + ("00000000" & daa_reg);
770 
         when alu_tpa =>
771 
           out_alu <= "00000000" & cc;
772 
         when others =>
773 
           out_alu   <= left; -- nop
774 
    end case;
775 
 
776 
         --
777 
         -- carry bit
778 
         --
779 
    case alu_ctrl is
780 
         when alu_add8 | alu_adc  =>
781 
      cc_out(CBIT) <= (left(7) and right(7)) or
782 
                                (left(7) and not out_alu(7)) or
783 
                                                   (right(7) and not out_alu(7));
784 
         when alu_sub8 | alu_sbc =>
785 
      cc_out(CBIT) <= ((not left(7)) and right(7)) or
786 
                                ((not left(7)) and out_alu(7)) or
787 
                                                         (right(7) and out_alu(7));
788 
         when alu_add16  =>
789 
      cc_out(CBIT) <= (left(15) and right(15)) or
790 
                                (left(15) and not out_alu(15)) or
791 
                                                   (right(15) and not out_alu(15));
792 
         when alu_sub16 =>
793 
      cc_out(CBIT) <= ((not left(15)) and right(15)) or
794 
                                ((not left(15)) and out_alu(15)) or
795 
                                                         (right(15) and out_alu(15));
796 
         when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
797 
           cc_out(CBIT) <= left(0);
798 
         when alu_rol8 | alu_asl8 =>
799 
           cc_out(CBIT) <= left(7);
800 
         when alu_lsl16 | alu_rol16 =>
801 
           cc_out(CBIT) <= left(15);
802 
         when alu_com =>
803 
           cc_out(CBIT) <= '1';
804 
         when alu_neg | alu_clr =>
805 
           cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
806 
                                out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
807 
    when alu_daa =>
808 
           if ( daa_reg(7 downto 4) = "0110" ) then
809 
                  cc_out(CBIT) <= '1';
810 
                else
811 
                  cc_out(CBIT) <= '0';
812 
           end if;
813 
         when alu_sec =>
814 
      cc_out(CBIT) <= '1';
815 
         when alu_clc =>
816 
      cc_out(CBIT) <= '0';
817 
    when alu_tap =>
818 
      cc_out(CBIT) <= left(CBIT);
819 
         when others => -- carry is not affected by cpx
820 
      cc_out(CBIT) <= cc(CBIT);
821 
    end case;
822 
         --
823 
         -- Zero flag
824 
         --
825 
    case alu_ctrl is
826 
         when alu_add8 | alu_sub8 |
827 
              alu_adc | alu_sbc |
828 
              alu_and | alu_ora | alu_eor |
829 
              alu_inc | alu_dec |
830 
                        alu_neg | alu_com | alu_clr |
831 
                        alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
832 
                   alu_ld8  | alu_st8 |
833 
                        alu_bset | alu_bclr =>
834 
      cc_out(ZBIT) <= not( out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
835 
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
836 
         when alu_add16 | alu_sub16 |
837 
              alu_lsl16 | alu_lsr16 |
838 
              alu_inc16 | alu_dec16 |
839 
                   alu_ld16  | alu_st16  =>
840 
      cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
841 
                                out_alu(11) or out_alu(10) or out_alu(9)  or out_alu(8)  or
842 
                                out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
843 
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
844 
    when alu_tap =>
845 
      cc_out(ZBIT) <= left(ZBIT);
846 
         when others =>
847 
      cc_out(ZBIT) <= cc(ZBIT);
848 
    end case;
849 
 
850 
    --
851 
         -- negative flag
852 
         --
853 
    case alu_ctrl is
854 
         when alu_add8 | alu_sub8 |
855 
              alu_adc | alu_sbc |
856 
              alu_and | alu_ora | alu_eor |
857 
              alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
858 
              alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
859 
                        alu_ld8  | alu_st8 |
860 
                        alu_bset | alu_bclr =>
861 
      cc_out(NBIT) <= out_alu(7);
862 
         when alu_add16 | alu_sub16 |
863 
              alu_lsl16 | alu_lsr16 |
864 
                        alu_ld16 | alu_st16 =>
865 
                cc_out(NBIT) <= out_alu(15);
866 
    when alu_tap =>
867 
      cc_out(NBIT) <= left(NBIT);
868 
         when others =>
869 
      cc_out(NBIT) <= cc(NBIT);
870 
    end case;
871 
 
872 
    --
873 
         -- Interrupt mask flag
874 
    --
875 
    case alu_ctrl is
876 
         when alu_sei =>
877 
                cc_out(IBIT) <= '1';               -- set interrupt mask
878 
         when alu_cli =>
879 
                cc_out(IBIT) <= '0';               -- clear interrupt mask
880 
         when alu_tap =>
881 
      cc_out(IBIT) <= left(IBIT);
882 
         when others =>
883 
                cc_out(IBIT) <= cc(IBIT);             -- interrupt mask
884 
    end case;
885 
 
886 
    --
887 
    -- Half Carry flag
888 
         --
889 
    case alu_ctrl is
890 
         when alu_add8 | alu_adc =>
891 
      cc_out(HBIT) <= (left(3) and right(3)) or
892 
                     (right(3) and not out_alu(3)) or
893 
                      (left(3) and not out_alu(3));
894 
    when alu_tap =>
895 
      cc_out(HBIT) <= left(HBIT);
896 
         when others =>
897 
                cc_out(HBIT) <= cc(HBIT);
898 
    end case;
899 
 
900 
    --
901 
    -- Overflow flag
902 
         --
903 
    case alu_ctrl is
904 
         when alu_add8 | alu_adc =>
905 
      cc_out(VBIT) <= (left(7)  and      right(7)  and (not out_alu(7))) or
906 
                 ((not left(7)) and (not right(7)) and      out_alu(7));
907 
         when alu_sub8 | alu_sbc =>
908 
      cc_out(VBIT) <= (left(7)  and (not right(7)) and (not out_alu(7))) or
909 
                 ((not left(7)) and      right(7)  and      out_alu(7));
910 
         when alu_add16 =>
911 
      cc_out(VBIT) <= (left(15)  and      right(15)  and (not out_alu(15))) or
912 
                 ((not left(15)) and (not right(15)) and      out_alu(15));
913 
         when alu_sub16 =>
914 
      cc_out(VBIT) <= (left(15)  and (not right(15)) and (not out_alu(15))) or
915 
                 ((not left(15)) and      right(15) and       out_alu(15));
916 
         when alu_inc =>
917 
           cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
918 
                                      left(3)  and left(2) and left(1) and left(0));
919 
         when alu_dec | alu_neg =>
920 
           cc_out(VBIT) <= (left(7)  and (not left(6)) and (not left(5)) and (not left(4)) and
921 
                            (not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
922 
         when alu_asr8 =>
923 
           cc_out(VBIT) <= left(0) xor left(7);
924 
         when alu_lsr8 | alu_lsr16 =>
925 
           cc_out(VBIT) <= left(0);
926 
         when alu_ror8 =>
927 
      cc_out(VBIT) <= left(0) xor cc(CBIT);
928 
    when alu_lsl16 =>
929 
      cc_out(VBIT) <= left(15) xor left(14);
930 
         when alu_rol8 | alu_asl8  =>
931 
      cc_out(VBIT) <= left(7) xor left(6);
932 
    when alu_tap =>
933 
      cc_out(VBIT) <= left(VBIT);
934 
         when alu_and | alu_ora | alu_eor | alu_com |
935 
              alu_st8 | alu_st16 | alu_ld8 | alu_ld16 |
936 
                        alu_bset | alu_bclr |
937 
                   alu_clv =>
938 
      cc_out(VBIT) <= '0';
939 
    when alu_sev =>
940 
           cc_out(VBIT) <= '1';
941 
         when others =>
942 
                cc_out(VBIT) <= cc(VBIT);
943 
    end case;
944 
 
945 
         case alu_ctrl is
946 
         when alu_sex =>
947 
                cc_out(XBIT) <= '1';               -- set interrupt mask
948 
         when alu_clx =>
949 
                cc_out(XBIT) <= '0';               -- clear interrupt mask
950 
         when alu_tap =>
951 
      cc_out(XBIT) <= cc(XBIT) and left(XBIT);
952 
         when others =>
953 
      cc_out(XBIT) <= cc(XBIT) and left(XBIT);
954 
         end case;
955 
 
956 
         case alu_ctrl is
957 
         when alu_tap =>
958 
      cc_out(SBIT) <= left(SBIT);
959 
         when others =>
960 
           cc_out(SBIT) <= cc(SBIT);
961 
         end case;
962 
end process;
963 
 
964 
 
965 
------------------------------------
966 
--
967 
-- state sequencer
968 
--
969 
------------------------------------
970 
state_logic: process( state, op_code, pre_byte, cc, ea, md, irq, xirq, ea_bit, count )
971 
        begin
972 
                  case state is
973 
          when reset_state =>        --  released from reset
974 
                            -- reset the registers
975 
             op_ctrl    <= reset_op;
976 
             pre_ctrl   <= reset_pre;
977 
                                 acca_ctrl  <= reset_acca;
978 
                                 accb_ctrl  <= reset_accb;
979 
                                 ix_ctrl    <= reset_ix;
980 
                                 iy_ctrl    <= reset_iy;
981 
                       sp_ctrl    <= reset_sp;
982 
                       pc_ctrl    <= reset_pc;
983 
                            ea_ctrl    <= reset_ea;
984 
                                 md_ctrl    <= reset_md;
985 
                                 iv_ctrl    <= reset_iv;
986 
                                 sp_ctrl    <= reset_sp;
987 
                                 count_ctrl <= reset_count;
988 
                                 -- idle the ALU
989 
             left_ctrl  <= pc_left;
990 
                                 right_ctrl <= zero_right;
991 
                                 alu_ctrl   <= alu_nop;
992 
             cc_ctrl    <= reset_cc;
993 
                                 -- idle the bus
994 
                                 dout_ctrl  <= md_lo_dout;
995 
             addr_ctrl  <= idle_ad;
996 
                       next_state <= vect_hi_state;
997 
 
998 
                         --
999 
                         -- Jump via interrupt vector
1000 
                         -- iv holds interrupt type
1001 
                         -- fetch PC hi from vector location
1002 
                         --
1003 
          when vect_hi_state =>
1004 
                            -- default the registers
1005 
             op_ctrl    <= latch_op;
1006 
             pre_ctrl   <= latch_pre;
1007 
             acca_ctrl  <= latch_acca;
1008 
             accb_ctrl  <= latch_accb;
1009 
             ix_ctrl    <= latch_ix;
1010 
             iy_ctrl    <= latch_iy;
1011 
             sp_ctrl    <= latch_sp;
1012 
             md_ctrl    <= latch_md;
1013 
             ea_ctrl    <= latch_ea;
1014 
             iv_ctrl    <= latch_iv;
1015 
                                 count_ctrl <= reset_count;
1016 
                                 -- idle the ALU
1017 
             left_ctrl  <= pc_left;
1018 
             right_ctrl <= zero_right;
1019 
             alu_ctrl   <= alu_nop;
1020 
             cc_ctrl    <= latch_cc;
1021 
                                 -- fetch pc low interrupt vector
1022 
                       pc_ctrl    <= pull_hi_pc;
1023 
             addr_ctrl  <= int_hi_ad;
1024 
             dout_ctrl  <= pc_hi_dout;
1025 
                       next_state <= vect_lo_state;
1026 
                         --
1027 
                         -- jump via interrupt vector
1028 
                         -- iv holds vector type
1029 
                         -- fetch PC lo from vector location
1030 
                         --
1031 
          when vect_lo_state =>
1032 
                            -- default the registers
1033 
             op_ctrl    <= latch_op;
1034 
             pre_ctrl   <= latch_pre;
1035 
             acca_ctrl  <= latch_acca;
1036 
             accb_ctrl  <= latch_accb;
1037 
             ix_ctrl    <= latch_ix;
1038 
             iy_ctrl    <= latch_iy;
1039 
             sp_ctrl    <= latch_sp;
1040 
             md_ctrl    <= latch_md;
1041 
             ea_ctrl    <= latch_ea;
1042 
             iv_ctrl    <= latch_iv;
1043 
                                 count_ctrl <= reset_count;
1044 
                                 -- idle the ALU
1045 
             left_ctrl  <= pc_left;
1046 
             right_ctrl <= zero_right;
1047 
             alu_ctrl   <= alu_nop;
1048 
             cc_ctrl    <= latch_cc;
1049 
                                 -- fetch the vector low byte
1050 
                       pc_ctrl    <= pull_lo_pc;
1051 
             addr_ctrl  <= int_lo_ad;
1052 
             dout_ctrl  <= pc_lo_dout;
1053 
                       next_state <= fetch_state;
1054 
 
1055 
                         --
1056 
                         -- Here to fetch an instruction
1057 
                         -- PC points to opcode
1058 
                         -- Should service interrupt requests at this point
1059 
                         -- either from the timer
1060 
                         -- or from the external input.
1061 
                         --
1062 4 dilbert57 
           when fetch_state =>
1063 
                              case op_code(7 downto 4) is
1064 
                                        when "0000" | -- inherent operators
1065 
                                             "0001" | -- bit operators come here
1066 
                         "0010" | -- branch conditional
1067 
                         "0011" | -- stack operators
1068 
                         "0100" | -- acca single operand
1069 
                         "0101" | -- accb single operand
1070 
                         "0110" | -- indexed single op
1071 
                         "0111" => -- extended single op
1072 
                 acca_ctrl  <= latch_acca;
1073 
                 accb_ctrl  <= latch_accb;
1074 
                 ix_ctrl    <= latch_ix;
1075 
                 iy_ctrl    <= latch_iy;
1076 
                 sp_ctrl    <= latch_sp;
1077 
                                          -- idle ALU
1078 
                 left_ctrl  <= acca_left;
1079 
                                          right_ctrl <= zero_right;
1080 
                                          alu_ctrl   <= alu_nop;
1081 
                                          cc_ctrl    <= latch_cc;
1082 
                    when "1000" | -- acca immediate
1083 
                         "1001" | -- acca direct
1084 
                         "1010" | -- acca indexed
1085 
                    "1011" => -- acca extended
1086 
                                     case op_code(3 downto 0) is
1087 
                                          when "0000" => -- suba
1088 
                                            left_ctrl   <= acca_left;
1089 
                                            right_ctrl  <= md_right;
1090 
                                            alu_ctrl    <= alu_sub8;
1091 
                                                 cc_ctrl     <= load_cc;
1092 
                                            acca_ctrl   <= load_acca;
1093 
                   accb_ctrl   <= latch_accb;
1094 
                   ix_ctrl     <= latch_ix;
1095 
                   iy_ctrl     <= latch_iy;
1096 
                   sp_ctrl     <= latch_sp;
1097 
                                          when "0001" => -- cmpa
1098 
                                            left_ctrl   <= acca_left;
1099 
                                            right_ctrl  <= md_right;
1100 
                                            alu_ctrl    <= alu_sub8;
1101 
                                                 cc_ctrl     <= load_cc;
1102 
                                            acca_ctrl   <= latch_acca;
1103 
                   accb_ctrl   <= latch_accb;
1104 
                   ix_ctrl     <= latch_ix;
1105 
                   iy_ctrl     <= latch_iy;
1106 
                   sp_ctrl     <= latch_sp;
1107 
                                          when "0010" => -- sbca
1108 
                                            left_ctrl   <= acca_left;
1109 
                                            right_ctrl  <= md_right;
1110 
                                            alu_ctrl    <= alu_sbc;
1111 
                                                 cc_ctrl     <= load_cc;
1112 
                                            acca_ctrl   <= load_acca;
1113 
                   accb_ctrl   <= latch_accb;
1114 
                   ix_ctrl     <= latch_ix;
1115 
                   iy_ctrl     <= latch_iy;
1116 
                   sp_ctrl     <= latch_sp;
1117 
                                          when "0011" => -- subd / cmpd
1118 
                                            left_ctrl   <= accd_left;
1119 
                                            right_ctrl  <= md_right;
1120 
                                            alu_ctrl    <= alu_sub16;
1121 
                                                 cc_ctrl     <= load_cc;
1122 
                                                 if (pre_byte = "00011010") or (pre_byte = "11001101") then
1123 
                                                   -- CPD
1124 
                                              acca_ctrl   <= latch_acca;
1125 
                                                   accb_ctrl   <= latch_accb;
1126 
                                                 else
1127 
                                                   -- SUBD
1128 
                                              acca_ctrl   <= load_hi_acca;
1129 
                                                   accb_ctrl   <= load_accb;
1130 
                                                 end if;
1131 
                   ix_ctrl     <= latch_ix;
1132 
                   iy_ctrl     <= latch_iy;
1133 
                   sp_ctrl     <= latch_sp;
1134 
                                          when "0100" => -- anda
1135 
                                            left_ctrl   <= acca_left;
1136 
                                            right_ctrl  <= md_right;
1137 
                                            alu_ctrl    <= alu_and;
1138 
                                                 cc_ctrl     <= load_cc;
1139 
                                            acca_ctrl   <= load_acca;
1140 
                   accb_ctrl   <= latch_accb;
1141 
                   ix_ctrl     <= latch_ix;
1142 
                   iy_ctrl     <= latch_iy;
1143 
                   sp_ctrl     <= latch_sp;
1144 
                                          when "0101" => -- bita
1145 
                                            left_ctrl   <= acca_left;
1146 
                                            right_ctrl  <= md_right;
1147 
                                            alu_ctrl    <= alu_and;
1148 
                                                 cc_ctrl     <= load_cc;
1149 
                                            acca_ctrl   <= latch_acca;
1150 
                   accb_ctrl   <= latch_accb;
1151 
                   ix_ctrl     <= latch_ix;
1152 
                   iy_ctrl     <= latch_iy;
1153 
                   sp_ctrl     <= latch_sp;
1154 
                                          when "0110" => -- ldaa
1155 
                                            left_ctrl   <= acca_left;
1156 
                                            right_ctrl  <= md_right;
1157 
                                            alu_ctrl    <= alu_ld8;
1158 
                                                 cc_ctrl     <= load_cc;
1159 
                                            acca_ctrl   <= load_acca;
1160 
                   accb_ctrl   <= latch_accb;
1161 
                   ix_ctrl     <= latch_ix;
1162 
                   iy_ctrl     <= latch_iy;
1163 
                   sp_ctrl     <= latch_sp;
1164 
                                          when "0111" => -- staa
1165 
                                            left_ctrl   <= acca_left;
1166 
                                            right_ctrl  <= md_right;
1167 
                                            alu_ctrl    <= alu_st8;
1168 
                                                 cc_ctrl     <= load_cc;
1169 
                                            acca_ctrl   <= latch_acca;
1170 
                   accb_ctrl   <= latch_accb;
1171 
                   ix_ctrl     <= latch_ix;
1172 
                   iy_ctrl     <= latch_iy;
1173 
                   sp_ctrl     <= latch_sp;
1174 
                                          when "1000" => -- eora
1175 
                                            left_ctrl   <= acca_left;
1176 
                                            right_ctrl  <= md_right;
1177 
                                            alu_ctrl    <= alu_eor;
1178 
                                                 cc_ctrl     <= load_cc;
1179 
                                            acca_ctrl   <= load_acca;
1180 
                   accb_ctrl   <= latch_accb;
1181 
                   ix_ctrl     <= latch_ix;
1182 
                   iy_ctrl     <= latch_iy;
1183 
                   sp_ctrl     <= latch_sp;
1184 
                                          when "1001" => -- adca
1185 
                                            left_ctrl   <= acca_left;
1186 
                                            right_ctrl  <= md_right;
1187 
                                            alu_ctrl    <= alu_adc;
1188 
                                                 cc_ctrl     <= load_cc;
1189 
                                            acca_ctrl   <= load_acca;
1190 
                   accb_ctrl   <= latch_accb;
1191 
                   ix_ctrl     <= latch_ix;
1192 
                   iy_ctrl     <= latch_iy;
1193 
                   sp_ctrl     <= latch_sp;
1194 
                                          when "1010" => -- oraa
1195 
                                            left_ctrl   <= acca_left;
1196 
                                            right_ctrl  <= md_right;
1197 
                                            alu_ctrl    <= alu_ora;
1198 
                                                 cc_ctrl     <= load_cc;
1199 
                                            acca_ctrl   <= load_acca;
1200 
                   accb_ctrl   <= latch_accb;
1201 
                   ix_ctrl     <= latch_ix;
1202 
                   iy_ctrl     <= latch_iy;
1203 
                   sp_ctrl     <= latch_sp;
1204 
                                          when "1011" => -- adda
1205 
                                            left_ctrl   <= acca_left;
1206 
                                            right_ctrl  <= md_right;
1207 
                                            alu_ctrl    <= alu_add8;
1208 
                                                 cc_ctrl     <= load_cc;
1209 
                                            acca_ctrl   <= load_acca;
1210 
                   accb_ctrl   <= latch_accb;
1211 
                   ix_ctrl     <= latch_ix;
1212 
                   iy_ctrl     <= latch_iy;
1213 
                   sp_ctrl     <= latch_sp;
1214 
                                          when "1100" => -- cpx / cpy
1215 
                                            if (pre_byte = "00011000") or (pre_byte = "00011010") then
1216 
                                                        -- cpy
1217 
                                                   left_ctrl   <= iy_left;
1218 
                                                 else
1219 
                                                   -- cpx
1220 
                                              left_ctrl   <= ix_left;
1221 
                                                 end if;
1222 
                                            right_ctrl  <= md_right;
1223 
                                            alu_ctrl    <= alu_sub16;
1224 
                                                 cc_ctrl     <= load_cc;
1225 
                                            acca_ctrl   <= latch_acca;
1226 
                   accb_ctrl   <= latch_accb;
1227 
                   ix_ctrl     <= latch_ix;
1228 
                   iy_ctrl     <= latch_iy;
1229 
                   sp_ctrl     <= latch_sp;
1230 
                                          when "1101" => -- bsr / jsr
1231 
                                            left_ctrl   <= pc_left;
1232 
                                            right_ctrl  <= md_right;
1233 
                                            alu_ctrl    <= alu_nop;
1234 
                                                 cc_ctrl     <= latch_cc;
1235 
                                            acca_ctrl   <= latch_acca;
1236 
                   accb_ctrl   <= latch_accb;
1237 
                   ix_ctrl     <= latch_ix;
1238 
                   iy_ctrl     <= latch_iy;
1239 
                   sp_ctrl     <= latch_sp;
1240 
                                          when "1110" => -- lds
1241 
                                            left_ctrl   <= sp_left;
1242 
                                            right_ctrl  <= md_right;
1243 
                                            alu_ctrl    <= alu_ld16;
1244 
                                                 cc_ctrl     <= load_cc;
1245 
                                            acca_ctrl   <= latch_acca;
1246 
                   accb_ctrl   <= latch_accb;
1247 
                   ix_ctrl     <= latch_ix;
1248 
                   iy_ctrl     <= latch_iy;
1249 
                                                 sp_ctrl     <= load_sp;
1250 
                                          when "1111" => -- sts / xgdx / xgdy
1251 
                                                 if op_code(7 downto 4) = "1000" then
1252 
                                         --
1253 
                                         -- exchange registers
1254 
                                         -- at this point md holds accd
1255 
                                         -- accd holds either X or Y
1256 
                                         -- now transfer md to X or Y
1257 
                                         --
1258 
                                              left_ctrl  <= md_left;
1259 
                     right_ctrl <= zero_right;
1260 
                     alu_ctrl   <= alu_st16;
1261 
                     cc_ctrl    <= latch_cc;
1262 
                     acca_ctrl  <= latch_acca;
1263 
                     accb_ctrl  <= latch_accb;
1264 
                     sp_ctrl    <= latch_sp;
1265 
                                              if pre_byte = "00011000" then
1266 
                       ix_ctrl    <= latch_ix;
1267 
                       iy_ctrl    <= load_iy;
1268 
                                              else
1269 
                       ix_ctrl    <= load_ix;
1270 
                       iy_ctrl    <= latch_iy;
1271 
                                              end if;
1272 
                   else
1273 
                                                   -- sts
1274 
                                              left_ctrl   <= sp_left;
1275 
                                              right_ctrl  <= md_right;
1276 
                                              alu_ctrl    <= alu_st16;
1277 
                                                   cc_ctrl     <= load_cc;
1278 
                                              acca_ctrl   <= latch_acca;
1279 
                     accb_ctrl   <= latch_accb;
1280 
                     ix_ctrl     <= latch_ix;
1281 
                     iy_ctrl     <= latch_iy;
1282 
                     sp_ctrl     <= latch_sp;
1283 
                   end if;
1284 
                                          when others =>
1285 
                                            left_ctrl   <= acca_left;
1286 
                                            right_ctrl  <= md_right;
1287 
                                            alu_ctrl    <= alu_nop;
1288 
                                                 cc_ctrl     <= latch_cc;
1289 
                                            acca_ctrl   <= latch_acca;
1290 
                   accb_ctrl   <= latch_accb;
1291 
                   ix_ctrl     <= latch_ix;
1292 
                   iy_ctrl     <= latch_iy;
1293 
                   sp_ctrl     <= latch_sp;
1294 
                                          end case;
1295 
                    when "1100" | -- accb immediate
1296 
                         "1101" | -- accb direct
1297 
                         "1110" | -- accb indexed
1298 
                    "1111" => -- accb extended
1299 
                                     case op_code(3 downto 0) is
1300 
                                          when "0000" => -- subb
1301 
                                            left_ctrl   <= accb_left;
1302 
                                            right_ctrl  <= md_right;
1303 
                                            alu_ctrl    <= alu_sub8;
1304 
                                                 cc_ctrl     <= load_cc;
1305 
                                            acca_ctrl   <= latch_acca;
1306 
                   accb_ctrl   <= load_accb;
1307 
                   ix_ctrl     <= latch_ix;
1308 
                   iy_ctrl     <= latch_iy;
1309 
                   sp_ctrl     <= latch_sp;
1310 
                                          when "0001" => -- cmpb
1311 
                                            left_ctrl   <= accb_left;
1312 
                                            right_ctrl  <= md_right;
1313 
                                            alu_ctrl    <= alu_sub8;
1314 
                                                 cc_ctrl     <= load_cc;
1315 
                                            acca_ctrl   <= latch_acca;
1316 
                   accb_ctrl   <= latch_accb;
1317 
                   ix_ctrl     <= latch_ix;
1318 
                   iy_ctrl     <= latch_iy;
1319 
                   sp_ctrl     <= latch_sp;
1320 
                                          when "0010" => -- sbcb
1321 
                                            left_ctrl   <= accb_left;
1322 
                                            right_ctrl  <= md_right;
1323 
                                            alu_ctrl    <= alu_sbc;
1324 
                                                 cc_ctrl     <= load_cc;
1325 
                                            acca_ctrl   <= latch_acca;
1326 
                   accb_ctrl   <= load_accb;
1327 
                   ix_ctrl     <= latch_ix;
1328 
                   iy_ctrl     <= latch_iy;
1329 
                   sp_ctrl     <= latch_sp;
1330 
                                          when "0011" => -- addd
1331 
                                            left_ctrl   <= accd_left;
1332 
                                            right_ctrl  <= md_right;
1333 
                                            alu_ctrl    <= alu_add16;
1334 
                                                 cc_ctrl     <= load_cc;
1335 
                                            acca_ctrl   <= load_hi_acca;
1336 
                                                 accb_ctrl   <= load_accb;
1337 
                   ix_ctrl     <= latch_ix;
1338 
                   iy_ctrl     <= latch_iy;
1339 
                   sp_ctrl     <= latch_sp;
1340 
                                          when "0100" => -- andb
1341 
                                            left_ctrl   <= accb_left;
1342 
                                            right_ctrl  <= md_right;
1343 
                                            alu_ctrl    <= alu_and;
1344 
                                                 cc_ctrl     <= load_cc;
1345 
                                            acca_ctrl   <= latch_acca;
1346 
                   accb_ctrl   <= load_accb;
1347 
                   ix_ctrl     <= latch_ix;
1348 
                   iy_ctrl     <= latch_iy;
1349 
                   sp_ctrl     <= latch_sp;
1350 
                                          when "0101" => -- bitb
1351 
                                            left_ctrl   <= accb_left;
1352 
                                            right_ctrl  <= md_right;
1353 
                                            alu_ctrl    <= alu_and;
1354 
                                                 cc_ctrl     <= load_cc;
1355 
                                            acca_ctrl   <= latch_acca;
1356 
                   accb_ctrl   <= latch_accb;
1357 
                   ix_ctrl     <= latch_ix;
1358 
                   iy_ctrl     <= latch_iy;
1359 
                   sp_ctrl     <= latch_sp;
1360 
                                          when "0110" => -- ldab
1361 
                                            left_ctrl   <= accb_left;
1362 
                                            right_ctrl  <= md_right;
1363 
                                            alu_ctrl    <= alu_ld8;
1364 
                                                 cc_ctrl     <= load_cc;
1365 
                                            acca_ctrl   <= latch_acca;
1366 
                   accb_ctrl   <= load_accb;
1367 
                   ix_ctrl     <= latch_ix;
1368 
                   iy_ctrl     <= latch_iy;
1369 
                   sp_ctrl     <= latch_sp;
1370 
                                          when "0111" => -- stab
1371 
                                            left_ctrl   <= accb_left;
1372 
                                            right_ctrl  <= md_right;
1373 
                                            alu_ctrl    <= alu_st8;
1374 
                                                 cc_ctrl     <= load_cc;
1375 
                                            acca_ctrl   <= latch_acca;
1376 
                   accb_ctrl   <= latch_accb;
1377 
                   ix_ctrl     <= latch_ix;
1378 
                   iy_ctrl     <= latch_iy;
1379 
                   sp_ctrl     <= latch_sp;
1380 
                                          when "1000" => -- eorb
1381 
                                            left_ctrl   <= accb_left;
1382 
                                            right_ctrl  <= md_right;
1383 
                                            alu_ctrl    <= alu_eor;
1384 
                                                 cc_ctrl     <= load_cc;
1385 
                                            acca_ctrl   <= latch_acca;
1386 
                   accb_ctrl   <= load_accb;
1387 
                   ix_ctrl     <= latch_ix;
1388 
                   iy_ctrl     <= latch_iy;
1389 
                   sp_ctrl     <= latch_sp;
1390 
                                          when "1001" => -- adcb
1391 
                                            left_ctrl   <= accb_left;
1392 
                                            right_ctrl  <= md_right;
1393 
                                            alu_ctrl    <= alu_adc;
1394 
                                                 cc_ctrl     <= load_cc;
1395 
                                            acca_ctrl   <= latch_acca;
1396 
                   accb_ctrl   <= load_accb;
1397 
                   ix_ctrl     <= latch_ix;
1398 
                   iy_ctrl     <= latch_iy;
1399 
                   sp_ctrl     <= latch_sp;
1400 
                                          when "1010" => -- orab
1401 
                                            left_ctrl   <= accb_left;
1402 
                                            right_ctrl  <= md_right;
1403 
                                            alu_ctrl    <= alu_ora;
1404 
                                                 cc_ctrl     <= load_cc;
1405 
                                            acca_ctrl   <= latch_acca;
1406 
                   accb_ctrl   <= load_accb;
1407 
                   ix_ctrl     <= latch_ix;
1408 
                   iy_ctrl     <= latch_iy;
1409 
                   sp_ctrl     <= latch_sp;
1410 
                                          when "1011" => -- addb
1411 
                                            left_ctrl   <= accb_left;
1412 
                                            right_ctrl  <= md_right;
1413 
                                            alu_ctrl    <= alu_add8;
1414 
                                                 cc_ctrl     <= load_cc;
1415 
                                            acca_ctrl   <= latch_acca;
1416 
                   accb_ctrl   <= load_accb;
1417 
                   ix_ctrl     <= latch_ix;
1418 
                   iy_ctrl     <= latch_iy;
1419 
                   sp_ctrl     <= latch_sp;
1420 
                                          when "1100" => -- ldd
1421 
                                            left_ctrl   <= accd_left;
1422 
                                            right_ctrl  <= md_right;
1423 
                                            alu_ctrl    <= alu_ld16;
1424 
                                                 cc_ctrl     <= load_cc;
1425 
                                            acca_ctrl   <= load_hi_acca;
1426 
                   accb_ctrl   <= load_accb;
1427 
                   ix_ctrl     <= latch_ix;
1428 
                   iy_ctrl     <= latch_iy;
1429 
                   sp_ctrl     <= latch_sp;
1430 
                                          when "1101" => -- std
1431 
                                            left_ctrl   <= accd_left;
1432 
                                            right_ctrl  <= md_right;
1433 
                                            alu_ctrl    <= alu_st16;
1434 
                                                 cc_ctrl     <= load_cc;
1435 
                                            acca_ctrl   <= latch_acca;
1436 
                   accb_ctrl   <= latch_accb;
1437 
                   ix_ctrl     <= latch_ix;
1438 
                   iy_ctrl     <= latch_iy;
1439 
                   sp_ctrl     <= latch_sp;
1440 
                                          when "1110" => -- ldx / ldy
1441 
                                            if ((pre_byte = "00011000") or (pre_byte = "00011010"))  then
1442 
                                                   -- LDY
1443 
                                              left_ctrl   <= iy_left;
1444 
                     ix_ctrl     <= latch_ix;
1445 
                     iy_ctrl     <= load_iy;
1446 
                   else
1447 
                                                   -- LDX
1448 
                                              left_ctrl   <= ix_left;
1449 
                     ix_ctrl     <= load_ix;
1450 
                     iy_ctrl     <= latch_iy;
1451 
                                                 end if;
1452 
                                            right_ctrl  <= md_right;
1453 
                                            alu_ctrl    <= alu_ld16;
1454 
                                                 cc_ctrl     <= load_cc;
1455 
                                            acca_ctrl   <= latch_acca;
1456 
                   accb_ctrl   <= latch_accb;
1457 
                                                 sp_ctrl     <= latch_sp;
1458 
                                          when "1111" => -- stx / sty
1459 
                                            if ((pre_byte = "00011000") or (pre_byte = "00011010"))  then
1460 
                     -- STY
1461 
                                              left_ctrl   <= iy_left;
1462 
                   else
1463 
                                                   -- STX
1464 
                                              left_ctrl   <= ix_left;
1465 
                                                 end if;
1466 
                                            right_ctrl  <= md_right;
1467 
                                            alu_ctrl    <= alu_st16;
1468 
                                                 cc_ctrl     <= load_cc;
1469 
                                            acca_ctrl   <= latch_acca;
1470 
                   accb_ctrl   <= latch_accb;
1471 
                   ix_ctrl     <= latch_ix;
1472 
                   iy_ctrl     <= latch_iy;
1473 
                   sp_ctrl     <= latch_sp;
1474 
                                          when others =>
1475 
                                            left_ctrl   <= accb_left;
1476 
                                            right_ctrl  <= md_right;
1477 
                                            alu_ctrl    <= alu_nop;
1478 
                                                 cc_ctrl     <= latch_cc;
1479 
                                            acca_ctrl   <= latch_acca;
1480 
                   accb_ctrl   <= latch_accb;
1481 
                   ix_ctrl     <= latch_ix;
1482 
                   iy_ctrl     <= latch_iy;
1483 
                   sp_ctrl     <= latch_sp;
1484 
                                          end case;
1485 
                    when others =>
1486 
                                          left_ctrl   <= accd_left;
1487 
                                          right_ctrl  <= md_right;
1488 
                                          alu_ctrl    <= alu_nop;
1489 
                                          cc_ctrl     <= latch_cc;
1490 
                                          acca_ctrl   <= latch_acca;
1491 
                 accb_ctrl   <= latch_accb;
1492 
                 ix_ctrl     <= latch_ix;
1493 
                 iy_ctrl     <= latch_iy;
1494 
                 sp_ctrl     <= latch_sp;
1495 
               end case;
1496 
               ea_ctrl    <= reset_ea;
1497 
               md_ctrl    <= latch_md;
1498 
                                   count_ctrl <= reset_count;
1499 
                                   -- fetch the op code
1500 
                              op_ctrl    <= fetch_op;
1501 
               pre_ctrl   <= fetch_pre;
1502 
               addr_ctrl  <= fetch_ad;
1503 
               dout_ctrl  <= md_lo_dout;
1504 
                              iv_ctrl    <= latch_iv;
1505 
                                   -- service non maskable interrupts
1506 
                              if (xirq = '1') and (cc(XBIT) = '0') then
1507 
                 pc_ctrl    <= latch_pc;
1508 
                                next_state <= int_pcl_state;
1509 
                                   -- service maskable interrupts
1510 
                              else
1511 2 dilbert57 
                                        --
1512 
                                        -- IRQ is level sensitive
1513 
                                        --
1514 4 dilbert57 
                                     if (irq = '1') and (cc(IBIT) = '0') then
1515 
                   pc_ctrl    <= latch_pc;
1516 
                                  next_state <= int_pcl_state;
1517 
                 else
1518 
                                     -- Advance the PC to fetch next instruction byte
1519 
                   pc_ctrl    <= incr_pc;
1520 
                                  next_state <= decode_state;
1521 
                 end if;
1522 
                                   end if;
1523 2 dilbert57 
                         --
1524 
                         -- Here to decode instruction
1525 
                         -- and fetch next byte of intruction
1526 
                         -- whether it be necessary or not
1527 
                         --
1528 
          when decode_state =>
1529 
                                 -- fetch first byte of address or immediate data
1530 
             addr_ctrl  <= fetch_ad;
1531 
             dout_ctrl  <= md_lo_dout;
1532 
             iv_ctrl    <= latch_iv;
1533 
                                 count_ctrl <= reset_count;
1534 4 dilbert57 
             pre_ctrl   <= latch_pre;
1535 2 dilbert57 
                            case op_code(7 downto 4) is
1536 
                                 when "0000" =>
1537 
                                   md_ctrl    <= reset_md;
1538 
               sp_ctrl    <= latch_sp;
1539 
               pc_ctrl    <= latch_pc;
1540 
                              op_ctrl    <= latch_op;
1541 
                    case op_code(3 downto 0) is
1542 
                         when "0000" => -- test -- spin PC
1543 
                                          left_ctrl  <= accd_left;
1544 
                 right_ctrl <= zero_right;
1545 
                                          alu_ctrl   <= alu_nop;
1546 
                 cc_ctrl    <= latch_cc;
1547 
                 ea_ctrl    <= reset_ea;
1548 
                                          acca_ctrl  <= latch_acca;
1549 
                                          accb_ctrl  <= latch_accb;
1550 
                                          ix_ctrl    <= latch_ix;
1551 
                                          iy_ctrl    <= latch_iy;
1552 
                                          next_state <= spin_state;
1553 
                         when "0001" => -- nop
1554 
                                          left_ctrl  <= accd_left;
1555 
                 right_ctrl <= zero_right;
1556 
                                          alu_ctrl   <= alu_nop;
1557 
                 cc_ctrl    <= latch_cc;
1558 
                 ea_ctrl    <= reset_ea;
1559 
                                          acca_ctrl  <= latch_acca;
1560 
                                          accb_ctrl  <= latch_accb;
1561 
                                          ix_ctrl    <= latch_ix;
1562 
                                          iy_ctrl    <= latch_iy;
1563 
                                          next_state <= fetch_state;
1564 
                         when "0010" => -- idiv
1565 
                                          -- transfer IX to ea
1566 
                 left_ctrl  <= ix_left;
1567 
                 right_ctrl <= zero_right;
1568 
                 alu_ctrl   <= alu_st16;
1569 
                 cc_ctrl    <= latch_cc;
1570 
                 ea_ctrl    <= load_ea;
1571 
                                          acca_ctrl  <= latch_acca;
1572 
                                          accb_ctrl  <= latch_accb;
1573 
                                          ix_ctrl    <= latch_ix;
1574 
                                          iy_ctrl    <= latch_iy;
1575 
                                          next_state <= idiv_state;
1576 
                         when "0011" => -- fdiv
1577 
                 left_ctrl  <= ix_left;
1578 
                 right_ctrl <= zero_right;
1579 
                 alu_ctrl   <= alu_st16;
1580 
                 cc_ctrl    <= latch_cc;
1581 
                 ea_ctrl    <= load_ea;
1582 
                                          acca_ctrl  <= latch_acca;
1583 
                                          accb_ctrl  <= latch_accb;
1584 
                                          ix_ctrl    <= reset_ix;
1585 
                                          iy_ctrl    <= latch_iy;
1586 
                                          next_state <= div1_state;
1587 
                         when "0100" => -- lsrd
1588 
                                          left_ctrl  <= accd_left;
1589 
                 right_ctrl <= zero_right;
1590 
                                          alu_ctrl   <= alu_lsr16;
1591 
                 cc_ctrl    <= load_cc;
1592 
                                          acca_ctrl  <= load_hi_acca;
1593 
                                          accb_ctrl  <= load_accb;
1594 
                                          ix_ctrl    <= latch_ix;
1595 
                                          iy_ctrl    <= latch_iy;
1596 
                 ea_ctrl    <= reset_ea;
1597 
                                          next_state <= fetch_state;
1598 
                         when "0101" => -- lsld
1599 
                                          left_ctrl  <= accd_left;
1600 
                 right_ctrl <= zero_right;
1601 
                                          alu_ctrl   <= alu_lsl16;
1602 
                 cc_ctrl    <= load_cc;
1603 
                                          acca_ctrl  <= load_hi_acca;
1604 
                                          accb_ctrl  <= load_accb;
1605 
                                          ix_ctrl    <= latch_ix;
1606 
                                          iy_ctrl    <= latch_iy;
1607 
                 ea_ctrl    <= reset_ea;
1608 
                                          next_state <= fetch_state;
1609 
                         when "0110" => -- tap
1610 
                                          left_ctrl  <= acca_left;
1611 
                 right_ctrl <= zero_right;
1612 
                                          alu_ctrl   <= alu_tap;
1613 
                 cc_ctrl    <= load_cc;
1614 
                                          acca_ctrl  <= latch_acca;
1615 
                                          accb_ctrl  <= latch_accb;
1616 
                                          ix_ctrl    <= latch_ix;
1617 
                                          iy_ctrl    <= latch_iy;
1618 
                 ea_ctrl    <= reset_ea;
1619 
                                          next_state <= fetch_state;
1620 
                         when "0111" => -- tpa
1621 
                                          left_ctrl  <= acca_left;
1622 
                 right_ctrl <= zero_right;
1623 
                                          alu_ctrl   <= alu_tpa;
1624 
                 cc_ctrl    <= latch_cc;
1625 
                                          acca_ctrl  <= load_acca;
1626 
                                          accb_ctrl  <= latch_accb;
1627 
                                          ix_ctrl    <= latch_ix;
1628 
                                          iy_ctrl    <= latch_iy;
1629 
                 ea_ctrl    <= reset_ea;
1630 
                                          next_state <= fetch_state;
1631 4 dilbert57 
                         when "1000" => -- inx / iny
1632 2 dilbert57 
                                          if pre_byte = "00011000" then
1633 4 dilbert57 
                                            -- iny
1634 2 dilbert57 
                                            left_ctrl  <= iy_left;
1635 
                                            ix_ctrl    <= latch_ix;
1636 
                                            iy_ctrl    <= load_iy;
1637 
                                          else
1638 4 dilbert57 
                                            -- inx
1639 2 dilbert57 
                                            left_ctrl  <= ix_left;
1640 
                                            ix_ctrl    <= load_ix;
1641 
                                            iy_ctrl    <= latch_iy;
1642 
                                          end if;
1643 
                 ea_ctrl    <= reset_ea;
1644 
                      right_ctrl <= one_right;
1645 
                                          alu_ctrl   <= alu_inc16;
1646 
                 cc_ctrl    <= load_cc;
1647 
                                          acca_ctrl  <= latch_acca;
1648 
                                          accb_ctrl  <= latch_accb;
1649 
                                          next_state <= fetch_state;
1650 4 dilbert57 
                         when "1001" => -- dex / dey
1651 2 dilbert57 
                                          if pre_byte = "00011000" then
1652 4 dilbert57 
                                            -- dey
1653 2 dilbert57 
                                            left_ctrl  <= iy_left;
1654 
                                            ix_ctrl    <= latch_ix;
1655 
                                            iy_ctrl    <= load_iy;
1656 
                                          else
1657 4 dilbert57 
                                            -- dex
1658 2 dilbert57 
                                            left_ctrl  <= ix_left;
1659 
                                            ix_ctrl    <= load_ix;
1660 
                                            iy_ctrl    <= latch_iy;
1661 
                                          end if;
1662 
                 ea_ctrl    <= reset_ea;
1663 
                      right_ctrl <= one_right;
1664 
                                          alu_ctrl   <= alu_dec16;
1665 
                 cc_ctrl    <= load_cc;
1666 
                                          acca_ctrl  <= latch_acca;
1667 
                                          accb_ctrl  <= latch_accb;
1668 
                                          next_state <= fetch_state;
1669 
                         when "1010" => -- clv
1670 
                                          left_ctrl  <= acca_left;
1671 
                 right_ctrl <= zero_right;
1672 
                                          alu_ctrl   <= alu_clv;
1673 
                 cc_ctrl    <= load_cc;
1674 
                                          acca_ctrl  <= latch_acca;
1675 
                                          accb_ctrl  <= latch_accb;
1676 
                                          ix_ctrl    <= latch_ix;
1677 
                                          iy_ctrl    <= latch_iy;
1678 
                 ea_ctrl    <= reset_ea;
1679 
                                          next_state <= fetch_state;
1680 
                         when "1011" => -- sev
1681 
                                          left_ctrl  <= acca_left;
1682 
                 right_ctrl <= zero_right;
1683 
                                          alu_ctrl   <= alu_sev;
1684 
                 cc_ctrl    <= load_cc;
1685 
                                          acca_ctrl  <= latch_acca;
1686 
                                          accb_ctrl  <= latch_accb;
1687 
                                          ix_ctrl    <= latch_ix;
1688 
                                          iy_ctrl    <= latch_iy;
1689 
                 ea_ctrl    <= reset_ea;
1690 
                                          next_state <= fetch_state;
1691 
                         when "1100" => -- clc
1692 
                                          left_ctrl  <= acca_left;
1693 
                 right_ctrl <= zero_right;
1694 
                                          alu_ctrl   <= alu_clc;
1695 
                 cc_ctrl    <= load_cc;
1696 
                                          acca_ctrl  <= latch_acca;
1697 
                                          accb_ctrl  <= latch_accb;
1698 
                                          ix_ctrl    <= latch_ix;
1699 
                                          iy_ctrl    <= latch_iy;
1700 
                 ea_ctrl    <= reset_ea;
1701 
                                          next_state <= fetch_state;
1702 
                         when "1101" => -- sec
1703 
                                          left_ctrl  <= acca_left;
1704 
                 right_ctrl <= zero_right;
1705 
                                          alu_ctrl   <= alu_sec;
1706 
                 cc_ctrl    <= load_cc;
1707 
                                          acca_ctrl  <= latch_acca;
1708 
                                          accb_ctrl  <= latch_accb;
1709 
                                          ix_ctrl    <= latch_ix;
1710 
                                          iy_ctrl    <= latch_iy;
1711 
                 ea_ctrl    <= reset_ea;
1712 
                                          next_state <= fetch_state;
1713 
                         when "1110" => -- cli
1714 
                                          left_ctrl  <= acca_left;
1715 
                 right_ctrl <= zero_right;
1716 
                                          alu_ctrl   <= alu_cli;
1717 
                 cc_ctrl    <= load_cc;
1718 
                                          acca_ctrl  <= latch_acca;
1719 
                                          accb_ctrl  <= latch_accb;
1720 
                                          ix_ctrl    <= latch_ix;
1721 
                                          iy_ctrl    <= latch_iy;
1722 
                 ea_ctrl    <= reset_ea;
1723 
                                          next_state <= fetch_state;
1724 
                         when "1111" => -- sei
1725 
                                          left_ctrl  <= acca_left;
1726 
                 right_ctrl <= zero_right;
1727 
                                          alu_ctrl   <= alu_sei;
1728 
                 cc_ctrl    <= load_cc;
1729 
                                          acca_ctrl  <= latch_acca;
1730 
                                          accb_ctrl  <= latch_accb;
1731 
                                          ix_ctrl    <= latch_ix;
1732 
                                          iy_ctrl    <= latch_iy;
1733 
                 ea_ctrl    <= reset_ea;
1734 
                                          next_state <= fetch_state;
1735 
               when others =>
1736 
                                          left_ctrl  <= acca_left;
1737 
                 right_ctrl <= zero_right;
1738 
                                          alu_ctrl   <= alu_nop;
1739 
                 cc_ctrl    <= latch_cc;
1740 
                                          acca_ctrl  <= latch_acca;
1741 
                                          accb_ctrl  <= latch_accb;
1742 
                                          ix_ctrl    <= latch_ix;
1743 
                                          iy_ctrl    <= latch_iy;
1744 
                 ea_ctrl    <= reset_ea;
1745 
                                          next_state <= fetch_state;
1746 
                         end case;
1747 
                                 -- acca / accb inherent instructions
1748 
                  when "0001" =>
1749 
               ea_ctrl    <= fetch_first_ea;
1750 
                                   md_ctrl    <= fetch_first_md;
1751 
               ix_ctrl    <= latch_ix;
1752 
               iy_ctrl    <= latch_iy;
1753 
               sp_ctrl    <= latch_sp;
1754 
                    case op_code(3 downto 0) is
1755 
                         when "0000" => -- sba
1756 
                                op_ctrl    <= latch_op;
1757 
                                          left_ctrl  <= acca_left;
1758 
                      right_ctrl <= accb_right;
1759 
                                          alu_ctrl   <= alu_sub8;
1760 
                                          cc_ctrl    <= load_cc;
1761 
                                          acca_ctrl  <= load_acca;
1762 
                 accb_ctrl  <= latch_accb;
1763 
                 pc_ctrl    <= latch_pc;
1764 
                                          next_state <= fetch_state;
1765 
                         when "0001" => -- cba
1766 
                                op_ctrl    <= latch_op;
1767 
                                          left_ctrl  <= acca_left;
1768 
                      right_ctrl <= accb_right;
1769 
                                          alu_ctrl   <= alu_sub8;
1770 
                                          cc_ctrl    <= load_cc;
1771 
                                          acca_ctrl  <= latch_acca;
1772 
                 accb_ctrl  <= latch_accb;
1773 
                 pc_ctrl    <= latch_pc;
1774 
                                          next_state <= fetch_state;
1775 
                         when "0010" => -- brset direct
1776 
                                op_ctrl    <= latch_op;
1777 
                                          left_ctrl  <= pc_left;
1778 
                      right_ctrl <= one_right;
1779 
                                          alu_ctrl   <= alu_add16;
1780 
                                          cc_ctrl    <= latch_cc;
1781 
                                          acca_ctrl  <= latch_acca;
1782 
                 accb_ctrl  <= latch_accb;
1783 
                 pc_ctrl    <= load_pc;
1784 4 dilbert57 
                                          next_state <= read8_state;
1785 2 dilbert57 
                         when "0011" => -- brclr direct
1786 
                                op_ctrl    <= latch_op;
1787 
                                          left_ctrl  <= pc_left;
1788 
                      right_ctrl <= one_right;
1789 
                                          alu_ctrl   <= alu_add16;
1790 
                                          cc_ctrl    <= latch_cc;
1791 
                                          acca_ctrl  <= latch_acca;
1792 
                 accb_ctrl  <= latch_accb;
1793 
                 pc_ctrl    <= load_pc;
1794 4 dilbert57 
                                          next_state <= read8_state;
1795 2 dilbert57 
                         when "0100" => -- bset direct
1796 
                                op_ctrl    <= latch_op;
1797 
                                          left_ctrl  <= pc_left;
1798 
                      right_ctrl <= one_right;
1799 
                                          alu_ctrl   <= alu_add16;
1800 
                                          cc_ctrl    <= latch_cc;
1801 
                                          acca_ctrl  <= latch_acca;
1802 
                 accb_ctrl  <= latch_accb;
1803 
                 pc_ctrl    <= load_pc;
1804 4 dilbert57 
                                          next_state <= read8_state;
1805 2 dilbert57 
                         when "0101" => -- bclr direct
1806 
                                op_ctrl    <= latch_op;
1807 
                                          left_ctrl  <= pc_left;
1808 
                      right_ctrl <= one_right;
1809 
                                          alu_ctrl   <= alu_add16;
1810 
                                          cc_ctrl    <= latch_cc;
1811 
                                          acca_ctrl  <= latch_acca;
1812 
                 accb_ctrl  <= latch_accb;
1813 
                 pc_ctrl    <= load_pc;
1814 4 dilbert57 
                                          next_state <= read8_state;
1815 2 dilbert57 
                         when "0110" => -- tab
1816 
                                op_ctrl    <= latch_op;
1817 
                                          left_ctrl  <= acca_left;
1818 
                      right_ctrl <= accb_right;
1819 
                                          alu_ctrl   <= alu_st8;
1820 
                                          cc_ctrl    <= load_cc;
1821 
                                          acca_ctrl  <= latch_acca;
1822 
                                          accb_ctrl  <= load_accb;
1823 
                 pc_ctrl    <= latch_pc;
1824 
                                          next_state <= fetch_state;
1825 
                         when "0111" => -- tba
1826 
                                op_ctrl    <= latch_op;
1827 
                                          left_ctrl  <= acca_left;
1828 
                      right_ctrl <= accb_right;
1829 
                                          alu_ctrl   <= alu_ld8;
1830 
                                          cc_ctrl    <= load_cc;
1831 
                                          acca_ctrl  <= load_acca;
1832 
                 accb_ctrl  <= latch_accb;
1833 
                 pc_ctrl    <= latch_pc;
1834 
                                          next_state <= fetch_state;
1835 
                         when "1000" => -- indexed y prebyte
1836 
                                op_ctrl    <= fetch_op;
1837 
                                          left_ctrl  <= pc_left;
1838 
                      right_ctrl <= one_right;
1839 
                                          alu_ctrl   <= alu_add16;
1840 
                                          cc_ctrl    <= latch_cc;
1841 
                                          acca_ctrl  <= latch_acca;
1842 
                 accb_ctrl  <= latch_accb;
1843 
                 pc_ctrl    <= load_pc;
1844 
                                          next_state <= decode_state;
1845 
                         when "1001" => -- daa
1846 
                                op_ctrl    <= latch_op;
1847 
                                          left_ctrl  <= acca_left;
1848 
                      right_ctrl <= accb_right;
1849 
                                          alu_ctrl   <= alu_daa;
1850 
                                          cc_ctrl    <= load_cc;
1851 
                                          acca_ctrl  <= load_acca;
1852 
                 accb_ctrl  <= latch_accb;
1853 
                 pc_ctrl    <= latch_pc;
1854 
                                          next_state <= fetch_state;
1855 4 dilbert57 
                         when "1010" => -- prebyte - CPD / CPY / LDY / STY ff,X
1856 2 dilbert57 
                                op_ctrl    <= fetch_op;
1857 
                                          left_ctrl  <= pc_left;
1858 
                      right_ctrl <= one_right;
1859 
                                          alu_ctrl   <= alu_add16;
1860 
                                          cc_ctrl    <= latch_cc;
1861 
                                          acca_ctrl  <= latch_acca;
1862 
                 accb_ctrl  <= latch_accb;
1863 
                 pc_ctrl    <= load_pc;
1864 
                                          next_state <= decode_state;
1865 
                         when "1011" => -- aba
1866 
                                op_ctrl    <= latch_op;
1867 
                                          left_ctrl  <= acca_left;
1868 
                      right_ctrl <= accb_right;
1869 
                                          alu_ctrl   <= alu_add8;
1870 
                                          cc_ctrl    <= load_cc;
1871 
                                          acca_ctrl  <= load_acca;
1872 
                 accb_ctrl  <= latch_accb;
1873 
                 pc_ctrl    <= latch_pc;
1874 
                                          next_state <= fetch_state;
1875 
                         when "1100" => -- bset indexed
1876 
                                op_ctrl    <= latch_op;
1877 
                                          left_ctrl  <= pc_left;
1878 
                      right_ctrl <= one_right;
1879 
                                          alu_ctrl   <= alu_add16;
1880 
                                          cc_ctrl    <= latch_cc;
1881 
                                          acca_ctrl  <= latch_acca;
1882 
                 accb_ctrl  <= latch_accb;
1883 
                 pc_ctrl    <= load_pc;
1884 
                                          next_state <= indexed_state;
1885 
                         when "1101" => -- bclr indexed
1886 
                                op_ctrl    <= latch_op;
1887 
                                          left_ctrl  <= pc_left;
1888 
                      right_ctrl <= one_right;
1889 
                                          alu_ctrl   <= alu_add16;
1890 
                                          cc_ctrl    <= latch_cc;
1891 
                                          acca_ctrl  <= latch_acca;
1892 
                 accb_ctrl  <= latch_accb;
1893 
                 pc_ctrl    <= load_pc;
1894 
                                          next_state <= indexed_state;
1895 
                         when "1110" => -- brset indexed
1896 
                                op_ctrl    <= latch_op;
1897 
                                          left_ctrl  <= pc_left;
1898 
                      right_ctrl <= one_right;
1899 
                                          alu_ctrl   <= alu_add16;
1900 
                                          cc_ctrl    <= latch_cc;
1901 
                                          acca_ctrl  <= latch_acca;
1902 
                 accb_ctrl  <= latch_accb;
1903 
                 pc_ctrl    <= load_pc;
1904 
                                          next_state <= indexed_state;
1905 
                         when "1111" => -- brclr indexed
1906 
                                op_ctrl    <= latch_op;
1907 
                                          left_ctrl  <= pc_left;
1908 
                      right_ctrl <= one_right;
1909 
                                          alu_ctrl   <= alu_add16;
1910 
                                          cc_ctrl    <= latch_cc;
1911 
                                          acca_ctrl  <= latch_acca;
1912 
                 accb_ctrl  <= latch_accb;
1913 
                 pc_ctrl    <= load_pc;
1914 
                                          next_state <= indexed_state;
1915 
                         when others =>
1916 
                                op_ctrl    <= latch_op;
1917 
                                          left_ctrl  <= acca_left;
1918 
                      right_ctrl <= accb_right;
1919 
                                          alu_ctrl   <= alu_nop;
1920 
                                          cc_ctrl    <= latch_cc;
1921 
                                          acca_ctrl  <= latch_acca;
1922 
                 accb_ctrl  <= latch_accb;
1923 
                 pc_ctrl    <= latch_pc;
1924 
                                          next_state <= fetch_state;
1925 
                         end case;
1926 
                  when "0010" => -- branch conditional
1927 
               ea_ctrl    <= fetch_first_ea;
1928 
                                   md_ctrl    <= fetch_first_md;
1929 
                                   op_ctrl    <= latch_op;
1930 
                                        acca_ctrl  <= latch_acca;
1931 
               accb_ctrl  <= latch_accb;
1932 
               ix_ctrl    <= latch_ix;
1933 
               iy_ctrl    <= latch_iy;
1934 
               sp_ctrl    <= latch_sp;
1935 
                                        -- increment the pc
1936 
               left_ctrl  <= pc_left;
1937 
               right_ctrl <= one_right;
1938 
               alu_ctrl   <= alu_add16;
1939 
                                        cc_ctrl    <= latch_cc;
1940 
               pc_ctrl    <= load_pc;
1941 
               case op_code(3 downto 0) is
1942 
                         when "0000" => -- bra
1943 
                 next_state <= branch_state;
1944 
                         when "0001" => -- brn
1945 
                                          next_state <= fetch_state;
1946 
                         when "0010" => -- bhi
1947 
                                          if (cc(CBIT) or cc(ZBIT)) = '0' then
1948 
                                            next_state <= branch_state;
1949 
                                          else
1950 
                                            next_state <= fetch_state;
1951 
                                          end if;
1952 
                         when "0011" => -- bls
1953 
                                          if (cc(CBIT) or cc(ZBIT)) = '1' then
1954 
                                            next_state <= branch_state;
1955 
                                          else
1956 
                                            next_state <= fetch_state;
1957 
                                          end if;
1958 
                         when "0100" => -- bcc/bhs
1959 
                                          if cc(CBIT) = '0' then
1960 
                                            next_state <= branch_state;
1961 
                                          else
1962 
                                            next_state <= fetch_state;
1963 
                                          end if;
1964 
                         when "0101" => -- bcs/blo
1965 
                                          if cc(CBIT) = '1' then
1966 
                                            next_state <= branch_state;
1967 
                                          else
1968 
                                            next_state <= fetch_state;
1969 
                                          end if;
1970 
                         when "0110" => -- bne
1971 
                                          if cc(ZBIT) = '0' then
1972 
                                            next_state <= branch_state;
1973 
                                          else
1974 
                                            next_state <= fetch_state;
1975 
                                          end if;
1976 
                         when "0111" => -- beq
1977 
                                          if cc(ZBIT) = '1' then
1978 
                                            next_state <= branch_state;
1979 
                                          else
1980 
                                            next_state <= fetch_state;
1981 
                                          end if;
1982 
                         when "1000" => -- bvc
1983 
                                          if cc(VBIT) = '0' then
1984 
                                            next_state <= branch_state;
1985 
                                          else
1986 
                                            next_state <= fetch_state;
1987 
                                          end if;
1988 
                         when "1001" => -- bvs
1989 
                                          if cc(VBIT) = '1' then
1990 
                                            next_state <= branch_state;
1991 
                                          else
1992 
                                            next_state <= fetch_state;
1993 
                                          end if;
1994 
                         when "1010" => -- bpl
1995 
                                          if cc(NBIT) = '0' then
1996 
                                            next_state <= branch_state;
1997 
                                          else
1998 
                                            next_state <= fetch_state;
1999 
                                          end if;
2000 
                         when "1011" => -- bmi
2001 
                                          if cc(NBIT) = '1' then
2002 
                                            next_state <= branch_state;
2003 
                                          else
2004 
                                            next_state <= fetch_state;
2005 
                                          end if;
2006 
                         when "1100" => -- bge
2007 
                                          if (cc(NBIT) xor cc(VBIT)) = '0' then
2008 
                                            next_state <= branch_state;
2009 
                                          else
2010 
                                            next_state <= fetch_state;
2011 
                                          end if;
2012 
                         when "1101" => -- blt
2013 
                                          if (cc(NBIT) xor cc(VBIT)) = '1' then
2014 
                                            next_state <= branch_state;
2015 
                                          else
2016 
                                            next_state <= fetch_state;
2017 
                                          end if;
2018 
                         when "1110" => -- bgt
2019 
                                          if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0' then
2020 
                                            next_state <= branch_state;
2021 
                                          else
2022 
                                            next_state <= fetch_state;
2023 
                                          end if;
2024 
                         when "1111" => -- ble
2025 
                                          if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1' then
2026 
                                            next_state <= branch_state;
2027 
                                          else
2028 
                                            next_state <= fetch_state;
2029 
                                          end if;
2030 
                         when others =>
2031 
                                          next_state <= fetch_state;
2032 
                         end case;
2033 
                                 --
2034 
                                 -- Single byte stack operators
2035 
                                 -- Do not advance PC
2036 
                                 --
2037 
                  when "0011" =>
2038 
               ea_ctrl    <= fetch_first_ea;
2039 
                                   md_ctrl    <= fetch_first_md;
2040 
                                   op_ctrl    <= latch_op;
2041 
                                        acca_ctrl  <= latch_acca;
2042 
               accb_ctrl  <= latch_accb;
2043 
               pc_ctrl    <= latch_pc;
2044 
                    case op_code(3 downto 0) is
2045 
                         when "0000" => -- tsx / tsy
2046 
                            left_ctrl  <= sp_left;
2047 
                            right_ctrl <= one_right;
2048 
                                                alu_ctrl   <= alu_add16;
2049 
                                           cc_ctrl    <= latch_cc;
2050 
                  sp_ctrl    <= latch_sp;
2051 
                                           if pre_byte = "00011000" then
2052 4 dilbert57 
                                                  -- tsy
2053 2 dilbert57 
                                             ix_ctrl    <= latch_ix;
2054 
                                             iy_ctrl    <= load_iy;
2055 
                                           else
2056 4 dilbert57 
                                                  -- tsx
2057 2 dilbert57 
                                             ix_ctrl    <= load_ix;
2058 
                                             iy_ctrl    <= latch_iy;
2059 
                                           end if;
2060 
                                                next_state <= fetch_state;
2061 
                         when "0001" => -- ins
2062 
                  left_ctrl  <= sp_left;
2063 
                  right_ctrl <= one_right;
2064 
                  alu_ctrl   <= alu_add16;
2065 
                                           cc_ctrl    <= latch_cc;
2066 
                                                ix_ctrl    <= latch_ix;
2067 
                  iy_ctrl    <= latch_iy;
2068 
                  sp_ctrl    <= load_sp;
2069 
                                                next_state <= fetch_state;
2070 
                         when "0010" => -- pula
2071 
                  left_ctrl  <= sp_left;
2072 
                  right_ctrl <= one_right;
2073 
                  alu_ctrl   <= alu_add16;
2074 
                                           cc_ctrl    <= latch_cc;
2075 
                                                ix_ctrl    <= latch_ix;
2076 
                  iy_ctrl    <= latch_iy;
2077 
                  sp_ctrl    <= load_sp;
2078 
                                                next_state <= pula_state;
2079 
                         when "0011" => -- pulb
2080 
                  left_ctrl  <= sp_left;
2081 
                  right_ctrl <= one_right;
2082 
                  alu_ctrl   <= alu_add16;
2083 
                                           cc_ctrl    <= latch_cc;
2084 
                                                ix_ctrl    <= latch_ix;
2085 
                  iy_ctrl    <= latch_iy;
2086 
                  sp_ctrl    <= load_sp;
2087 
                                                next_state <= pulb_state;
2088 
                         when "0100" => -- des
2089 
                  -- decrement sp
2090 
                  left_ctrl  <= sp_left;
2091 
                  right_ctrl <= one_right;
2092 
                  alu_ctrl   <= alu_sub16;
2093 
                                           cc_ctrl    <= latch_cc;
2094 
                                                ix_ctrl    <= latch_ix;
2095 
                  iy_ctrl    <= latch_iy;
2096 
                  sp_ctrl    <= load_sp;
2097 
                                                next_state <= fetch_state;
2098 
                         when "0101" => -- txs / tys
2099 
                                           if pre_byte = "00011000" then
2100 4 dilbert57 
                                                  -- tys
2101 2 dilbert57 
                                             left_ctrl  <= iy_left;
2102 
                                           else
2103 4 dilbert57 
                                                  -- txs
2104 2 dilbert57 
                                             left_ctrl  <= ix_left;
2105 
                                           end if;
2106 
                            right_ctrl <= one_right;
2107 
                                                alu_ctrl   <= alu_sub16;
2108 
                                           cc_ctrl    <= latch_cc;
2109 
                                                ix_ctrl    <= latch_ix;
2110 
                                           iy_ctrl    <= latch_iy;
2111 
                                                sp_ctrl    <= load_sp;
2112 
                                                next_state <= fetch_state;
2113 
                         when "0110" => -- psha
2114 
                            left_ctrl  <= sp_left;
2115 
                            right_ctrl <= zero_right;
2116 
                                                alu_ctrl   <= alu_nop;
2117 
                                           cc_ctrl    <= latch_cc;
2118 
                                                ix_ctrl    <= latch_ix;
2119 
                  iy_ctrl    <= latch_iy;
2120 
                                                sp_ctrl    <= latch_sp;
2121 
                                                next_state <= psha_state;
2122 
                         when "0111" => -- pshb
2123 
                            left_ctrl  <= sp_left;
2124 
                            right_ctrl <= zero_right;
2125 
                                                alu_ctrl   <= alu_nop;
2126 
                                           cc_ctrl    <= latch_cc;
2127 
                                                ix_ctrl    <= latch_ix;
2128 
                  iy_ctrl    <= latch_iy;
2129 
                                                sp_ctrl    <= latch_sp;
2130 
                                                next_state <= pshb_state;
2131 4 dilbert57 
                         when "1000" => -- pulxy
2132 2 dilbert57 
                  left_ctrl  <= sp_left;
2133 
                  right_ctrl <= one_right;
2134 
                  alu_ctrl   <= alu_add16;
2135 
                                           cc_ctrl    <= latch_cc;
2136 
                                                ix_ctrl    <= latch_ix;
2137 
                  iy_ctrl    <= latch_iy;
2138 
                  sp_ctrl    <= load_sp;
2139 4 dilbert57 
                                                next_state <= pulxy_hi_state;
2140 2 dilbert57 
                         when "1001" => -- rts
2141 
                  left_ctrl  <= sp_left;
2142 
                  right_ctrl <= one_right;
2143 
                  alu_ctrl   <= alu_add16;
2144 
                                           cc_ctrl    <= latch_cc;
2145 
                                                ix_ctrl    <= latch_ix;
2146 
                  iy_ctrl    <= latch_iy;
2147 
                  sp_ctrl    <= load_sp;
2148 
                                                next_state <= rts_hi_state;
2149 
                         when "1010" => -- abx / aby
2150 
                                           if pre_byte = "00011000" then
2151 
                                             left_ctrl  <= iy_left;
2152 
                                                  ix_ctrl    <= latch_ix;
2153 
                    iy_ctrl    <= load_iy;
2154 
                                           else
2155 
                                             left_ctrl  <= ix_left;
2156 
                                                  ix_ctrl    <= load_ix;
2157 
                    iy_ctrl    <= latch_iy;
2158 
                                           end if;
2159 
                            right_ctrl <= accb_right;
2160 
                                                alu_ctrl   <= alu_add16;
2161 
                                           cc_ctrl    <= latch_cc;
2162 
                  sp_ctrl    <= latch_sp;
2163 
                                                next_state <= fetch_state;
2164 
                         when "1011" => -- rti
2165 
                  left_ctrl  <= sp_left;
2166 
                  right_ctrl <= one_right;
2167 
                  alu_ctrl   <= alu_add16;
2168 
                                           cc_ctrl    <= latch_cc;
2169 
                                                ix_ctrl    <= latch_ix;
2170 
                                                iy_ctrl    <= latch_iy;
2171 
                  sp_ctrl    <= load_sp;
2172 
                                                next_state <= rti_cc_state;
2173 4 dilbert57 
                         when "1100" => -- pshxy
2174 2 dilbert57 
                            left_ctrl  <= sp_left;
2175 
                            right_ctrl <= zero_right;
2176 
                                                alu_ctrl   <= alu_nop;
2177 
                                           cc_ctrl    <= latch_cc;
2178 
                                                ix_ctrl    <= latch_ix;
2179 
                                                iy_ctrl    <= latch_iy;
2180 
                                                sp_ctrl    <= latch_sp;
2181 4 dilbert57 
                                                next_state <= pshxy_lo_state;
2182 2 dilbert57 
                         when "1101" => -- mul
2183 
                            left_ctrl  <= acca_left;
2184 
                            right_ctrl <= accb_right;
2185 
                                                alu_ctrl   <= alu_add16;
2186 
                                           cc_ctrl    <= latch_cc;
2187 
                                                ix_ctrl    <= latch_ix;
2188 
                                                iy_ctrl    <= latch_iy;
2189 
                                                sp_ctrl    <= latch_sp;
2190 
                                                next_state <= mul_state;
2191 
                         when "1110" => -- wai
2192 
                            left_ctrl  <= sp_left;
2193 
                            right_ctrl <= zero_right;
2194 
                                                alu_ctrl   <= alu_nop;
2195 
                                           cc_ctrl    <= latch_cc;
2196 
                                                ix_ctrl    <= latch_ix;
2197 
                                                iy_ctrl    <= latch_iy;
2198 
                                                sp_ctrl    <= latch_sp;
2199 
                                                next_state <= int_pcl_state;
2200 
                         when "1111" => -- swi
2201 
                            left_ctrl  <= sp_left;
2202 
                            right_ctrl <= zero_right;
2203 
                                                alu_ctrl   <= alu_nop;
2204 
                                           cc_ctrl    <= latch_cc;
2205 
                                                ix_ctrl    <= latch_ix;
2206 
                                                iy_ctrl    <= latch_iy;
2207 
                                                sp_ctrl    <= latch_sp;
2208 
                                                next_state <= int_pcl_state;
2209 
                         when others =>
2210 
                            left_ctrl  <= sp_left;
2211 
                            right_ctrl <= zero_right;
2212 
                                                alu_ctrl   <= alu_nop;
2213 
                                           cc_ctrl    <= latch_cc;
2214 
                                                ix_ctrl    <= latch_ix;
2215 
                                                iy_ctrl    <= latch_iy;
2216 
                                                sp_ctrl    <= latch_sp;
2217 
                                                next_state <= fetch_state;
2218 
                         end case;
2219 
                                 --
2220 
                                 -- Accumulator A Single operand
2221 
                                 -- source = Acc A dest = Acc A
2222 
                                 -- Do not advance PC
2223 
                                 --
2224 
                  when "0100" => -- acca single op
2225 4 dilbert57 
               ea_ctrl    <= latch_ea;
2226 
                                   md_ctrl    <= latch_md;
2227 2 dilbert57 
                                   op_ctrl    <= latch_op;
2228 
               accb_ctrl  <= latch_accb;
2229 
               pc_ctrl    <= latch_pc;
2230 
                                   ix_ctrl    <= latch_ix;
2231 
                                   iy_ctrl    <= latch_iy;
2232 
                                   sp_ctrl    <= latch_sp;
2233 
                         left_ctrl  <= acca_left;
2234 
                    case op_code(3 downto 0) is
2235 
                         when "0000" => -- neg
2236 
                                          right_ctrl <= zero_right;
2237 
                                          alu_ctrl   <= alu_neg;
2238 
                                          acca_ctrl  <= load_acca;
2239 
                                          cc_ctrl    <= load_cc;
2240 
                    when "0011" => -- com
2241 
                           right_ctrl <= zero_right;
2242 
                                          alu_ctrl   <= alu_com;
2243 
                                          acca_ctrl  <= load_acca;
2244 
                                          cc_ctrl    <= load_cc;
2245 
                         when "0100" => -- lsr
2246 
                           right_ctrl <= zero_right;
2247 
                                          alu_ctrl   <= alu_lsr8;
2248 
                                          acca_ctrl  <= load_acca;
2249 
                                          cc_ctrl    <= load_cc;
2250 
                         when "0110" => -- ror
2251 
                           right_ctrl <= zero_right;
2252 
                                          alu_ctrl   <= alu_ror8;
2253 
                                          acca_ctrl  <= load_acca;
2254 
                                          cc_ctrl    <= load_cc;
2255 
                         when "0111" => -- asr
2256 
                           right_ctrl <= zero_right;
2257 
                                          alu_ctrl   <= alu_asr8;
2258 
                                          acca_ctrl  <= load_acca;
2259 
                                          cc_ctrl    <= load_cc;
2260 
                         when "1000" => -- asl
2261 
                           right_ctrl <= zero_right;
2262 
                                          alu_ctrl   <= alu_asl8;
2263 
                                          acca_ctrl  <= load_acca;
2264 
                                          cc_ctrl    <= load_cc;
2265 
                         when "1001" => -- rol
2266 
                           right_ctrl <= zero_right;
2267 
                                          alu_ctrl   <= alu_rol8;
2268 
                                          acca_ctrl  <= load_acca;
2269 
                                          cc_ctrl    <= load_cc;
2270 
                         when "1010" => -- dec
2271 
                           right_ctrl <= one_right;
2272 
                                          alu_ctrl   <= alu_dec;
2273 
                                          acca_ctrl  <= load_acca;
2274 
                                          cc_ctrl    <= load_cc;
2275 
                         when "1011" => -- undefined
2276 
                           right_ctrl <= zero_right;
2277 
                                          alu_ctrl   <= alu_nop;
2278 
                                          acca_ctrl  <= latch_acca;
2279 
                                          cc_ctrl    <= latch_cc;
2280 
                         when "1100" => -- inc
2281 
                           right_ctrl <= one_right;
2282 
                                          alu_ctrl   <= alu_inc;
2283 
                                          acca_ctrl  <= load_acca;
2284 
                                          cc_ctrl    <= load_cc;
2285 
                         when "1101" => -- tst
2286 
                           right_ctrl <= zero_right;
2287 
                                          alu_ctrl   <= alu_st8;
2288 
                                          acca_ctrl  <= latch_acca;
2289 
                                          cc_ctrl    <= load_cc;
2290 
                         when "1110" => -- jmp
2291 
                           right_ctrl <= zero_right;
2292 
                                          alu_ctrl   <= alu_nop;
2293 
                                          acca_ctrl  <= latch_acca;
2294 
                                          cc_ctrl    <= latch_cc;
2295 
                         when "1111" => -- clr
2296 
                           right_ctrl <= zero_right;
2297 4 dilbert57 
                                          alu_ctrl   <= alu_clr;
2298 2 dilbert57 
                                          acca_ctrl  <= load_acca;
2299 
                                          cc_ctrl    <= load_cc;
2300 
                         when others =>
2301 
                           right_ctrl <= zero_right;
2302 
                                          alu_ctrl   <= alu_nop;
2303 
                                          acca_ctrl  <= latch_acca;
2304 
                                          cc_ctrl    <= latch_cc;
2305 
                         end case;
2306 
                                   next_state <= fetch_state;
2307 
                                 --
2308 
                                 -- single operand acc b
2309 
                                 -- Do not advance PC
2310 
                                 --
2311 
                  when "0101" =>
2312 4 dilbert57 
               ea_ctrl    <= latch_ea;
2313 
                                   md_ctrl    <= latch_md;
2314 2 dilbert57 
                                   op_ctrl    <= latch_op;
2315 
               acca_ctrl  <= latch_acca;
2316 
               pc_ctrl    <= latch_pc;
2317 
                                   ix_ctrl    <= latch_ix;
2318 
                                   iy_ctrl    <= latch_iy;
2319 
                                   sp_ctrl    <= latch_sp;
2320 
                         left_ctrl  <= accb_left;
2321 
                    case op_code(3 downto 0) is
2322 
                         when "0000" => -- neg
2323 
                                          right_ctrl <= zero_right;
2324 
                                          alu_ctrl   <= alu_neg;
2325 
                                          accb_ctrl  <= load_accb;
2326 
                                          cc_ctrl    <= load_cc;
2327 
                    when "0011" => -- com
2328 
                           right_ctrl <= zero_right;
2329 
                                          alu_ctrl   <= alu_com;
2330 
                                          accb_ctrl  <= load_accb;
2331 
                                          cc_ctrl    <= load_cc;
2332 
                         when "0100" => -- lsr
2333 
                           right_ctrl <= zero_right;
2334 
                                          alu_ctrl   <= alu_lsr8;
2335 
                                          accb_ctrl  <= load_accb;
2336 
                                          cc_ctrl    <= load_cc;
2337 
                         when "0110" => -- ror
2338 
                           right_ctrl <= zero_right;
2339 
                                          alu_ctrl   <= alu_ror8;
2340 
                                          accb_ctrl  <= load_accb;
2341 
                                          cc_ctrl    <= load_cc;
2342 
                         when "0111" => -- asr
2343 
                           right_ctrl <= zero_right;
2344 
                                          alu_ctrl   <= alu_asr8;
2345 
                                          accb_ctrl  <= load_accb;
2346 
                                          cc_ctrl    <= load_cc;
2347 
                         when "1000" => -- asl
2348 
                           right_ctrl <= zero_right;
2349 
                                          alu_ctrl   <= alu_asl8;
2350 
                                          accb_ctrl  <= load_accb;
2351 
                                          cc_ctrl    <= load_cc;
2352 
                         when "1001" => -- rol
2353 
                           right_ctrl <= zero_right;
2354 
                                          alu_ctrl   <= alu_rol8;
2355 
                                          accb_ctrl  <= load_accb;
2356 
                                          cc_ctrl    <= load_cc;
2357 
                         when "1010" => -- dec
2358 
                           right_ctrl <= one_right;
2359 
                                          alu_ctrl   <= alu_dec;
2360 
                                          accb_ctrl  <= load_accb;
2361 
                                          cc_ctrl    <= load_cc;
2362 
                         when "1011" => -- undefined
2363 
                           right_ctrl <= zero_right;
2364 
                                          alu_ctrl   <= alu_nop;
2365 
                                          accb_ctrl  <= latch_accb;
2366 
                                          cc_ctrl    <= latch_cc;
2367 
                         when "1100" => -- inc
2368 
                           right_ctrl <= one_right;
2369 
                                          alu_ctrl   <= alu_inc;
2370 
                                          accb_ctrl  <= load_accb;
2371 
                                          cc_ctrl    <= load_cc;
2372 
                         when "1101" => -- tst
2373 
                           right_ctrl <= zero_right;
2374 
                                          alu_ctrl   <= alu_st8;
2375 
                                          accb_ctrl  <= latch_accb;
2376 
                                          cc_ctrl    <= load_cc;
2377 
                         when "1110" => -- jmp
2378 
                           right_ctrl <= zero_right;
2379 
                                          alu_ctrl   <= alu_nop;
2380 
                                          accb_ctrl  <= latch_accb;
2381 
                                          cc_ctrl    <= latch_cc;
2382 
                         when "1111" => -- clr
2383 
                           right_ctrl <= zero_right;
2384 4 dilbert57 
                                          alu_ctrl   <= alu_clr;
2385 2 dilbert57 
                                          accb_ctrl  <= load_accb;
2386 
                                          cc_ctrl    <= load_cc;
2387 
                         when others =>
2388 
                           right_ctrl <= zero_right;
2389 
                                          alu_ctrl   <= alu_nop;
2390 
                                          accb_ctrl  <= latch_accb;
2391 
                                          cc_ctrl    <= latch_cc;
2392 
                         end case;
2393 
                                   next_state <= fetch_state;
2394 
                                 --
2395 
                                 -- Single operand indexed
2396 
                                 -- Two byte instruction so advance PC
2397 
                                 -- EA should hold index offset
2398 
                                 --
2399 
                  when "0110" => -- indexed single op
2400 
               ea_ctrl    <= fetch_first_ea;
2401 
                                   md_ctrl    <= fetch_first_md;
2402 
                                   op_ctrl    <= latch_op;
2403 
               acca_ctrl  <= latch_acca;
2404 
                                        accb_ctrl  <= latch_accb;
2405 
                                   ix_ctrl    <= latch_ix;
2406 
                                   iy_ctrl    <= latch_iy;
2407 
                                   sp_ctrl    <= latch_sp;
2408 
                                        -- increment the pc
2409 
               left_ctrl  <= pc_left;
2410 
               right_ctrl <= one_right;
2411 
               alu_ctrl   <= alu_add16;
2412 
                                        cc_ctrl    <= latch_cc;
2413 
               pc_ctrl    <= load_pc;
2414 
                                   next_state <= indexed_state;
2415 
             --
2416 
                                 -- Single operand extended addressing
2417 
                                 -- three byte instruction so advance the PC
2418 
                                 -- Low order EA holds high order address
2419 
                                 --
2420 
                  when "0111" => -- extended single op
2421 
               ea_ctrl    <= fetch_first_ea;
2422 
                                   md_ctrl    <= fetch_first_md;
2423 
                                   op_ctrl    <= latch_op;
2424 
               acca_ctrl  <= latch_acca;
2425 
                                        accb_ctrl  <= latch_accb;
2426 
                                   ix_ctrl    <= latch_ix;
2427 
                                   iy_ctrl    <= latch_iy;
2428 
                                   sp_ctrl    <= latch_sp;
2429 
                                        -- increment the pc
2430 
               left_ctrl  <= pc_left;
2431 
               right_ctrl <= one_right;
2432 
               alu_ctrl   <= alu_add16;
2433 
                                        cc_ctrl    <= latch_cc;
2434 
               pc_ctrl    <= load_pc;
2435 
                                   next_state <= extended_state;
2436 
 
2437 
                  when "1000" => -- acca immediate
2438 4 dilbert57 
               ea_ctrl    <= fetch_first_ea;    -- for BSR
2439 2 dilbert57 
                                   op_ctrl    <= latch_op;
2440 
               acca_ctrl  <= latch_acca;
2441 
                                        accb_ctrl  <= latch_accb;
2442 
                                   ix_ctrl    <= latch_ix;
2443 
                                   iy_ctrl    <= latch_iy;
2444 
                                   sp_ctrl    <= latch_sp;
2445 
                                        cc_ctrl    <= latch_cc;
2446 
                                        case op_code(3 downto 0) is
2447 
               when "0011" | -- subd #
2448 
                                             "1100" | -- cpx / cpy #
2449 
                                             "1110" => -- lds #
2450 
                                     -- increment the pc
2451 
                                     md_ctrl    <= fetch_first_md;
2452 
                 left_ctrl  <= pc_left;
2453 
                 right_ctrl <= one_right;
2454 
                 alu_ctrl   <= alu_add16;
2455 
                 pc_ctrl    <= load_pc;
2456 
                                          next_state <= immediate16_state;
2457 
                                        when "1101" => -- bsr
2458 
                                     -- increment the pc
2459 
                                     md_ctrl    <= fetch_first_md;
2460 
                 left_ctrl  <= pc_left;
2461 
                 right_ctrl <= one_right;
2462 
                 alu_ctrl   <= alu_add16;
2463 
                 pc_ctrl    <= load_pc;
2464 
                                          next_state <= bsr_state;
2465 
                                        when "1111" => -- egdx /egdy
2466 
                                          -- idle pc
2467 
                 left_ctrl  <= accd_left;
2468 
                 right_ctrl <= zero_right;
2469 
                 alu_ctrl   <= alu_st16;
2470 
                 pc_ctrl    <= latch_pc;
2471 
                                     md_ctrl    <= load_md;
2472 4 dilbert57 
                                          next_state <= exchange_state;
2473 2 dilbert57 
                                        when others =>
2474 
                                     md_ctrl    <= fetch_first_md;
2475 
                 left_ctrl  <= pc_left;
2476 
                 right_ctrl <= one_right;
2477 
                 alu_ctrl   <= alu_add16;
2478 
                 pc_ctrl    <= load_pc;
2479 4 dilbert57 
                                     next_state <= fetch_state;
2480 2 dilbert57 
               end case;
2481 
 
2482 
                  when "1001" => -- acca direct
2483 
               ea_ctrl    <= fetch_first_ea;
2484 
                                   op_ctrl    <= latch_op;
2485 
               acca_ctrl  <= latch_acca;
2486 
                                        accb_ctrl  <= latch_accb;
2487 
                                   ix_ctrl    <= latch_ix;
2488 
                                   iy_ctrl    <= latch_iy;
2489 
                                   sp_ctrl    <= latch_sp;
2490 
                                        -- increment the pc
2491 4 dilbert57 
               pc_ctrl    <= incr_pc;
2492 2 dilbert57 
                                        case op_code(3 downto 0) is
2493 4 dilbert57 
                                        when "0111" =>  -- staa direct
2494 
                 left_ctrl  <= acca_left;
2495 
                 right_ctrl <= zero_right;
2496 
                 alu_ctrl   <= alu_st8;
2497 
                                          cc_ctrl    <= latch_cc;
2498 
                                     md_ctrl    <= load_md;
2499 
                                     next_state <= write8_state;
2500 
                                        when "1111" => -- sts direct
2501 
                 left_ctrl  <= sp_left;
2502 
                 right_ctrl <= zero_right;
2503 
                 alu_ctrl   <= alu_st16;
2504 
                                          cc_ctrl    <= latch_cc;
2505 
                                     md_ctrl    <= load_md;
2506 
                                     next_state <= write16_state;
2507 2 dilbert57 
                                        when "1101" => -- jsr direct
2508 4 dilbert57 
                 left_ctrl  <= acca_left;
2509 
                 right_ctrl <= zero_right;
2510 
                 alu_ctrl   <= alu_nop;
2511 
                                          cc_ctrl    <= latch_cc;
2512 
                                     md_ctrl    <= fetch_first_md;
2513 2 dilbert57 
                                          next_state <= jsr_state;
2514 
                                        when others =>
2515 4 dilbert57 
                 left_ctrl  <= acca_left;
2516 
                 right_ctrl <= zero_right;
2517 
                 alu_ctrl   <= alu_nop;
2518 
                                          cc_ctrl    <= latch_cc;
2519 
                                     md_ctrl    <= fetch_first_md;
2520 
                                     next_state <= read8_state;
2521 2 dilbert57 
               end case;
2522 
 
2523 
                  when "1010" => -- acca indexed
2524 
               ea_ctrl    <= fetch_first_ea;
2525 
                                   md_ctrl    <= fetch_first_md;
2526 
                                   op_ctrl    <= latch_op;
2527 
               acca_ctrl  <= latch_acca;
2528 
                                        accb_ctrl  <= latch_accb;
2529 
                                   ix_ctrl    <= latch_ix;
2530 
                                   iy_ctrl    <= latch_iy;
2531 
                                   sp_ctrl    <= latch_sp;
2532 
                                        -- increment the pc
2533 
               left_ctrl  <= pc_left;
2534 
               right_ctrl <= one_right;
2535 
               alu_ctrl   <= alu_add16;
2536 
                                        cc_ctrl    <= latch_cc;
2537 
               pc_ctrl    <= load_pc;
2538 
                                   next_state <= indexed_state;
2539 
 
2540 
             when "1011" => -- acca extended
2541 
               ea_ctrl    <= fetch_first_ea;
2542 
                                   md_ctrl    <= fetch_first_md;
2543 
                                   op_ctrl    <= latch_op;
2544 
               acca_ctrl  <= latch_acca;
2545 
                                        accb_ctrl  <= latch_accb;
2546 
                                   ix_ctrl    <= latch_ix;
2547 
                                   iy_ctrl    <= latch_iy;
2548 
                                   sp_ctrl    <= latch_sp;
2549 
                                        -- increment the pc
2550 
               left_ctrl  <= pc_left;
2551 
               right_ctrl <= one_right;
2552 
               alu_ctrl   <= alu_add16;
2553 
                                        cc_ctrl    <= latch_cc;
2554 
               pc_ctrl    <= load_pc;
2555 
                                   next_state <= extended_state;
2556 
 
2557 
                  when "1100" => -- accb immediate
2558 4 dilbert57 
               ea_ctrl    <= latch_ea;
2559 2 dilbert57 
                                   md_ctrl    <= fetch_first_md;
2560 
               acca_ctrl  <= latch_acca;
2561 
                                        accb_ctrl  <= latch_accb;
2562 
                                   ix_ctrl    <= latch_ix;
2563 
                                   iy_ctrl    <= latch_iy;
2564 
                                   sp_ctrl    <= latch_sp;
2565 
                                        -- increment the pc
2566 
               left_ctrl  <= pc_left;
2567 
               right_ctrl <= one_right;
2568 
               alu_ctrl   <= alu_add16;
2569 
                                        cc_ctrl    <= latch_cc;
2570 
               pc_ctrl    <= load_pc;
2571 
                                        case op_code(3 downto 0) is
2572 
               when "0011" | -- addd #
2573 
                                             "1100" | -- ldd #
2574 4 dilbert57 
                                             "1110" => -- ldx # / ldy #
2575 2 dilbert57 
                                     op_ctrl    <= latch_op;
2576 
                                          next_state <= immediate16_state;
2577 
                                        when "1101" => -- indexed Y pre-byte $CD
2578 
                                     op_ctrl    <= fetch_op;
2579 
                                          next_state <= decode_state;
2580 
                                        when others =>
2581 
                                     op_ctrl    <= latch_op;
2582 4 dilbert57 
                                     next_state <= fetch_state;
2583 2 dilbert57 
               end case;
2584 
 
2585 
                  when "1101" => -- accb direct
2586 
               ea_ctrl    <= fetch_first_ea;
2587 
                                   md_ctrl    <= fetch_first_md;
2588 
                                   op_ctrl    <= latch_op;
2589 
               acca_ctrl  <= latch_acca;
2590 
                                        accb_ctrl  <= latch_accb;
2591 
                                   ix_ctrl    <= latch_ix;
2592 
                                   iy_ctrl    <= latch_iy;
2593 
                                   sp_ctrl    <= latch_sp;
2594 4 dilbert57 
               pc_ctrl    <= incr_pc;
2595 2 dilbert57 
                                        case op_code(3 downto 0) is
2596 4 dilbert57 
                                        when "0111" =>  -- stab direct
2597 
                 left_ctrl  <= accb_left;
2598 
                 right_ctrl <= zero_right;
2599 
                 alu_ctrl   <= alu_st8;
2600 
                                          cc_ctrl    <= latch_cc;
2601 
                                     md_ctrl    <= load_md;
2602 
                                     next_state <= write8_state;
2603 
                                        when "1101" => -- std direct
2604 
                 left_ctrl  <= accd_left;
2605 
                 right_ctrl <= zero_right;
2606 
                 alu_ctrl   <= alu_st16;
2607 
                                          cc_ctrl    <= latch_cc;
2608 
                                     md_ctrl    <= load_md;
2609 
                                          next_state <= write16_state;
2610 
                                        when "1111" => -- stx / sty direct
2611 
                                          if( pre_byte = "00011000" ) or (pre_byte = "00011010" ) then
2612 
                                            left_ctrl  <= iy_left;
2613 
                 else
2614 
                   left_ctrl  <= ix_left;
2615 
                 end if;
2616 
                 right_ctrl <= zero_right;
2617 
                 alu_ctrl   <= alu_st16;
2618 
                                          cc_ctrl    <= latch_cc;
2619 
                                     md_ctrl    <= load_md;
2620 
                                     next_state <= write16_state;
2621 2 dilbert57 
                                        when others =>
2622 4 dilbert57 
                 left_ctrl  <= acca_left;
2623 
                 right_ctrl <= zero_right;
2624 
                 alu_ctrl   <= alu_nop;
2625 
                                          cc_ctrl    <= latch_cc;
2626 
                                     md_ctrl    <= fetch_first_md;
2627 
                                     next_state <= read8_state;
2628 2 dilbert57 
               end case;
2629 
 
2630 
                  when "1110" => -- accb indexed
2631 
               ea_ctrl    <= fetch_first_ea;
2632 
                                   md_ctrl    <= fetch_first_md;
2633 
                                   op_ctrl    <= latch_op;
2634 
               acca_ctrl  <= latch_acca;
2635 
                                        accb_ctrl  <= latch_accb;
2636 
                                   ix_ctrl    <= latch_ix;
2637 
                                   iy_ctrl    <= latch_iy;
2638 
                                   sp_ctrl    <= latch_sp;
2639 
                                        -- increment the pc
2640 
               left_ctrl  <= pc_left;
2641 
               right_ctrl <= one_right;
2642 
               alu_ctrl   <= alu_add16;
2643 
                                        cc_ctrl    <= latch_cc;
2644 
               pc_ctrl    <= load_pc;
2645 
                                   next_state <= indexed_state;
2646 
 
2647 
             when "1111" => -- accb extended
2648 
               ea_ctrl    <= fetch_first_ea;
2649 
                                   md_ctrl    <= fetch_first_md;
2650 
                                   op_ctrl    <= latch_op;
2651 
               acca_ctrl  <= latch_acca;
2652 
                                        accb_ctrl  <= latch_accb;
2653 
                                   ix_ctrl    <= latch_ix;
2654 
                                   iy_ctrl    <= latch_iy;
2655 
                                   sp_ctrl    <= latch_sp;
2656 
                                        -- increment the pc
2657 
               left_ctrl  <= pc_left;
2658 
               right_ctrl <= one_right;
2659 
               alu_ctrl   <= alu_add16;
2660 
                                        cc_ctrl    <= latch_cc;
2661 
               pc_ctrl    <= load_pc;
2662 
                                   next_state <= extended_state;
2663 
 
2664 
                  when others =>
2665 
               ea_ctrl    <= fetch_first_ea;
2666 
                                   md_ctrl    <= fetch_first_md;
2667 
                                   op_ctrl    <= latch_op;
2668 
               acca_ctrl  <= latch_acca;
2669 
                                        accb_ctrl  <= latch_accb;
2670 
                                   ix_ctrl    <= latch_ix;
2671 
                                   iy_ctrl    <= latch_iy;
2672 
                                   sp_ctrl    <= latch_sp;
2673 
                                        -- idle the pc
2674 
               left_ctrl  <= pc_left;
2675 
               right_ctrl <= zero_right;
2676 
               alu_ctrl   <= alu_nop;
2677 
                                        cc_ctrl    <= latch_cc;
2678 
               pc_ctrl    <= latch_pc;
2679 
                         next_state <= fetch_state;
2680 
             end case;
2681 
 
2682 
                          when immediate16_state =>
2683 
             acca_ctrl  <= latch_acca;
2684 
             accb_ctrl  <= latch_accb;
2685 
             ix_ctrl    <= latch_ix;
2686 
                                 iy_ctrl    <= latch_iy;
2687 
             sp_ctrl    <= latch_sp;
2688 
                            op_ctrl    <= latch_op;
2689 
                                 pre_ctrl   <= latch_pre;
2690 
                                 pre_ctrl   <= latch_pre;
2691 
             iv_ctrl    <= latch_iv;
2692 
                                 count_ctrl <= reset_count;
2693 
             ea_ctrl    <= latch_ea;
2694 
                                 -- increment pc
2695 
             left_ctrl  <= pc_left;
2696 
             right_ctrl <= one_right;
2697 
             alu_ctrl   <= alu_add16;
2698 
             cc_ctrl    <= latch_cc;
2699 
             pc_ctrl    <= load_pc;
2700 
                                 -- fetch next immediate byte
2701 
                            md_ctrl    <= fetch_next_md;
2702 
             addr_ctrl  <= fetch_ad;
2703 
             dout_ctrl  <= md_lo_dout;
2704 4 dilbert57 
                                 next_state <= fetch_state;
2705 2 dilbert57 
           --
2706 
                          -- ea holds 8 bit index offet
2707 
                          -- calculate the effective memory address
2708 
                          -- using the alu
2709 
                          --
2710 
           when indexed_state =>
2711 
             acca_ctrl  <= latch_acca;
2712 
             accb_ctrl  <= latch_accb;
2713 
             sp_ctrl    <= latch_sp;
2714 
             pc_ctrl    <= latch_pc;
2715 
             iv_ctrl    <= latch_iv;
2716 
                                 count_ctrl <= reset_count;
2717 
                            op_ctrl    <= latch_op;
2718 
                                 pre_ctrl   <= latch_pre;
2719 4 dilbert57 
                                 ix_ctrl    <= latch_ix;
2720 
                            iy_ctrl    <= latch_iy;
2721 
                                 -- idle bus.
2722 
             addr_ctrl  <= idle_ad;
2723 
             dout_ctrl  <= md_lo_dout;
2724 
                                 -- add 8 bit ea to ix or iy
2725 
                                 if(( pre_byte = "00011000") or (pre_byte = "00011010")) then
2726 
                                   ea_ctrl    <= add_iy_ea;
2727 2 dilbert57 
                                 else
2728 4 dilbert57 
                                   ea_ctrl    <= add_ix_ea;
2729 2 dilbert57 
                                 end if;
2730 
                                 case op_code(7 downto 4) is
2731 4 dilbert57 
                                 when "0001" => -- BSET, BCLR, BRSET, BRCLR
2732 
                              left_ctrl  <= acca_left;
2733 
                                   right_ctrl <= zero_right;
2734 
                                   alu_ctrl   <= alu_nop;
2735 
               cc_ctrl    <= latch_cc;
2736 
               md_ctrl    <= latch_md;
2737 
                    case op_code(3 downto 0) is
2738 
                                        when "1100" |  -- BSET
2739 
                                          "1101" |  -- BCLR
2740 
                                                  "1110" |  -- BRSET
2741 
                                                  "1111" => -- BRCLR
2742 
                 next_state <= read8_state;
2743 
               when others =>
2744 
                                          next_state <= fetch_state;
2745 
               end case;
2746 2 dilbert57 
                                 when "0110" => -- single op indexed
2747 
                    case op_code(3 downto 0) is
2748 
                         when "1011" => -- undefined
2749 4 dilbert57 
                                left_ctrl  <= acca_left;
2750 
                                     right_ctrl <= zero_right;
2751 
                                     alu_ctrl   <= alu_nop;
2752 
                 cc_ctrl    <= latch_cc;
2753 
                 md_ctrl    <= latch_md;
2754 2 dilbert57 
                                          next_state <= fetch_state;
2755 
                         when "1110" => -- jmp
2756 4 dilbert57 
                                left_ctrl  <= acca_left;
2757 
                                     right_ctrl <= zero_right;
2758 
                                     alu_ctrl   <= alu_nop;
2759 
                 cc_ctrl    <= latch_cc;
2760 
                 md_ctrl    <= latch_md;
2761 2 dilbert57 
                                          next_state <= jmp_state;
2762 4 dilbert57 
                                        when "1111" => -- clr
2763 
                                left_ctrl  <= acca_left;
2764 
                                     right_ctrl <= zero_right;
2765 
                                     alu_ctrl   <= alu_st8;
2766 
                 cc_ctrl    <= latch_cc;
2767 
                 md_ctrl    <= load_md;
2768 
                                          next_state <= write8_state;
2769 2 dilbert57 
                         when others =>
2770 4 dilbert57 
                                left_ctrl  <= acca_left;
2771 
                                     right_ctrl <= zero_right;
2772 
                                     alu_ctrl   <= alu_nop;
2773 
                 cc_ctrl    <= latch_cc;
2774 
                 md_ctrl    <= latch_md;
2775 
                                          next_state <= read8_state;
2776 2 dilbert57 
                         end case;
2777 
                  when "1010" => -- acca indexed
2778 
                                   case op_code(3 downto 0) is
2779 4 dilbert57 
                                        when "0111" =>  -- staa
2780 
                                left_ctrl  <= acca_left;
2781 
                                     right_ctrl <= zero_right;
2782 
                                     alu_ctrl   <= alu_st8;
2783 
                 cc_ctrl    <= latch_cc;
2784 
                 md_ctrl    <= load_md;
2785 
                                     next_state <= write8_state;
2786 2 dilbert57 
                                        when "1101" => -- jsr
2787 4 dilbert57 
                                left_ctrl  <= acca_left;
2788 
                                     right_ctrl <= zero_right;
2789 
                                     alu_ctrl   <= alu_nop;
2790 
                 cc_ctrl    <= latch_cc;
2791 
                 md_ctrl    <= latch_md;
2792 2 dilbert57 
                                          next_state <= jsr_state;
2793 4 dilbert57 
                                        when "1111" => -- sts
2794 
                                left_ctrl  <= sp_left;
2795 
                                     right_ctrl <= zero_right;
2796 
                                     alu_ctrl   <= alu_st16;
2797 
                 cc_ctrl    <= latch_cc;
2798 
                 md_ctrl    <= load_md;
2799 
                                     next_state <= write16_state;
2800 2 dilbert57 
                                        when others =>
2801 4 dilbert57 
                                left_ctrl  <= acca_left;
2802 
                                     right_ctrl <= zero_right;
2803 
                                     alu_ctrl   <= alu_nop;
2804 
                 cc_ctrl    <= latch_cc;
2805 
                 md_ctrl    <= latch_md;
2806 
                                          next_state <= read8_state;
2807 2 dilbert57 
                                        end case;
2808 
                  when "1110" => -- accb indexed
2809 
                                   case op_code(3 downto 0) is
2810 4 dilbert57 
                                        when "0111" =>  -- stab direct
2811 
                                left_ctrl  <= accb_left;
2812 
                                     right_ctrl <= zero_right;
2813 
                                     alu_ctrl   <= alu_st8;
2814 
                 cc_ctrl    <= latch_cc;
2815 
                 md_ctrl    <= load_md;
2816 
                                     next_state <= write8_state;
2817 
                                        when "1101" => -- std direct
2818 
                                left_ctrl  <= accd_left;
2819 
                                     right_ctrl <= zero_right;
2820 
                                     alu_ctrl   <= alu_st16;
2821 
                 cc_ctrl    <= latch_cc;
2822 
                 md_ctrl    <= load_md;
2823 
                                          next_state <= write16_state;
2824 
                                        when "1111" => -- stx / sty direct
2825 
                                          if( pre_byte = "00011000" ) or (pre_byte = "00011010" ) then
2826 
                                            left_ctrl  <= iy_left;
2827 
                 else
2828 
                   left_ctrl  <= ix_left;
2829 
                 end if;
2830 
                 right_ctrl <= zero_right;
2831 
                 alu_ctrl   <= alu_st16;
2832 
                                          cc_ctrl    <= latch_cc;
2833 
                                     md_ctrl    <= load_md;
2834 
                                     next_state <= write16_state;
2835 2 dilbert57 
                                        when others =>
2836 4 dilbert57 
                                left_ctrl  <= acca_left;
2837 
                                     right_ctrl <= zero_right;
2838 
                                     alu_ctrl   <= alu_nop;
2839 
                 cc_ctrl    <= latch_cc;
2840 
                 md_ctrl    <= latch_md;
2841 
                                          next_state <= read8_state;
2842 2 dilbert57 
                                        end case;
2843 
                            when others =>
2844 4 dilbert57 
                              left_ctrl  <= acca_left;
2845 
                                   right_ctrl <= zero_right;
2846 
                                   alu_ctrl   <= alu_nop;
2847 
               cc_ctrl    <= latch_cc;
2848 
               md_ctrl    <= latch_md;
2849 2 dilbert57 
                                        next_state <= fetch_state;
2850 
                            end case;
2851 
           --
2852 4 dilbert57 
                          -- ea holds 8 bit index offet
2853 
                          -- calculate the effective memory address
2854 
                          -- using the alu
2855 
                          --
2856 
           --
2857 2 dilbert57 
                          -- ea holds the low byte of the absolute address
2858 
                          -- Move ea low byte into ea high byte
2859 
                          -- load new ea low byte to for absolute 16 bit address
2860 
                          -- advance the program counter
2861 
                          --
2862 
                          when extended_state => -- fetch ea low byte
2863 4 dilbert57 
               acca_ctrl  <= latch_acca;
2864 
               accb_ctrl  <= latch_accb;
2865 
               ix_ctrl    <= latch_ix;
2866 
               iy_ctrl    <= latch_iy;
2867 
               sp_ctrl    <= latch_sp;
2868 
               iv_ctrl    <= latch_iv;
2869 
                                   count_ctrl <= reset_count;
2870 
                              op_ctrl    <= latch_op;
2871 
                                   pre_ctrl   <= latch_pre;
2872 
                                        -- increment pc
2873 
               pc_ctrl    <= incr_pc;
2874 
                                        -- fetch next effective address bytes
2875 
                                        ea_ctrl    <= fetch_next_ea;
2876 
               addr_ctrl  <= fetch_ad;
2877 
                                        dout_ctrl  <= md_lo_dout;
2878 
                                        -- work out the next state
2879 
                                   case op_code(7 downto 4) is
2880 
                                   when "0111" => -- single op extended
2881 2 dilbert57 
                      case op_code(3 downto 0) is
2882 4 dilbert57 
                           when "1011" => -- undefined
2883 
                                  left_ctrl  <= acca_left;
2884 
                                       right_ctrl <= zero_right;
2885 
                                       alu_ctrl   <= alu_nop;
2886 
                   cc_ctrl    <= latch_cc;
2887 
                   md_ctrl    <= latch_md;
2888 
                                            next_state <= fetch_state;
2889 
                           when "1110" => -- jmp
2890 
                                  left_ctrl  <= acca_left;
2891 
                                       right_ctrl <= zero_right;
2892 
                                       alu_ctrl   <= alu_nop;
2893 
                   cc_ctrl    <= latch_cc;
2894 
                   md_ctrl    <= latch_md;
2895 
                                            next_state <= jmp_state;
2896 
                           when "1111" => -- clr
2897 
                                  left_ctrl  <= acca_left;
2898 
                                       right_ctrl <= zero_right;
2899 
                                       alu_ctrl   <= alu_ld8;
2900 
                   cc_ctrl    <= latch_cc;
2901 
                   md_ctrl    <= load_md;
2902 
                                            next_state <= write8_state;
2903 
                           when others =>
2904 
                                  left_ctrl  <= acca_left;
2905 
                                       right_ctrl <= zero_right;
2906 
                                       alu_ctrl   <= alu_nop;
2907 
                   cc_ctrl    <= latch_cc;
2908 
                   md_ctrl    <= latch_md;
2909 
                                            next_state <= read8_state;
2910 2 dilbert57 
                           end case;
2911 
                    when "1011" => -- acca extended
2912 
                                     case op_code(3 downto 0) is
2913 4 dilbert57 
                                          when "0111" =>  -- staa
2914 
                                  left_ctrl  <= acca_left;
2915 
                                       right_ctrl <= zero_right;
2916 
                                       alu_ctrl   <= alu_st8;
2917 
                   cc_ctrl    <= latch_cc;
2918 
                   md_ctrl    <= load_md;
2919 
                                       next_state <= write8_state;
2920 
                                          when "1101" => -- jsr
2921 
                                  left_ctrl  <= acca_left;
2922 
                                       right_ctrl <= zero_right;
2923 
                                       alu_ctrl   <= alu_nop;
2924 
                   cc_ctrl    <= latch_cc;
2925 
                   md_ctrl    <= latch_md;
2926 
                                            next_state <= jsr_state;
2927 
                                          when "1111" => -- sts
2928 
                                  left_ctrl  <= sp_left;
2929 
                                       right_ctrl <= zero_right;
2930 
                                       alu_ctrl   <= alu_st16;
2931 
                   cc_ctrl    <= latch_cc;
2932 
                   md_ctrl    <= load_md;
2933 
                                       next_state <= write16_state;
2934 
                                          when others =>
2935 
                                  left_ctrl  <= acca_left;
2936 
                                       right_ctrl <= zero_right;
2937 
                                       alu_ctrl   <= alu_nop;
2938 
                   cc_ctrl    <= latch_cc;
2939 
                   md_ctrl    <= latch_md;
2940 
                                            next_state <= read8_state;
2941 2 dilbert57 
                                          end case;
2942 
                    when "1111" => -- accb extended
2943 
                                     case op_code(3 downto 0) is
2944 4 dilbert57 
                                          when "0111" =>  -- stab
2945 
                                  left_ctrl  <= accb_left;
2946 
                                       right_ctrl <= zero_right;
2947 
                                       alu_ctrl   <= alu_st8;
2948 
                   cc_ctrl    <= latch_cc;
2949 
                   md_ctrl    <= load_md;
2950 
                                       next_state <= write8_state;
2951 
                                          when "1101" => -- std
2952 
                                  left_ctrl  <= accd_left;
2953 
                                       right_ctrl <= zero_right;
2954 
                                       alu_ctrl   <= alu_st16;
2955 
                   cc_ctrl    <= latch_cc;
2956 
                   md_ctrl    <= load_md;
2957 
                                            next_state <= write16_state;
2958 
                                          when "1111" => -- stx / sty
2959 
                                            if(( pre_byte = "00011000" ) or ( pre_byte = "00011010" )) then
2960 
                                              left_ctrl <= iy_left;
2961 
                                            else
2962 
                                    left_ctrl <= ix_left;
2963 
                                            end if;
2964 
                                       right_ctrl <= zero_right;
2965 
                                       alu_ctrl   <= alu_st16;
2966 
                   cc_ctrl    <= latch_cc;
2967 
                   md_ctrl    <= load_md;
2968 
                                       next_state <= write16_state;
2969 
                                          when others =>
2970 
                                  left_ctrl  <= acca_left;
2971 
                                       right_ctrl <= zero_right;
2972 
                                       alu_ctrl   <= alu_nop;
2973 
                   cc_ctrl    <= latch_cc;
2974 
                   md_ctrl    <= latch_md;
2975 
                                            next_state <= read8_state;
2976 2 dilbert57 
                                          end case;
2977 4 dilbert57 
                              when others =>
2978 
                 md_ctrl    <= latch_md;
2979 
                                left_ctrl  <= acca_left;
2980 
                                     right_ctrl <= zero_right;
2981 
                                     alu_ctrl   <= alu_nop;
2982 
                 cc_ctrl    <= latch_cc;
2983 
                                          next_state <= fetch_state;
2984 
                              end case;
2985 2 dilbert57 
           --
2986 
                          -- here if ea holds low byte (direct page)
2987 
                          -- can enter here from extended addressing
2988 
                          -- read memory location
2989 
                          -- note that reads may be 8 or 16 bits
2990 
                          --
2991 4 dilbert57 
                          when read8_state => -- read data
2992 2 dilbert57 
             acca_ctrl  <= latch_acca;
2993 
             accb_ctrl  <= latch_accb;
2994 
             ix_ctrl    <= latch_ix;
2995 
             iy_ctrl    <= latch_iy;
2996 
             sp_ctrl    <= latch_sp;
2997 
             iv_ctrl    <= latch_iv;
2998 
                                 count_ctrl <= reset_count;
2999 
                            op_ctrl    <= latch_op;
3000 
                                 pre_ctrl   <= latch_pre;
3001 
                                 -- read first data byte from ea
3002 
                                 md_ctrl    <= fetch_first_md;
3003 
             addr_ctrl  <= read_ad;
3004 
                                 dout_ctrl  <= md_lo_dout;
3005 
                            case op_code(7 downto 4) is
3006 4 dilbert57 
                                   when "0001" => -- bset / bclr / brset / brclr
3007 2 dilbert57 
                                          left_ctrl  <= pc_left;
3008 
                                          right_ctrl <= one_right;
3009 
                                          alu_ctrl   <= alu_add16;
3010 
                 cc_ctrl    <= latch_cc;
3011 
                                          ea_ctrl    <= latch_ea;
3012 
                 pc_ctrl    <= load_pc;
3013 
                                          next_state <= bitmask_state;
3014 
                                        when "0110" | "0111" => -- single operand
3015 
                                          left_ctrl  <= ea_left;
3016 
                                          right_ctrl <= zero_right;
3017 
                                          alu_ctrl   <= alu_nop;
3018 
                 cc_ctrl    <= latch_cc;
3019 
                                          ea_ctrl    <= latch_ea;
3020 
                 pc_ctrl    <= latch_pc;
3021 
                                          next_state <= execute_state;
3022 
                    when "1001" | "1010" | "1011" => -- acca
3023 
                 pc_ctrl    <= latch_pc;
3024 
                                     case op_code(3 downto 0) is
3025 
                                            when "0011" |  -- subd / cpd
3026 
                                                 "1110" |  -- lds
3027 
                                                 "1100" => -- cpx / cpy
3028 
                                         -- increment the effective address in case of 16 bit load
3029 
                                              left_ctrl  <= ea_left;
3030 
                                              right_ctrl <= one_right;
3031 
                                              alu_ctrl   <= alu_add16;
3032 
                     cc_ctrl    <= latch_cc;
3033 
                                              ea_ctrl    <= load_ea;
3034 4 dilbert57 
                                              next_state <= read16_state;
3035 2 dilbert57 
                                            when others =>
3036 
                                              left_ctrl  <= ea_left;
3037 
                                              right_ctrl <= zero_right;
3038 
                                              alu_ctrl   <= alu_nop;
3039 
                     cc_ctrl    <= latch_cc;
3040 
                                              ea_ctrl    <= latch_ea;
3041 4 dilbert57 
                                              next_state <= fetch_state;
3042 2 dilbert57 
                                          end case;
3043 
                    when "1101" | "1110" | "1111" => -- accb
3044 
                 pc_ctrl    <= latch_pc;
3045 
                                     case op_code(3 downto 0) is
3046 
                                            when "0011" |  -- addd
3047 
                                                 "1100" |  -- ldd
3048 
                                                 "1110" => -- ldx / ldy
3049 
                                         -- increment the effective address in case of 16 bit load
3050 
                                              left_ctrl  <= ea_left;
3051 
                                              right_ctrl <= one_right;
3052 
                                              alu_ctrl   <= alu_add16;
3053 
                     cc_ctrl    <= latch_cc;
3054 
                                              ea_ctrl    <= load_ea;
3055 4 dilbert57 
                                              next_state <= read16_state;
3056 2 dilbert57 
                                            when others =>
3057 
                                              left_ctrl  <= ea_left;
3058 
                                              right_ctrl <= zero_right;
3059 
                                              alu_ctrl   <= alu_nop;
3060 
                     cc_ctrl    <= latch_cc;
3061 
                                              ea_ctrl    <= latch_ea;
3062 4 dilbert57 
                                              next_state <= fetch_state;
3063 2 dilbert57 
                                          end case;
3064 
                                        when others =>
3065 
                                          left_ctrl  <= ea_left;
3066 
                                          right_ctrl <= zero_right;
3067 
                                          alu_ctrl   <= alu_nop;
3068 
                 cc_ctrl    <= latch_cc;
3069 
                                          ea_ctrl    <= latch_ea;
3070 
                 pc_ctrl    <= latch_pc;
3071 
                                          next_state <= fetch_state;
3072 
                            end case;
3073 
 
3074 4 dilbert57 
                          when read16_state => -- read second data byte from ea
3075 2 dilbert57 
                 -- default
3076 
             acca_ctrl  <= latch_acca;
3077 
             accb_ctrl  <= latch_accb;
3078 
             ix_ctrl    <= latch_ix;
3079 
             iy_ctrl    <= latch_iy;
3080 
             sp_ctrl    <= latch_sp;
3081 
             pc_ctrl    <= latch_pc;
3082 
             iv_ctrl    <= latch_iv;
3083 
                                 count_ctrl <= reset_count;
3084 
                            op_ctrl    <= latch_op;
3085 
                                 pre_ctrl   <= latch_pre;
3086 
                            -- idle the effective address
3087 
             left_ctrl  <= ea_left;
3088 
             right_ctrl <= one_right;
3089 
             alu_ctrl   <= alu_nop;
3090 
             cc_ctrl    <= latch_cc;
3091 
             ea_ctrl    <= latch_ea;
3092 
                            -- read the low byte of the 16 bit data
3093 
                                 md_ctrl    <= fetch_next_md;
3094 
             addr_ctrl  <= read_ad;
3095 
             dout_ctrl  <= md_lo_dout;
3096 4 dilbert57 
                            next_state <= fetch_state;
3097 2 dilbert57 
 
3098 
                          --
3099 
                          -- exchange registers
3100 
                          -- at this point md holds accd
3101 
                          -- transfer X or Y to accd
3102 
                          --
3103 4 dilbert57 
                          when exchange_state => -- md holds accd
3104 2 dilbert57 
             -- default
3105 
             ix_ctrl    <= latch_ix;
3106 
             iy_ctrl    <= latch_iy;
3107 
             sp_ctrl    <= latch_sp;
3108 
             pc_ctrl    <= latch_pc;
3109 
             iv_ctrl    <= latch_iv;
3110 
                                 count_ctrl <= reset_count;
3111 
                            op_ctrl    <= latch_op;
3112 
                                 pre_ctrl   <= latch_pre;
3113 
             ea_ctrl    <= latch_ea;
3114 
                                 md_ctrl    <= latch_md;
3115 
                            -- transfer x or y to accd
3116 
                            if pre_byte = "00011000" then
3117 
                                        left_ctrl  <= iy_left;
3118 
                                 else
3119 
               left_ctrl  <= ix_left;
3120 
                            end if;
3121 
             right_ctrl <= zero_right;
3122 
             alu_ctrl   <= alu_st16;
3123 
             cc_ctrl    <= latch_cc;
3124 
             acca_ctrl  <= load_hi_acca;
3125 
             accb_ctrl  <= load_accb;
3126 
                            -- idle the address bus
3127 
             addr_ctrl  <= idle_ad;
3128 
             dout_ctrl  <= md_lo_dout;
3129 4 dilbert57 
                            next_state <= fetch_state;
3130 2 dilbert57 
 
3131 
                           when bitmask_state => -- fetch bit mask from next op
3132 
                 -- default
3133 
                 acca_ctrl  <= latch_acca;
3134 
                 accb_ctrl  <= latch_accb;
3135 
                 ix_ctrl    <= latch_ix;
3136 
                 iy_ctrl    <= latch_iy;
3137 
                 sp_ctrl    <= latch_sp;
3138 
                 ea_ctrl    <= latch_ea;
3139 
                                     md_ctrl    <= latch_md;
3140 
                 iv_ctrl    <= latch_iv;
3141 
                                     count_ctrl <= reset_count;
3142 
                                op_ctrl    <= latch_op;
3143 
                                          -- addvance the pc
3144 
                 left_ctrl  <= pc_left;
3145 
                 right_ctrl <= one_right;
3146 
                 alu_ctrl   <= alu_add16;
3147 
                 cc_ctrl    <= latch_cc;
3148 
                 pc_ctrl    <= load_pc;
3149 
                                          -- read the bit mask into the pre byte register
3150 
                                     pre_ctrl   <= fetch_pre;
3151 
                 addr_ctrl  <= fetch_ad;
3152 
                 dout_ctrl  <= md_lo_dout;
3153 
                                          case op_code is
3154 
                                          when "00010010" | "00011110" => -- brset
3155 
                                            next_state <= brset_state;
3156 
                                          when "00010011" | "00011111" => -- brclr
3157 
                                            next_state <= brclr_state;
3158 
                                          when "00010100" | "00011100" => -- bset
3159 4 dilbert57 
                                                 next_state <= execute_state;
3160 2 dilbert57 
                                          when "00010101" | "00011101" => -- bclr
3161 4 dilbert57 
                                                 next_state <= execute_state;
3162 2 dilbert57 
                                          when others =>
3163 
                                            next_state <= fetch_state;
3164 
                                          end case;
3165 
 
3166 
                           when brclr_state => -- fetch the branch offset
3167 
                 -- default
3168 
                 acca_ctrl  <= latch_acca;
3169 
                 accb_ctrl  <= latch_accb;
3170 
                 ix_ctrl    <= latch_ix;
3171 
                 iy_ctrl    <= latch_iy;
3172 
                 sp_ctrl    <= latch_sp;
3173 
                                     md_ctrl    <= latch_md;
3174 
                 iv_ctrl    <= latch_iv;
3175 
                                     count_ctrl <= reset_count;
3176 
                                op_ctrl    <= latch_op;
3177 
                                     pre_ctrl   <= latch_pre;
3178 
                                          -- advance the pc
3179 
                 left_ctrl  <= pc_left;
3180 
                 right_ctrl <= one_right;
3181 
                 alu_ctrl   <= alu_add16;
3182 
                 cc_ctrl    <= latch_cc;
3183 
                 pc_ctrl    <= load_pc;
3184 
                                          -- fetch the branch offset
3185 
                 addr_ctrl  <= fetch_ad;
3186 
                 ea_ctrl    <= fetch_first_ea;
3187 
                 dout_ctrl  <= md_lo_dout;
3188 
                                          if (pre_byte and md(7 downto 0) ) = "00000000" then
3189 
                                                   next_state <= branch_state;
3190 
                                          else
3191 
                                                   next_state <= fetch_state;
3192 
                                          end if;
3193 
 
3194 
                           when brset_state => -- fetch the branch offset
3195 
                 -- default
3196 
                 acca_ctrl  <= latch_acca;
3197 
                 accb_ctrl  <= latch_accb;
3198 
                 ix_ctrl    <= latch_ix;
3199 
                 iy_ctrl    <= latch_iy;
3200 
                 sp_ctrl    <= latch_sp;
3201 
                                     md_ctrl    <= latch_md;
3202 
                 iv_ctrl    <= latch_iv;
3203 
                                     count_ctrl <= reset_count;
3204 
                                op_ctrl    <= latch_op;
3205 
                                     pre_ctrl   <= latch_pre;
3206 
                                          -- advance the pc
3207 
                 left_ctrl  <= pc_left;
3208 
                 right_ctrl <= one_right;
3209 
                 alu_ctrl   <= alu_add16;
3210 
                 cc_ctrl    <= latch_cc;
3211 
                 pc_ctrl    <= load_pc;
3212 
                                          -- fetch the branch offset
3213 
                 addr_ctrl  <= fetch_ad;
3214 
                 ea_ctrl    <= fetch_first_ea;
3215 
                 dout_ctrl  <= md_lo_dout;
3216 
                                          if (pre_byte and md(7 downto 0) ) = "00000000" then
3217 
                                                   next_state <= fetch_state;
3218 
                                          else
3219 
                                                   next_state <= branch_state;
3220 
                                          end if;
3221 
 
3222 
 
3223 
                                when jmp_state =>
3224 
                 acca_ctrl  <= latch_acca;
3225 
                 accb_ctrl  <= latch_accb;
3226 
                 ix_ctrl    <= latch_ix;
3227 
                 iy_ctrl    <= latch_iy;
3228 
                 sp_ctrl    <= latch_sp;
3229 
                 md_ctrl    <= latch_md;
3230 
                 iv_ctrl    <= latch_iv;
3231 
                                     count_ctrl <= reset_count;
3232 
                                op_ctrl    <= latch_op;
3233 
                                     pre_ctrl   <= latch_pre;
3234 
                 ea_ctrl    <= latch_ea;
3235 
                                          -- load PC with effective address
3236 
                 left_ctrl  <= pc_left;
3237 
                                          right_ctrl <= ea_right;
3238 
                                     alu_ctrl   <= alu_ld16;
3239 
                 cc_ctrl    <= latch_cc;
3240 
                                          pc_ctrl    <= load_pc;
3241 
                                          -- idle the bus
3242 
                 addr_ctrl  <= idle_ad;
3243 
                 dout_ctrl  <= md_lo_dout;
3244 
                 next_state <= fetch_state;
3245 
 
3246 
                                when jsr_state => -- JSR
3247 
                 acca_ctrl  <= latch_acca;
3248 
                 accb_ctrl  <= latch_accb;
3249 
                 ix_ctrl    <= latch_ix;
3250 
                 iy_ctrl    <= latch_iy;
3251 
                 sp_ctrl    <= latch_sp;
3252 
                 pc_ctrl    <= latch_pc;
3253 
                 md_ctrl    <= latch_md;
3254 
                 iv_ctrl    <= latch_iv;
3255 
                                     count_ctrl <= reset_count;
3256 
                                op_ctrl    <= latch_op;
3257 
                                     pre_ctrl   <= latch_pre;
3258 
                 ea_ctrl    <= latch_ea;
3259 
                 -- decrement sp
3260 
                 left_ctrl  <= sp_left;
3261 
                 right_ctrl <= one_right;
3262 
                 alu_ctrl   <= alu_sub16;
3263 
                 cc_ctrl    <= latch_cc;
3264 
                 sp_ctrl    <= load_sp;
3265 
                                          -- write pc low
3266 
                 addr_ctrl  <= push_ad;
3267 
                                          dout_ctrl  <= pc_lo_dout;
3268 
                 next_state <= jsr1_state;
3269 
 
3270 
                                when jsr1_state => -- JSR
3271 
                 acca_ctrl  <= latch_acca;
3272 
                 accb_ctrl  <= latch_accb;
3273 
                 ix_ctrl    <= latch_ix;
3274 
                 iy_ctrl    <= latch_iy;
3275 
                 pc_ctrl    <= latch_pc;
3276 
                 md_ctrl    <= latch_md;
3277 
                 iv_ctrl    <= latch_iv;
3278 
                                     count_ctrl <= reset_count;
3279 
                                op_ctrl    <= latch_op;
3280 
                                     pre_ctrl   <= latch_pre;
3281 
                 ea_ctrl    <= latch_ea;
3282 
                 -- decrement sp
3283 
                 left_ctrl  <= sp_left;
3284 
                 right_ctrl <= one_right;
3285 
                 alu_ctrl   <= alu_sub16;
3286 
                 cc_ctrl    <= latch_cc;
3287 
                 sp_ctrl    <= load_sp;
3288 
                                          -- write pc hi
3289 
                 addr_ctrl  <= push_ad;
3290 
                                          dout_ctrl  <= pc_hi_dout;
3291 
                 next_state <= jmp_state;
3292 
 
3293 
                                when branch_state => -- Bcc
3294 
                                     -- default registers
3295 
                 acca_ctrl  <= latch_acca;
3296 
                 accb_ctrl  <= latch_accb;
3297 
                 ix_ctrl    <= latch_ix;
3298 
                 iy_ctrl    <= latch_iy;
3299 
                 sp_ctrl    <= latch_sp;
3300 
                 md_ctrl    <= latch_md;
3301 
                 iv_ctrl    <= latch_iv;
3302 
                                     count_ctrl <= reset_count;
3303 
                                op_ctrl    <= latch_op;
3304 
                                     pre_ctrl   <= latch_pre;
3305 
                 ea_ctrl    <= latch_ea;
3306 
                                          -- calculate signed branch
3307 
                                          left_ctrl  <= pc_left;
3308 
                                          right_ctrl <= sexea_right; -- right must be sign extended effective address
3309 
                                     alu_ctrl   <= alu_add16;
3310 
                 cc_ctrl    <= latch_cc;
3311 
                                          pc_ctrl    <= load_pc;
3312 
                                          -- idle the bus
3313 
                 addr_ctrl  <= idle_ad;
3314 
                 dout_ctrl  <= md_lo_dout;
3315 
                 next_state <= fetch_state;
3316 
 
3317 
                                when bsr_state => -- BSR
3318 
                                     -- default
3319 
                 acca_ctrl  <= latch_acca;
3320 
                 accb_ctrl  <= latch_accb;
3321 
                 ix_ctrl    <= latch_ix;
3322 
                 iy_ctrl    <= latch_iy;
3323 
                 pc_ctrl    <= latch_pc;
3324 
                 md_ctrl    <= latch_md;
3325 
                 iv_ctrl    <= latch_iv;
3326 
                                     count_ctrl <= reset_count;
3327 
                                op_ctrl    <= latch_op;
3328 
                                     pre_ctrl   <= latch_pre;
3329 
                 ea_ctrl    <= latch_ea;
3330 
                 -- decrement sp
3331 
                 left_ctrl  <= sp_left;
3332 
                 right_ctrl <= one_right;
3333 
                 alu_ctrl   <= alu_sub16;
3334 
                 cc_ctrl    <= latch_cc;
3335 
                 sp_ctrl    <= load_sp;
3336 
                                          -- write pc low
3337 
                 addr_ctrl  <= push_ad;
3338 
                                          dout_ctrl  <= pc_lo_dout;
3339 
                 next_state <= bsr1_state;
3340 
 
3341 
                                when bsr1_state => -- BSR
3342 
                                     -- default registers
3343 
                 acca_ctrl  <= latch_acca;
3344 
                 accb_ctrl  <= latch_accb;
3345 
                 ix_ctrl    <= latch_ix;
3346 
                 iy_ctrl    <= latch_iy;
3347 
                 pc_ctrl    <= latch_pc;
3348 
                 md_ctrl    <= latch_md;
3349 
                 iv_ctrl    <= latch_iv;
3350 
                                     count_ctrl <= reset_count;
3351 
                                op_ctrl    <= latch_op;
3352 
                                     pre_ctrl   <= latch_pre;
3353 
                 ea_ctrl    <= latch_ea;
3354 
                 -- decrement sp
3355 
                 left_ctrl  <= sp_left;
3356 
                 right_ctrl <= one_right;
3357 
                 alu_ctrl   <= alu_sub16;
3358 
                 cc_ctrl    <= latch_cc;
3359 
                 sp_ctrl    <= load_sp;
3360 
                                          -- write pc hi
3361 
                 addr_ctrl  <= push_ad;
3362 
                                          dout_ctrl  <= pc_hi_dout;
3363 
                 next_state <= branch_state;
3364 
 
3365 
                                 when rts_hi_state => -- RTS
3366 
                                     -- default
3367 
                 acca_ctrl  <= latch_acca;
3368 
                 accb_ctrl  <= latch_accb;
3369 
                 ix_ctrl    <= latch_ix;
3370 
                 iy_ctrl    <= latch_iy;
3371 
                 pc_ctrl    <= latch_pc;
3372 
                 md_ctrl    <= latch_md;
3373 
                 iv_ctrl    <= latch_iv;
3374 
                                     count_ctrl <= reset_count;
3375 
                                op_ctrl    <= latch_op;
3376 
                                     pre_ctrl   <= latch_pre;
3377 
                 ea_ctrl    <= latch_ea;
3378 
                                          -- increment the sp
3379 
                 left_ctrl  <= sp_left;
3380 
                 right_ctrl <= one_right;
3381 
                 alu_ctrl   <= alu_add16;
3382 
                 cc_ctrl    <= latch_cc;
3383 
                 sp_ctrl    <= load_sp;
3384 
                 -- read pc hi
3385 
                                          pc_ctrl    <= pull_hi_pc;
3386 
                 addr_ctrl  <= pull_ad;
3387 
                 dout_ctrl  <= pc_hi_dout;
3388 
                 next_state <= rts_lo_state;
3389 
 
3390 
                                when rts_lo_state => -- RTS1
3391 
                                     -- default
3392 
                 acca_ctrl  <= latch_acca;
3393 
                 accb_ctrl  <= latch_accb;
3394 
                 ix_ctrl    <= latch_ix;
3395 
                 iy_ctrl    <= latch_iy;
3396 
                 sp_ctrl    <= latch_sp;
3397 
                 md_ctrl    <= latch_md;
3398 
                 iv_ctrl    <= latch_iv;
3399 
                                     count_ctrl <= reset_count;
3400 
                                op_ctrl    <= latch_op;
3401 
                                     pre_ctrl   <= latch_pre;
3402 
                 ea_ctrl    <= latch_ea;
3403 
                                          -- idle the ALU
3404 
                 left_ctrl  <= acca_left;
3405 
                 right_ctrl <= zero_right;
3406 
                 alu_ctrl   <= alu_nop;
3407 
                 cc_ctrl    <= latch_cc;
3408 
                                          -- read pc low
3409 
                                          pc_ctrl    <= pull_lo_pc;
3410 
                 addr_ctrl  <= pull_ad;
3411 
                 dout_ctrl  <= pc_lo_dout;
3412 
                 next_state <= fetch_state;
3413 
 
3414 
                                 when mul_state =>
3415 
                                     -- default
3416 
                 acca_ctrl  <= latch_acca;
3417 
                 accb_ctrl  <= latch_accb;
3418 
                 ix_ctrl    <= latch_ix;
3419 
                 iy_ctrl    <= latch_iy;
3420 
                 sp_ctrl    <= latch_sp;
3421 
                 pc_ctrl    <= latch_pc;
3422 
                 iv_ctrl    <= latch_iv;
3423 
                                     count_ctrl <= reset_count;
3424 
                                op_ctrl    <= latch_op;
3425 
                                     pre_ctrl   <= latch_pre;
3426 
                 ea_ctrl    <= latch_ea;
3427 
                                          -- move acca to md
3428 
                 left_ctrl  <= acca_left;
3429 
                 right_ctrl <= zero_right;
3430 
                 alu_ctrl   <= alu_st16;
3431 
                 cc_ctrl    <= latch_cc;
3432 
                 md_ctrl    <= load_md;
3433 
                                          -- idle bus
3434 
                 addr_ctrl  <= idle_ad;
3435 
                 dout_ctrl  <= md_lo_dout;
3436 
                                     next_state <= mulea_state;
3437 
 
3438 
                                 when mulea_state =>
3439 
                                     -- default
3440 
                 acca_ctrl  <= latch_acca;
3441 
                 accb_ctrl  <= latch_accb;
3442 
                 ix_ctrl    <= latch_ix;
3443 
                 iy_ctrl    <= latch_iy;
3444 
                 sp_ctrl    <= latch_sp;
3445 
                 pc_ctrl    <= latch_pc;
3446 
                 iv_ctrl    <= latch_iv;
3447 
                                     count_ctrl <= reset_count;
3448 
                                op_ctrl    <= latch_op;
3449 
                                     pre_ctrl   <= latch_pre;
3450 
                 md_ctrl    <= latch_md;
3451 
                                          -- move accb to ea
3452 
                 left_ctrl  <= accb_left;
3453 
                 right_ctrl <= zero_right;
3454 
                 alu_ctrl   <= alu_st16;
3455 
                 cc_ctrl    <= latch_cc;
3456 
                 ea_ctrl    <= load_ea;
3457 
                                          -- idle bus
3458 
                 addr_ctrl  <= idle_ad;
3459 
                 dout_ctrl  <= md_lo_dout;
3460 
                                     next_state <= muld_state;
3461 
 
3462 
                                 when muld_state =>
3463 
                                     -- default
3464 
                 ix_ctrl    <= latch_ix;
3465 
                 iy_ctrl    <= latch_iy;
3466 
                 sp_ctrl    <= latch_sp;
3467 
                 pc_ctrl    <= latch_pc;
3468 
                 iv_ctrl    <= latch_iv;
3469 
                                     count_ctrl <= reset_count;
3470 
                                op_ctrl    <= latch_op;
3471 
                                     pre_ctrl   <= latch_pre;
3472 
                 ea_ctrl    <= latch_ea;
3473 
                 md_ctrl    <= latch_md;
3474 
                                          -- clear accd
3475 
                 left_ctrl  <= acca_left;
3476 
                 right_ctrl <= zero_right;
3477 
                 alu_ctrl   <= alu_ld8;
3478 
                 cc_ctrl    <= latch_cc;
3479 
                 acca_ctrl  <= load_hi_acca;
3480 
                 accb_ctrl  <= load_accb;
3481 
                                          -- idle bus
3482 
                 addr_ctrl  <= idle_ad;
3483 
                 dout_ctrl  <= md_lo_dout;
3484 
                                     next_state <= mul0_state;
3485 
 
3486 
                                 when mul0_state =>
3487 
                                     -- default
3488 
                 ix_ctrl    <= latch_ix;
3489 
                 iy_ctrl    <= latch_iy;
3490 
                 sp_ctrl    <= latch_sp;
3491 
                 pc_ctrl    <= latch_pc;
3492 
                 iv_ctrl    <= latch_iv;
3493 
                                     count_ctrl <= inc_count;
3494 
                                op_ctrl    <= latch_op;
3495 
                                     pre_ctrl   <= latch_pre;
3496 
                 ea_ctrl    <= latch_ea;
3497 
                                          -- if ea bit(count) set, add accd to md
3498 
                 left_ctrl  <= accd_left;
3499 
                 right_ctrl <= md_right;
3500 
                 alu_ctrl   <= alu_add16;
3501 
                                          if ea_bit = '1' then
3502 
                   cc_ctrl    <= load_cc;
3503 
                   acca_ctrl  <= load_hi_acca;
3504 
                   accb_ctrl  <= load_accb;
3505 
                                          else
3506 
                   cc_ctrl    <= latch_cc;
3507 
                   acca_ctrl  <= latch_acca;
3508 
                   accb_ctrl  <= latch_accb;
3509 
                                          end if;
3510 
                 md_ctrl    <= shiftl_md;
3511 
                                          -- idle bus
3512 
                 addr_ctrl  <= idle_ad;
3513 
                 dout_ctrl  <= md_lo_dout;
3514 
                                          if count = "0111" then
3515 
                                            next_state <= fetch_state;
3516 
                                          else
3517 
                                       next_state <= mul0_state;
3518 
                                          end if;
3519 
 
3520 
                                 --
3521 
                                 -- Integer division
3522 
                                 -- ACCD = numerator
3523 
                                 -- EA = denominator
3524 
                                 -- IX = quotient
3525 
                                 --
3526 
                                 -- For integer divide, re-arrange registers
3527 
                                 -- IX = ACCD = dividend low word
3528 
                                 -- ACCD = 0 = dividend
3529 
                                 --
3530 
                                 when idiv_state =>
3531 
                 iy_ctrl    <= latch_iy;
3532 
                 sp_ctrl    <= latch_sp;
3533 
                 pc_ctrl    <= latch_pc;
3534 
                 iv_ctrl    <= latch_iv;
3535 
                                     count_ctrl <= reset_count;
3536 
                                op_ctrl    <= latch_op;
3537 
                                     pre_ctrl   <= latch_pre;
3538 
                 ea_ctrl    <= latch_ea;
3539 
                 md_ctrl    <= latch_md;
3540 
                                          -- transfer ACCD to IX
3541 
                 left_ctrl  <= accd_left;
3542 
                 right_ctrl <= zero_right;
3543 
                 alu_ctrl   <= alu_st16;
3544 
                 cc_ctrl    <= load_cc;
3545 
                 ix_ctrl    <= load_ix;  --- quotient / dividend
3546 
                 acca_ctrl  <= reset_acca;
3547 
                 accb_ctrl  <= reset_accb;
3548 
                                          -- idle bus
3549 
                 addr_ctrl  <= idle_ad;
3550 
                 dout_ctrl  <= md_lo_dout;
3551 
                                     next_state <= div1_state;
3552 
 
3553 
 
3554 
                                 --
3555 
                                 -- Common integer divide
3556 
                                 -- ACCD = Dividend high word
3557 
                                 -- IX = Dividend low word / Quotient
3558 
                                 -- EA = Divisor
3559 
                                 -- MD = Temp for subtraction
3560 
                                 --
3561 
                                 -- Test for divide
3562 
                                 -- MD = ACCD - EA
3563 
                                 --
3564 
                                 when div1_state =>
3565 
                                     -- default
3566 
                 acca_ctrl  <= latch_acca;
3567 
                 accb_ctrl  <= latch_accb;
3568 
                 ix_ctrl    <= latch_ix;
3569 
                 iy_ctrl    <= latch_iy;
3570 
                 sp_ctrl    <= latch_sp;
3571 
                 pc_ctrl    <= latch_pc;
3572 
                 iv_ctrl    <= latch_iv;
3573 
                                     count_ctrl <= latch_count;
3574 
                                op_ctrl    <= latch_op;
3575 
                                     pre_ctrl   <= latch_pre;
3576 
                 ea_ctrl    <= latch_ea;
3577 
                                          -- subtract denominator from numerator
3578 
                 left_ctrl  <= accd_left;
3579 
                 right_ctrl <= ea_right;
3580 
                 alu_ctrl   <= alu_sub16;
3581 
                 cc_ctrl    <= load_cc;
3582 
                 md_ctrl    <= load_md; -- md = temporary result
3583 
                                          -- idle bus
3584 
                 addr_ctrl  <= idle_ad;
3585 
                 dout_ctrl  <= md_lo_dout;
3586 
                                     next_state <= div2_state;
3587 
 
3588 
                                 --
3589 
                                 -- shift carry into quotient
3590 
                                 -- IX = IX << 1 + Carry
3591 
                                 -- next state dependant on carry from previous state
3592 
                                 --
3593 
                                 when div2_state =>
3594 
                                     -- default
3595 
                 acca_ctrl  <= latch_acca;
3596 
                 accb_ctrl  <= latch_accb;
3597 
                 iy_ctrl    <= latch_iy;
3598 
                 sp_ctrl    <= latch_sp;
3599 
                 pc_ctrl    <= latch_pc;
3600 
                 iv_ctrl    <= latch_iv;
3601 
                                     count_ctrl <= inc_count;
3602 
                                op_ctrl    <= latch_op;
3603 
                                     pre_ctrl   <= latch_pre;
3604 
                 ea_ctrl    <= latch_ea;
3605 
                 md_ctrl    <= load_md;
3606 
                                          -- rotate carry into quotient
3607 
                 left_ctrl  <= ix_left;
3608 
                 right_ctrl <= zero_right;
3609 
                 alu_ctrl   <= alu_rol16;
3610 
                 cc_ctrl    <= load_cc;
3611 
                 ix_ctrl    <= load_ix;
3612 
                                          -- idle bus
3613 
                 addr_ctrl  <= idle_ad;
3614 
                 dout_ctrl  <= md_lo_dout;
3615 
                                          if cc(CBIT) = '1' then
3616 
                                       next_state <= div3_state;
3617 
                                          else
3618 
                                            next_state <= div4_state;
3619 
                                          end if;
3620 
 
3621 
                                 --
3622 
                                 -- hear if Carry Set from subtract
3623 
                                 -- ACCD = ACCD << 1 + Carry
3624 
                                 --
3625 
                                 when div3_state =>
3626 
                                     -- default
3627 
                 ix_ctrl    <= latch_ix;
3628 
                 iy_ctrl    <= latch_iy;
3629 
                 sp_ctrl    <= latch_sp;
3630 
                 pc_ctrl    <= latch_pc;
3631 
                 iv_ctrl    <= latch_iv;
3632 
                                     count_ctrl <= latch_count;
3633 
                                op_ctrl    <= latch_op;
3634 
                                     pre_ctrl   <= latch_pre;
3635 
                 ea_ctrl    <= latch_ea;
3636 
                 md_ctrl    <= latch_md;
3637 
                                          -- shift numerator left
3638 
                 left_ctrl  <= accd_left;
3639 
                 right_ctrl <= zero_right;
3640 
                 alu_ctrl   <= alu_rol16;
3641 
                 cc_ctrl    <= load_cc;
3642 
                 acca_ctrl  <= load_hi_acca;
3643 
                 accb_ctrl  <= load_accb;
3644 
                                          -- idle bus
3645 
                 addr_ctrl  <= idle_ad;
3646 
                 dout_ctrl  <= md_lo_dout;
3647 
                                          if count = "10000" then
3648 
                                            next_state <= div5_state;
3649 
                                          else
3650 
                                       next_state <= div1_state;
3651 
                                          end if;
3652 
                                 --
3653 
                                 -- hear if Carry Clear from subtract
3654 
                                 -- ACCD = MD << 1 + Carry
3655 
                                 --
3656 
                                 when div4_state =>
3657 
                 ix_ctrl    <= latch_ix;
3658 
                 iy_ctrl    <= latch_iy;
3659 
                 sp_ctrl    <= latch_sp;
3660 
                 pc_ctrl    <= latch_pc;
3661 
                 iv_ctrl    <= latch_iv;
3662 
                                     count_ctrl <= latch_count;
3663 
                                op_ctrl    <= latch_op;
3664 
                                     pre_ctrl   <= latch_pre;
3665 
                 ea_ctrl    <= latch_ea;
3666 
                 md_ctrl    <= latch_md;
3667 
                                          -- numerator = Subtraction rotated left
3668 
                 left_ctrl  <= md_left;
3669 
                 right_ctrl <= zero_right;
3670 
                 alu_ctrl   <= alu_rol16;
3671 
                 cc_ctrl    <= load_cc;
3672 
                 acca_ctrl  <= load_hi_acca;
3673 
                 accb_ctrl  <= load_accb;
3674 
                                          -- idle bus
3675 
                 addr_ctrl  <= idle_ad;
3676 
                 dout_ctrl  <= md_lo_dout;
3677 
                                          if count = "10000" then
3678 
                                            next_state <= div5_state;
3679 
                                          else
3680 
                                       next_state <= div1_state;
3681 
                                          end if;
3682 
 
3683 
                                 --
3684 
                                 -- invert quotient in IX
3685 
                                 -- IX = COM( IX )
3686 
                                 --
3687 
                                 when div5_state =>
3688 
                                     -- default
3689 
                 acca_ctrl  <= latch_acca;
3690 
                 accb_ctrl  <= latch_accb;
3691 
                 iy_ctrl    <= latch_iy;
3692 
                 sp_ctrl    <= latch_sp;
3693 
                 pc_ctrl    <= latch_pc;
3694 
                 iv_ctrl    <= latch_iv;
3695 
                                     count_ctrl <= latch_count;
3696 
                                op_ctrl    <= latch_op;
3697 
                                     pre_ctrl   <= latch_pre;
3698 
                 ea_ctrl    <= latch_ea;
3699 
                 md_ctrl    <= latch_md;
3700 
                                          -- complement quotient
3701 
                 left_ctrl  <= ix_left;
3702 
                 right_ctrl <= ea_right;
3703 
                 alu_ctrl   <= alu_com;
3704 
                 cc_ctrl    <= load_cc;
3705 
                 ix_ctrl    <= load_ix;
3706 
                                          -- idle bus
3707 
                 addr_ctrl  <= idle_ad;
3708 
                 dout_ctrl  <= md_lo_dout;
3709 
                                     next_state <= fetch_state;
3710 
 
3711 
                                 --
3712 
                                 -- Spin the Program counter
3713 
                                 --
3714 
                                 when spin_state =>
3715 
                                     -- default
3716 
                 acca_ctrl  <= latch_acca;
3717 
                 accb_ctrl  <= latch_accb;
3718 
                 ix_ctrl    <= latch_ix;
3719 
                 iy_ctrl    <= latch_iy;
3720 
                 sp_ctrl    <= latch_sp;
3721 
                 iv_ctrl    <= latch_iv;
3722 
                                     count_ctrl <= latch_count;
3723 
                                op_ctrl    <= latch_op;
3724 
                                     pre_ctrl   <= latch_pre;
3725 
                 ea_ctrl    <= latch_ea;
3726 
                 md_ctrl    <= latch_md;
3727 
                                          -- complement quotient
3728 
                 left_ctrl  <= pc_left;
3729 
                 right_ctrl <= one_right;
3730 
                 alu_ctrl   <= alu_add16;
3731 
                 pc_ctrl    <= load_pc;
3732 
                 cc_ctrl    <= latch_cc;
3733 
                                          -- idle bus
3734 
                 addr_ctrl  <= fetch_ad;
3735 
                 dout_ctrl  <= md_lo_dout;
3736 
                                     next_state <= spin_state;
3737 
 
3738 4 dilbert57 
             --
3739 
                                 -- Execute cycle is performed by
3740 
                                 -- single operand indexed and extended instructions
3741 
                                 -- and bit operators.
3742 
                                 --
3743 2 dilbert57 
                            when execute_state => -- execute
3744 
                                   -- default
3745 
                              op_ctrl    <= latch_op;
3746 
                                   pre_ctrl   <= latch_pre;
3747 
                                   count_ctrl <= reset_count;
3748 4 dilbert57 
                                        acca_ctrl   <= latch_acca;
3749 
               accb_ctrl   <= latch_accb;
3750 
               ix_ctrl     <= latch_ix;
3751 
               iy_ctrl     <= latch_iy;
3752 
               sp_ctrl     <= latch_sp;
3753 
               pc_ctrl     <= latch_pc;
3754 
               iv_ctrl     <= latch_iv;
3755 
               ea_ctrl     <= latch_ea;
3756 
                                          -- idle the bus
3757 
               addr_ctrl   <= idle_ad;
3758 
               dout_ctrl   <= md_lo_dout;
3759 2 dilbert57 
                              case op_code(7 downto 4) is
3760 
                                        when "0001" => -- bit operators come here
3761 
                                          case op_code(3 downto 0) is
3762 4 dilbert57 
                                          when "0100" | "1100" => -- bset
3763 2 dilbert57 
                                              -- OR bit
3764 
                     left_ctrl  <= md_left;
3765 
                                              right_ctrl <= pre_right;
3766 
                                              alu_ctrl   <= alu_bset;
3767 
                                              cc_ctrl    <= load_cc;
3768 
                     md_ctrl    <= load_md;
3769 
                                         next_state <= write8_state;
3770 4 dilbert57 
                                          when "0101" | "1101" => -- bclr
3771 2 dilbert57 
                                              -- AND bit
3772 
                     left_ctrl  <= md_left;
3773 
                                              right_ctrl <= pre_right;
3774 
                                              alu_ctrl   <= alu_bclr;
3775 
                                              cc_ctrl    <= load_cc;
3776 
                     md_ctrl    <= load_md;
3777 
                                         next_state <= write8_state;
3778 4 dilbert57 
                                          when others =>
3779 2 dilbert57 
                                              -- idle ALU
3780 
                     left_ctrl  <= md_left;
3781 
                                              right_ctrl <= pre_right;
3782 
                                              alu_ctrl   <= alu_nop;
3783 
                                              cc_ctrl    <= latch_cc;
3784 
                     md_ctrl    <= latch_md;
3785 
                                         next_state <= fetch_state;
3786 
                                          end case;
3787 
 
3788 
                    when "0110" | -- indexed single op
3789 
                         "0111" => -- extended single op
3790 
                      case op_code(3 downto 0) is
3791 
                           when "0000" => -- neg
3792 
                   left_ctrl  <= md_left;
3793 
                                            right_ctrl <= zero_right;
3794 
                                            alu_ctrl   <= alu_neg;
3795 
                                            cc_ctrl    <= load_cc;
3796 
                                       md_ctrl    <= load_md;
3797 
                                       next_state <= write8_state;
3798 
                      when "0011" => -- com
3799 
                   left_ctrl  <= md_left;
3800 
                             right_ctrl <= zero_right;
3801 
                                            alu_ctrl   <= alu_com;
3802 
                                            cc_ctrl    <= load_cc;
3803 
                                       md_ctrl    <= load_md;
3804 
                                       next_state <= write8_state;
3805 
                           when "0100" => -- lsr
3806 
                   left_ctrl  <= md_left;
3807 
                                                 right_ctrl <= zero_right;
3808 
                                            alu_ctrl   <= alu_lsr8;
3809 
                                            cc_ctrl    <= load_cc;
3810 
                                       md_ctrl    <= load_md;
3811 
                                       next_state <= write8_state;
3812 
                           when "0110" => -- ror
3813 
                   left_ctrl  <= md_left;
3814 
                                                 right_ctrl <= zero_right;
3815 
                                            alu_ctrl   <= alu_ror8;
3816 
                                            cc_ctrl    <= load_cc;
3817 
                                       md_ctrl    <= load_md;
3818 
                                       next_state <= write8_state;
3819 
                           when "0111" => -- asr
3820 
                   left_ctrl  <= md_left;
3821 
                                                 right_ctrl <= zero_right;
3822 
                                            alu_ctrl   <= alu_asr8;
3823 
                                            cc_ctrl    <= load_cc;
3824 
                                       md_ctrl    <= load_md;
3825 
                                       next_state <= write8_state;
3826 
                           when "1000" => -- asl
3827 
                   left_ctrl  <= md_left;
3828 
                                                 right_ctrl <= zero_right;
3829 
                                            alu_ctrl   <= alu_asl8;
3830 
                                            cc_ctrl    <= load_cc;
3831 
                                       md_ctrl    <= load_md;
3832 
                                       next_state <= write8_state;
3833 
                           when "1001" => -- rol
3834 
                   left_ctrl  <= md_left;
3835 
                                                 right_ctrl <= zero_right;
3836 
                                            alu_ctrl   <= alu_rol8;
3837 
                                            cc_ctrl    <= load_cc;
3838 
                                       md_ctrl    <= load_md;
3839 
                                       next_state <= write8_state;
3840 
                           when "1010" => -- dec
3841 
                   left_ctrl  <= md_left;
3842 
                             right_ctrl <= one_right;
3843 
                                            alu_ctrl   <= alu_dec;
3844 
                                            cc_ctrl    <= load_cc;
3845 
                                       md_ctrl    <= load_md;
3846 
                                       next_state <= write8_state;
3847 
                           when "1011" => -- undefined
3848 
                   left_ctrl  <= md_left;
3849 
                                                 right_ctrl <= zero_right;
3850 
                                            alu_ctrl   <= alu_nop;
3851 
                                            cc_ctrl    <= latch_cc;
3852 
                                       md_ctrl    <= latch_md;
3853 
                                       next_state <= fetch_state;
3854 
                           when "1100" => -- inc
3855 
                   left_ctrl  <= md_left;
3856 
                             right_ctrl <= one_right;
3857 
                                            alu_ctrl   <= alu_inc;
3858 
                                            cc_ctrl    <= load_cc;
3859 
                                       md_ctrl    <= load_md;
3860 
                                       next_state <= write8_state;
3861 
                           when "1101" => -- tst
3862 
                   left_ctrl  <= md_left;
3863 
                             right_ctrl <= zero_right;
3864 
                                            alu_ctrl   <= alu_st8;
3865 
                                            cc_ctrl    <= load_cc;
3866 
                                       md_ctrl    <= latch_md;
3867 
                                       next_state <= fetch_state;
3868 
                           when "1110" => -- jmp
3869 
                   left_ctrl  <= md_left;
3870 
                                                 right_ctrl <= zero_right;
3871 
                                            alu_ctrl   <= alu_nop;
3872 
                                            cc_ctrl    <= latch_cc;
3873 
                                       md_ctrl    <= latch_md;
3874 
                                       next_state <= fetch_state;
3875 
                           when "1111" => -- clr
3876 
                   left_ctrl  <= md_left;
3877 
                                                 right_ctrl <= zero_right;
3878 4 dilbert57 
                                            alu_ctrl   <= alu_clr;
3879 2 dilbert57 
                                            cc_ctrl    <= load_cc;
3880 
                                       md_ctrl    <= load_md;
3881 
                                       next_state <= write8_state;
3882 
                           when others =>
3883 
                   left_ctrl  <= md_left;
3884 
                                                 right_ctrl <= zero_right;
3885 
                                            alu_ctrl   <= alu_nop;
3886 
                                            cc_ctrl    <= latch_cc;
3887 
                                       md_ctrl    <= latch_md;
3888 
                                       next_state <= fetch_state;
3889 
                           end case;
3890 4 dilbert57 
 
3891 2 dilbert57 
                    when others =>
3892 
                                          left_ctrl   <= accd_left;
3893 
                                          right_ctrl  <= md_right;
3894 
                                          alu_ctrl    <= alu_nop;
3895 
                                          cc_ctrl     <= latch_cc;
3896 
                 md_ctrl     <= latch_md;
3897 
                           next_state  <= fetch_state;
3898 4 dilbert57 
               end case;
3899 2 dilbert57 
           --
3900 
                          -- 16 bit Write state
3901 
                          -- write high byte of ALU output.
3902 
                          -- EA hold address of memory to write to
3903 
                          -- Advance the effective address in ALU
3904 
                          --
3905 
                          when write16_state =>
3906 
                                 -- default
3907 
             acca_ctrl  <= latch_acca;
3908 
             accb_ctrl  <= latch_accb;
3909 
             ix_ctrl    <= latch_ix;
3910 
             iy_ctrl    <= latch_iy;
3911 
             sp_ctrl    <= latch_sp;
3912 
             pc_ctrl    <= latch_pc;
3913 
             md_ctrl    <= latch_md;
3914 
             iv_ctrl    <= latch_iv;
3915 
                                 count_ctrl <= reset_count;
3916 
                            op_ctrl    <= latch_op;
3917 
                                 pre_ctrl   <= latch_pre;
3918 
                                 -- increment the effective address
3919 
                                 left_ctrl  <= ea_left;
3920 
                                 right_ctrl <= one_right;
3921 
                                 alu_ctrl   <= alu_add16;
3922 
             cc_ctrl    <= latch_cc;
3923 
                            ea_ctrl    <= load_ea;
3924 
                                 -- write the ALU hi byte to ea
3925 
             addr_ctrl  <= write_ad;
3926 
             dout_ctrl  <= md_hi_dout;
3927 
                                 next_state <= write8_state;
3928 
           --
3929 
                          -- 8 bit write
3930 
                          -- Write low 8 bits of ALU output
3931 
                          --
3932 
                          when write8_state =>
3933 
                                 -- default registers
3934 
             acca_ctrl  <= latch_acca;
3935 
             accb_ctrl  <= latch_accb;
3936 
             ix_ctrl    <= latch_ix;
3937 
             iy_ctrl    <= latch_iy;
3938 
             sp_ctrl    <= latch_sp;
3939 
             pc_ctrl    <= latch_pc;
3940 
             md_ctrl    <= latch_md;
3941 
             iv_ctrl    <= latch_iv;
3942 
                                 count_ctrl <= reset_count;
3943 
                            op_ctrl    <= latch_op;
3944 
                                 pre_ctrl   <= latch_pre;
3945 
             ea_ctrl    <= latch_ea;
3946 
                                 -- idle the ALU
3947 
             left_ctrl  <= acca_left;
3948 
             right_ctrl <= zero_right;
3949 
             alu_ctrl   <= alu_nop;
3950 
             cc_ctrl    <= latch_cc;
3951 
                                 -- write ALU low byte output
3952 
             addr_ctrl  <= write_ad;
3953 
             dout_ctrl  <= md_lo_dout;
3954 
                                 next_state <= fetch_state;
3955 
 
3956 
                          when psha_state =>
3957 
                                 -- default registers
3958 
             acca_ctrl  <= latch_acca;
3959 
             accb_ctrl  <= latch_accb;
3960 
             ix_ctrl    <= latch_ix;
3961 
             iy_ctrl    <= latch_iy;
3962 
             pc_ctrl    <= latch_pc;
3963 
             md_ctrl    <= latch_md;
3964 
             iv_ctrl    <= latch_iv;
3965 
                                 count_ctrl <= reset_count;
3966 
                            op_ctrl    <= latch_op;
3967 
                                 pre_ctrl   <= latch_pre;
3968 
             ea_ctrl    <= latch_ea;
3969 
             -- decrement sp
3970 
             left_ctrl  <= sp_left;
3971 
             right_ctrl <= one_right;
3972 
             alu_ctrl   <= alu_sub16;
3973 
             cc_ctrl    <= latch_cc;
3974 
             sp_ctrl    <= load_sp;
3975 
                                 -- write acca
3976 
             addr_ctrl  <= push_ad;
3977 
                            dout_ctrl  <= acca_dout;
3978 
             next_state <= fetch_state;
3979 
 
3980 
                          when pula_state =>
3981 
                                 -- default registers
3982 
             acca_ctrl  <= latch_acca;
3983 
             accb_ctrl  <= latch_accb;
3984 
             ix_ctrl    <= latch_ix;
3985 
             iy_ctrl    <= latch_iy;
3986 
             pc_ctrl    <= latch_pc;
3987 
             md_ctrl    <= latch_md;
3988 
             iv_ctrl    <= latch_iv;
3989 
                                 count_ctrl <= reset_count;
3990 
                            op_ctrl    <= latch_op;
3991 
                                 pre_ctrl   <= latch_pre;
3992 
             ea_ctrl    <= latch_ea;
3993 
                                 -- idle sp
3994 
             left_ctrl  <= sp_left;
3995 
             right_ctrl <= zero_right;
3996 
             alu_ctrl   <= alu_nop;
3997 
             cc_ctrl    <= latch_cc;
3998 
             sp_ctrl    <= latch_sp;
3999 
                                 -- read acca
4000 
                                 acca_ctrl  <= pull_acca;
4001 
             addr_ctrl  <= pull_ad;
4002 
             dout_ctrl  <= acca_dout;
4003 
             next_state <= fetch_state;
4004 
 
4005 
                          when pshb_state =>
4006 
                                 -- default registers
4007 
             acca_ctrl  <= latch_acca;
4008 
             accb_ctrl  <= latch_accb;
4009 
             ix_ctrl    <= latch_ix;
4010 
             iy_ctrl    <= latch_iy;
4011 
             pc_ctrl    <= latch_pc;
4012 
             md_ctrl    <= latch_md;
4013 
             iv_ctrl    <= latch_iv;
4014 
                                 count_ctrl <= reset_count;
4015 
                            op_ctrl    <= latch_op;
4016 
                                 pre_ctrl   <= latch_pre;
4017 
             ea_ctrl    <= latch_ea;
4018 
             -- decrement sp
4019 
             left_ctrl  <= sp_left;
4020 
             right_ctrl <= one_right;
4021 
             alu_ctrl   <= alu_sub16;
4022 
             cc_ctrl    <= latch_cc;
4023 
             sp_ctrl    <= load_sp;
4024 
                                 -- write accb
4025 
             addr_ctrl  <= push_ad;
4026 
                            dout_ctrl  <= accb_dout;
4027 
             next_state <= fetch_state;
4028 
 
4029 
                          when pulb_state =>
4030 
                                 -- default
4031 
             acca_ctrl  <= latch_acca;
4032 
             accb_ctrl  <= latch_accb;
4033 
             ix_ctrl    <= latch_ix;
4034 
             iy_ctrl    <= latch_iy;
4035 
             pc_ctrl    <= latch_pc;
4036 
             md_ctrl    <= latch_md;
4037 
             iv_ctrl    <= latch_iv;
4038 
                                 count_ctrl <= reset_count;
4039 
                            op_ctrl    <= latch_op;
4040 
                                 pre_ctrl   <= latch_pre;
4041 
             ea_ctrl    <= latch_ea;
4042 
                                 -- idle sp
4043 
             left_ctrl  <= sp_left;
4044 
             right_ctrl <= zero_right;
4045 
             alu_ctrl   <= alu_nop;
4046 
             cc_ctrl    <= latch_cc;
4047 
             sp_ctrl    <= latch_sp;
4048 
                                 -- read accb
4049 
                                 accb_ctrl  <= pull_accb;
4050 
             addr_ctrl  <= pull_ad;
4051 
             dout_ctrl  <= accb_dout;
4052 
             next_state <= fetch_state;
4053 
 
4054 4 dilbert57 
                          when pshxy_lo_state =>
4055 2 dilbert57 
                                 -- default
4056 
             acca_ctrl  <= latch_acca;
4057 
             accb_ctrl  <= latch_accb;
4058 
             ix_ctrl    <= latch_ix;
4059 
             iy_ctrl    <= latch_iy;
4060 
             sp_ctrl    <= latch_sp;
4061 
             pc_ctrl    <= latch_pc;
4062 
             md_ctrl    <= latch_md;
4063 
             iv_ctrl    <= latch_iv;
4064 
                                 count_ctrl <= reset_count;
4065 
                            op_ctrl    <= latch_op;
4066 
                                 pre_ctrl   <= latch_pre;
4067 
             ea_ctrl    <= latch_ea;
4068 
             -- decrement sp
4069 
             left_ctrl  <= sp_left;
4070 
             right_ctrl <= one_right;
4071 
             alu_ctrl   <= alu_sub16;
4072 
             cc_ctrl    <= latch_cc;
4073 
             sp_ctrl    <= load_sp;
4074 
                                 -- write ix low
4075 
             addr_ctrl  <= push_ad;
4076 
                                 if pre_byte = "00011000" then
4077 
                              dout_ctrl  <= iy_lo_dout;
4078 
                                 else
4079 
                              dout_ctrl  <= ix_lo_dout;
4080 
                                 end if;
4081 4 dilbert57 
             next_state <= pshxy_hi_state;
4082 2 dilbert57 
 
4083 4 dilbert57 
                          when pshxy_hi_state =>
4084 2 dilbert57 
                                 -- default registers
4085 
             acca_ctrl  <= latch_acca;
4086 
             accb_ctrl  <= latch_accb;
4087 
             ix_ctrl    <= latch_ix;
4088 
             iy_ctrl    <= latch_iy;
4089 
             pc_ctrl    <= latch_pc;
4090 
             md_ctrl    <= latch_md;
4091 
             iv_ctrl    <= latch_iv;
4092 
                                 count_ctrl <= reset_count;
4093 
                            op_ctrl    <= latch_op;
4094 
                                 pre_ctrl   <= latch_pre;
4095 
             ea_ctrl    <= latch_ea;
4096 
             -- decrement sp
4097 
             left_ctrl  <= sp_left;
4098 
             right_ctrl <= one_right;
4099 
             alu_ctrl   <= alu_sub16;
4100 
             cc_ctrl    <= latch_cc;
4101 
             sp_ctrl    <= load_sp;
4102 
                                 -- write ix / iy hi
4103 
             addr_ctrl  <= push_ad;
4104 
                                 if pre_byte = "00011000" then
4105 
                              dout_ctrl  <= iy_hi_dout;
4106 
                                 else
4107 
                              dout_ctrl  <= ix_hi_dout;
4108 
                                 end if;
4109 
             next_state <= fetch_state;
4110 
 
4111 4 dilbert57 
                          when pulxy_hi_state =>
4112 2 dilbert57 
                                 -- default
4113 
             acca_ctrl  <= latch_acca;
4114 
             accb_ctrl  <= latch_accb;
4115 
             pc_ctrl    <= latch_pc;
4116 
             md_ctrl    <= latch_md;
4117 
             iv_ctrl    <= latch_iv;
4118 
                                 count_ctrl <= reset_count;
4119 
                            op_ctrl    <= latch_op;
4120 
                                 pre_ctrl   <= latch_pre;
4121 
             ea_ctrl    <= latch_ea;
4122 
             -- increment sp
4123 
             left_ctrl  <= sp_left;
4124 
             right_ctrl <= one_right;
4125 
             alu_ctrl   <= alu_add16;
4126 
             cc_ctrl    <= latch_cc;
4127 
             sp_ctrl    <= load_sp;
4128 
                                 -- pull ix hi
4129 
                                 if pre_byte = "00011000" then
4130 
                                   ix_ctrl    <= latch_ix;
4131 
                                   iy_ctrl    <= pull_hi_iy;
4132 
               dout_ctrl  <= iy_hi_dout;
4133 
                                 else
4134 
                                   ix_ctrl    <= pull_hi_ix;
4135 
                                   iy_ctrl    <= latch_iy;
4136 
               dout_ctrl  <= ix_hi_dout;
4137 
                                 end if;
4138 
             addr_ctrl  <= pull_ad;
4139 4 dilbert57 
             next_state <= pulxy_lo_state;
4140 2 dilbert57 
 
4141 4 dilbert57 
                          when pulxy_lo_state =>
4142 2 dilbert57 
                                 -- default
4143 
             acca_ctrl  <= latch_acca;
4144 
             accb_ctrl  <= latch_accb;
4145 
             pc_ctrl    <= latch_pc;
4146 
             md_ctrl    <= latch_md;
4147 
             iv_ctrl    <= latch_iv;
4148 
                                 count_ctrl <= reset_count;
4149 
                            op_ctrl    <= latch_op;
4150 
                                 pre_ctrl   <= latch_pre;
4151 
             ea_ctrl    <= latch_ea;
4152 
                                 -- idle sp
4153 
             left_ctrl  <= sp_left;
4154 
             right_ctrl <= zero_right;
4155 
             alu_ctrl   <= alu_nop;
4156 
             cc_ctrl    <= latch_cc;
4157 
             sp_ctrl    <= latch_sp;
4158 
                                 -- read ix low
4159 
                                 if pre_byte = "00011000" then
4160 
                                   ix_ctrl    <= latch_ix;
4161 
                                   iy_ctrl    <= pull_lo_iy;
4162 
               dout_ctrl  <= iy_lo_dout;
4163 
                                 else
4164 
                                   ix_ctrl    <= pull_lo_ix;
4165 
                                   iy_ctrl    <= latch_iy;
4166 
               dout_ctrl  <= ix_lo_dout;
4167 
                                 end if;
4168 
             addr_ctrl  <= pull_ad;
4169 
             next_state <= fetch_state;
4170 
 
4171 
           --
4172 
                          -- return from interrupt
4173 
                          -- enter here from bogus interrupts
4174 
                          --
4175 
                          when rti_state =>
4176 
                                 -- default registers
4177 
             acca_ctrl  <= latch_acca;
4178 
             accb_ctrl  <= latch_accb;
4179 
             ix_ctrl    <= latch_ix;
4180 
             iy_ctrl    <= latch_iy;
4181 
             pc_ctrl    <= latch_pc;
4182 
             md_ctrl    <= latch_md;
4183 
             iv_ctrl    <= latch_iv;
4184 
                                 count_ctrl <= reset_count;
4185 
                            op_ctrl    <= latch_op;
4186 
                                 pre_ctrl   <= latch_pre;
4187 
             ea_ctrl    <= latch_ea;
4188 
                                 -- increment sp
4189 
             left_ctrl  <= sp_left;
4190 
             right_ctrl <= one_right;
4191 
             alu_ctrl   <= alu_add16;
4192 
             sp_ctrl    <= load_sp;
4193 
                                 -- idle address bus
4194 
             cc_ctrl    <= latch_cc;
4195 
             addr_ctrl  <= idle_ad;
4196 
             dout_ctrl  <= cc_dout;
4197 
             next_state <= rti_cc_state;
4198 
 
4199 
                          when rti_cc_state =>
4200 
                                 -- default registers
4201 
             acca_ctrl  <= latch_acca;
4202 
             accb_ctrl  <= latch_accb;
4203 
             ix_ctrl    <= latch_ix;
4204 
             iy_ctrl    <= latch_iy;
4205 
             pc_ctrl    <= latch_pc;
4206 
             md_ctrl    <= latch_md;
4207 
             iv_ctrl    <= latch_iv;
4208 
                                 count_ctrl <= reset_count;
4209 
                            op_ctrl    <= latch_op;
4210 
                                 pre_ctrl   <= latch_pre;
4211 
             ea_ctrl    <= latch_ea;
4212 
                                 -- increment sp
4213 
             left_ctrl  <= sp_left;
4214 
             right_ctrl <= one_right;
4215 
             alu_ctrl   <= alu_add16;
4216 
             sp_ctrl    <= load_sp;
4217 
                                 -- read cc
4218 
             cc_ctrl    <= pull_cc;
4219 
             addr_ctrl  <= pull_ad;
4220 
             dout_ctrl  <= cc_dout;
4221 
             next_state <= rti_accb_state;
4222 
 
4223 
                          when rti_accb_state =>
4224 
                                 -- default registers
4225 
             acca_ctrl  <= latch_acca;
4226 
             ix_ctrl    <= latch_ix;
4227 
             iy_ctrl    <= latch_iy;
4228 
             pc_ctrl    <= latch_pc;
4229 
             md_ctrl    <= latch_md;
4230 
             iv_ctrl    <= latch_iv;
4231 
                                 count_ctrl <= reset_count;
4232 
                            op_ctrl    <= latch_op;
4233 
                                 pre_ctrl   <= latch_pre;
4234 
             ea_ctrl    <= latch_ea;
4235 
                                 -- increment sp
4236 
             left_ctrl  <= sp_left;
4237 
             right_ctrl <= one_right;
4238 
             alu_ctrl   <= alu_add16;
4239 
             cc_ctrl    <= latch_cc;
4240 
             sp_ctrl    <= load_sp;
4241 
                                 -- read accb
4242 
                                 accb_ctrl  <= pull_accb;
4243 
             addr_ctrl  <= pull_ad;
4244 
             dout_ctrl  <= accb_dout;
4245 
             next_state <= rti_acca_state;
4246 
 
4247 
                          when rti_acca_state =>
4248 
                                 -- default registers
4249 
             accb_ctrl  <= latch_accb;
4250 
             ix_ctrl    <= latch_ix;
4251 
             iy_ctrl    <= latch_iy;
4252 
             pc_ctrl    <= latch_pc;
4253 
             md_ctrl    <= latch_md;
4254 
             iv_ctrl    <= latch_iv;
4255 
                                 count_ctrl <= reset_count;
4256 
                            op_ctrl    <= latch_op;
4257 
                                 pre_ctrl   <= latch_pre;
4258 
             ea_ctrl    <= latch_ea;
4259 
                                 -- increment sp
4260 
             left_ctrl  <= sp_left;
4261 
             right_ctrl <= one_right;
4262 
             alu_ctrl   <= alu_add16;
4263 
             cc_ctrl    <= latch_cc;
4264 
             sp_ctrl    <= load_sp;
4265 
                                 -- read acca
4266 
                                 acca_ctrl  <= pull_acca;
4267 
             addr_ctrl  <= pull_ad;
4268 
             dout_ctrl  <= acca_dout;
4269 
             next_state <= rti_ixh_state;
4270 
 
4271 
                          when rti_ixh_state =>
4272 
                                 -- default
4273 
             acca_ctrl  <= latch_acca;
4274 
             accb_ctrl  <= latch_accb;
4275 
             iy_ctrl    <= latch_iy;
4276 
             pc_ctrl    <= latch_pc;
4277 
             md_ctrl    <= latch_md;
4278 
             iv_ctrl    <= latch_iv;
4279 
                                 count_ctrl <= reset_count;
4280 
                            op_ctrl    <= latch_op;
4281 
                                 pre_ctrl   <= latch_pre;
4282 
             ea_ctrl    <= latch_ea;
4283 
                                 -- increment sp
4284 
             left_ctrl  <= sp_left;
4285 
             right_ctrl <= one_right;
4286 
             alu_ctrl   <= alu_add16;
4287 
             cc_ctrl    <= latch_cc;
4288 
             sp_ctrl    <= load_sp;
4289 
                                 -- read ix hi
4290 
                                 ix_ctrl    <= pull_hi_ix;
4291 
             addr_ctrl  <= pull_ad;
4292 
             dout_ctrl  <= ix_hi_dout;
4293 
             next_state <= rti_ixl_state;
4294 
 
4295 
                          when rti_ixl_state =>
4296 
                                 -- default
4297 
             acca_ctrl  <= latch_acca;
4298 
             accb_ctrl  <= latch_accb;
4299 
             iy_ctrl    <= latch_iy;
4300 
             pc_ctrl    <= latch_pc;
4301 
             md_ctrl    <= latch_md;
4302 
             iv_ctrl    <= latch_iv;
4303 
                                 count_ctrl <= reset_count;
4304 
                            op_ctrl    <= latch_op;
4305 
                                 pre_ctrl   <= latch_pre;
4306 
             ea_ctrl    <= latch_ea;
4307 
                                 -- increment sp
4308 
             left_ctrl  <= sp_left;
4309 
             right_ctrl <= one_right;
4310 
             alu_ctrl   <= alu_add16;
4311 
             cc_ctrl    <= latch_cc;
4312 
             sp_ctrl    <= load_sp;
4313 
                                 -- read ix low
4314 
                                 ix_ctrl    <= pull_lo_ix;
4315 
             addr_ctrl  <= pull_ad;
4316 
             dout_ctrl  <= ix_lo_dout;
4317 
             next_state <= rti_iyh_state;
4318 
 
4319 
                          when rti_iyh_state =>
4320 
                                 -- default
4321 
             acca_ctrl  <= latch_acca;
4322 
             accb_ctrl  <= latch_accb;
4323 
             ix_ctrl    <= latch_ix;
4324 
             pc_ctrl    <= latch_pc;
4325 
             md_ctrl    <= latch_md;
4326 
             iv_ctrl    <= latch_iv;
4327 
                                 count_ctrl <= reset_count;
4328 
                            op_ctrl    <= latch_op;
4329 
                                 pre_ctrl   <= latch_pre;
4330 
             ea_ctrl    <= latch_ea;
4331 
                                 -- increment sp
4332 
             left_ctrl  <= sp_left;
4333 
             right_ctrl <= one_right;
4334 
             alu_ctrl   <= alu_add16;
4335 
             cc_ctrl    <= latch_cc;
4336 
             sp_ctrl    <= load_sp;
4337 
                                 -- read iy hi
4338 
                                 iy_ctrl    <= pull_hi_iy;
4339 
             addr_ctrl  <= pull_ad;
4340 
             dout_ctrl  <= iy_hi_dout;
4341 
             next_state <= rti_iyl_state;
4342 
 
4343 
                          when rti_iyl_state =>
4344 
                                 -- default
4345 
             acca_ctrl  <= latch_acca;
4346 
             accb_ctrl  <= latch_accb;
4347 
             ix_ctrl    <= latch_ix;
4348 
             pc_ctrl    <= latch_pc;
4349 
             md_ctrl    <= latch_md;
4350 
             iv_ctrl    <= latch_iv;
4351 
                                 count_ctrl <= reset_count;
4352 
                            op_ctrl    <= latch_op;
4353 
                                 pre_ctrl   <= latch_pre;
4354 
             ea_ctrl    <= latch_ea;
4355 
                                 -- increment sp
4356 
             left_ctrl  <= sp_left;
4357 
             right_ctrl <= one_right;
4358 
             alu_ctrl   <= alu_add16;
4359 
             cc_ctrl    <= latch_cc;
4360 
             sp_ctrl    <= load_sp;
4361 
                                 -- read iy low
4362 
                                 iy_ctrl    <= pull_lo_iy;
4363 
             addr_ctrl  <= pull_ad;
4364 
             dout_ctrl  <= iy_lo_dout;
4365 
             next_state <= rti_pch_state;
4366 
 
4367 
                          when rti_pch_state =>
4368 
                                 -- default
4369 
             acca_ctrl  <= latch_acca;
4370 
             accb_ctrl  <= latch_accb;
4371 
             ix_ctrl    <= latch_ix;
4372 
             iy_ctrl    <= latch_iy;
4373 
             pc_ctrl    <= latch_pc;
4374 
             md_ctrl    <= latch_md;
4375 
             iv_ctrl    <= latch_iv;
4376 
                                 count_ctrl <= reset_count;
4377 
                            op_ctrl    <= latch_op;
4378 
                                 pre_ctrl   <= latch_pre;
4379 
             ea_ctrl    <= latch_ea;
4380 
                  -- increment sp
4381 
             left_ctrl  <= sp_left;
4382 
             right_ctrl <= one_right;
4383 
             alu_ctrl   <= alu_add16;
4384 
             cc_ctrl    <= latch_cc;
4385 
             sp_ctrl    <= load_sp;
4386 
                                 -- pull pc hi
4387 
                                 pc_ctrl    <= pull_hi_pc;
4388 
             addr_ctrl  <= pull_ad;
4389 
             dout_ctrl  <= pc_hi_dout;
4390 
             next_state <= rti_pcl_state;
4391 
 
4392 
                          when rti_pcl_state =>
4393 
                                 -- default
4394 
             acca_ctrl  <= latch_acca;
4395 
             accb_ctrl  <= latch_accb;
4396 
             ix_ctrl    <= latch_ix;
4397 
             iy_ctrl    <= latch_iy;
4398 
             md_ctrl    <= latch_md;
4399 
             iv_ctrl    <= latch_iv;
4400 
                                 count_ctrl <= reset_count;
4401 
                            op_ctrl    <= latch_op;
4402 
                                 pre_ctrl   <= latch_pre;
4403 
             ea_ctrl    <= latch_ea;
4404 
                                 -- idle sp
4405 
             left_ctrl  <= sp_left;
4406 
             right_ctrl <= zero_right;
4407 
             alu_ctrl   <= alu_nop;
4408 
             cc_ctrl    <= latch_cc;
4409 
             sp_ctrl    <= latch_sp;
4410 
                  -- pull pc low
4411 
                                 pc_ctrl    <= pull_lo_pc;
4412 
             addr_ctrl  <= pull_ad;
4413 
             dout_ctrl  <= pc_lo_dout;
4414 
             next_state <= fetch_state;
4415 
 
4416 
                          --
4417 
                          -- here on interrupt
4418 
                          -- iv register hold interrupt type
4419 
                          --
4420 
                          when int_pcl_state =>
4421 
                                 -- default
4422 
             acca_ctrl  <= latch_acca;
4423 
             accb_ctrl  <= latch_accb;
4424 
             ix_ctrl    <= latch_ix;
4425 
             iy_ctrl    <= latch_iy;
4426 
             pc_ctrl    <= latch_pc;
4427 
             md_ctrl    <= latch_md;
4428 
             iv_ctrl    <= latch_iv;
4429 
                                 count_ctrl <= reset_count;
4430 
                            op_ctrl    <= latch_op;
4431 
                                 pre_ctrl   <= latch_pre;
4432 
             ea_ctrl    <= latch_ea;
4433 
             -- decrement sp
4434 
             left_ctrl  <= sp_left;
4435 
             right_ctrl <= one_right;
4436 
             alu_ctrl   <= alu_sub16;
4437 
             cc_ctrl    <= latch_cc;
4438 
             sp_ctrl    <= load_sp;
4439 
                                 -- write pc low
4440 
             addr_ctrl  <= push_ad;
4441 
                            dout_ctrl  <= pc_lo_dout;
4442 
             next_state <= int_pch_state;
4443 
 
4444 
                          when int_pch_state =>
4445 
                                 -- default
4446 
             acca_ctrl  <= latch_acca;
4447 
             accb_ctrl  <= latch_accb;
4448 
             ix_ctrl    <= latch_ix;
4449 
             iy_ctrl    <= latch_iy;
4450 
             pc_ctrl    <= latch_pc;
4451 
             md_ctrl    <= latch_md;
4452 
             iv_ctrl    <= latch_iv;
4453 
                                 count_ctrl <= reset_count;
4454 
                            op_ctrl    <= latch_op;
4455 
                                 pre_ctrl   <= latch_pre;
4456 
             ea_ctrl    <= latch_ea;
4457 
             -- decrement sp
4458 
             left_ctrl  <= sp_left;
4459 
             right_ctrl <= one_right;
4460 
             alu_ctrl   <= alu_sub16;
4461 
             cc_ctrl    <= latch_cc;
4462 
             sp_ctrl    <= load_sp;
4463 
                                 -- write pc hi
4464 
             addr_ctrl  <= push_ad;
4465 
                            dout_ctrl  <= pc_hi_dout;
4466 
             next_state <= int_iyl_state;
4467 
 
4468 
                          when int_iyl_state =>
4469 
                                 -- default
4470 
             acca_ctrl  <= latch_acca;
4471 
             accb_ctrl  <= latch_accb;
4472 
             ix_ctrl    <= latch_ix;
4473 
             iy_ctrl    <= latch_iy;
4474 
             pc_ctrl    <= latch_pc;
4475 
             md_ctrl    <= latch_md;
4476 
             iv_ctrl    <= latch_iv;
4477 
                                 count_ctrl <= reset_count;
4478 
                            op_ctrl    <= latch_op;
4479 
                                 pre_ctrl   <= latch_pre;
4480 
             ea_ctrl    <= latch_ea;
4481 
             -- decrement sp
4482 
             left_ctrl  <= sp_left;
4483 
             right_ctrl <= one_right;
4484 
             alu_ctrl   <= alu_sub16;
4485 
             cc_ctrl    <= latch_cc;
4486 
             sp_ctrl    <= load_sp;
4487 
                                 -- write iy low
4488 
             addr_ctrl  <= push_ad;
4489 
                            dout_ctrl  <= iy_lo_dout;
4490 
             next_state <= int_iyh_state;
4491 
 
4492 
                          when int_iyh_state =>
4493 
                                 -- default
4494 
             acca_ctrl  <= latch_acca;
4495 
             accb_ctrl  <= latch_accb;
4496 
             ix_ctrl    <= latch_ix;
4497 
             iy_ctrl    <= latch_iy;
4498 
             pc_ctrl    <= latch_pc;
4499 
             md_ctrl    <= latch_md;
4500 
             iv_ctrl    <= latch_iv;
4501 
                                 count_ctrl <= reset_count;
4502 
                            op_ctrl    <= latch_op;
4503 
                                 pre_ctrl   <= latch_pre;
4504 
             ea_ctrl    <= latch_ea;
4505 
             -- decrement sp
4506 
             left_ctrl  <= sp_left;
4507 
             right_ctrl <= one_right;
4508 
             alu_ctrl   <= alu_sub16;
4509 
             cc_ctrl    <= latch_cc;
4510 
             sp_ctrl    <= load_sp;
4511 
                                 -- write iy hi
4512 
             addr_ctrl  <= push_ad;
4513 
                            dout_ctrl  <= iy_hi_dout;
4514 
             next_state <= int_ixl_state;
4515 
 
4516 
                          when int_ixl_state =>
4517 
                                 -- default
4518 
             acca_ctrl  <= latch_acca;
4519 
             accb_ctrl  <= latch_accb;
4520 
             ix_ctrl    <= latch_ix;
4521 
             iy_ctrl    <= latch_iy;
4522 
             pc_ctrl    <= latch_pc;
4523 
             md_ctrl    <= latch_md;
4524 
             iv_ctrl    <= latch_iv;
4525 
                                 count_ctrl <= reset_count;
4526 
                            op_ctrl    <= latch_op;
4527 
                                 pre_ctrl   <= latch_pre;
4528 
             ea_ctrl    <= latch_ea;
4529 
             -- decrement sp
4530 
             left_ctrl  <= sp_left;
4531 
             right_ctrl <= one_right;
4532 
             alu_ctrl   <= alu_sub16;
4533 
             cc_ctrl    <= latch_cc;
4534 
             sp_ctrl    <= load_sp;
4535 
                                 -- write ix low
4536 
             addr_ctrl  <= push_ad;
4537 
                            dout_ctrl  <= ix_lo_dout;
4538 
             next_state <= int_ixh_state;
4539 
 
4540 
                          when int_ixh_state =>
4541 
                                 -- default
4542 
             acca_ctrl  <= latch_acca;
4543 
             accb_ctrl  <= latch_accb;
4544 
             ix_ctrl    <= latch_ix;
4545 
             iy_ctrl    <= latch_iy;
4546 
             pc_ctrl    <= latch_pc;
4547 
             md_ctrl    <= latch_md;
4548 
             iv_ctrl    <= latch_iv;
4549 
                                 count_ctrl <= reset_count;
4550 
                            op_ctrl    <= latch_op;
4551 
                                 pre_ctrl   <= latch_pre;
4552 
             ea_ctrl    <= latch_ea;
4553 
             -- decrement sp
4554 
             left_ctrl  <= sp_left;
4555 
             right_ctrl <= one_right;
4556 
             alu_ctrl   <= alu_sub16;
4557 
             cc_ctrl    <= latch_cc;
4558 
             sp_ctrl    <= load_sp;
4559 
                                 -- write ix hi
4560 
             addr_ctrl  <= push_ad;
4561 
                            dout_ctrl  <= ix_hi_dout;
4562 
             next_state <= int_acca_state;
4563 
 
4564 
                          when int_acca_state =>
4565 
                                 -- default
4566 
             acca_ctrl  <= latch_acca;
4567 
             accb_ctrl  <= latch_accb;
4568 
             ix_ctrl    <= latch_ix;
4569 
             iy_ctrl    <= latch_iy;
4570 
             pc_ctrl    <= latch_pc;
4571 
             md_ctrl    <= latch_md;
4572 
             iv_ctrl    <= latch_iv;
4573 
                                 count_ctrl <= reset_count;
4574 
                            op_ctrl    <= latch_op;
4575 
                                 pre_ctrl   <= latch_pre;
4576 
             ea_ctrl    <= latch_ea;
4577 
             -- decrement sp
4578 
             left_ctrl  <= sp_left;
4579 
             right_ctrl <= one_right;
4580 
             alu_ctrl   <= alu_sub16;
4581 
             cc_ctrl    <= latch_cc;
4582 
             sp_ctrl    <= load_sp;
4583 
                                 -- write acca
4584 
             addr_ctrl  <= push_ad;
4585 
                            dout_ctrl  <= acca_dout;
4586 
             next_state <= int_accb_state;
4587 
 
4588 
 
4589 
                          when int_accb_state =>
4590 
                                 -- default
4591 
             acca_ctrl  <= latch_acca;
4592 
             accb_ctrl  <= latch_accb;
4593 
             ix_ctrl    <= latch_ix;
4594 
             iy_ctrl    <= latch_iy;
4595 
             pc_ctrl    <= latch_pc;
4596 
             md_ctrl    <= latch_md;
4597 
             iv_ctrl    <= latch_iv;
4598 
                                 count_ctrl <= reset_count;
4599 
                            op_ctrl    <= latch_op;
4600 
                                 pre_ctrl   <= latch_pre;
4601 
             ea_ctrl    <= latch_ea;
4602 
             -- decrement sp
4603 
             left_ctrl  <= sp_left;
4604 
             right_ctrl <= one_right;
4605 
             alu_ctrl   <= alu_sub16;
4606 
             cc_ctrl    <= latch_cc;
4607 
             sp_ctrl    <= load_sp;
4608 
                                 -- write accb
4609 
             addr_ctrl  <= push_ad;
4610 
                            dout_ctrl  <= accb_dout;
4611 
             next_state <= int_cc_state;
4612 
 
4613 
                          when int_cc_state =>
4614 
                                 -- default
4615 
             acca_ctrl  <= latch_acca;
4616 
             accb_ctrl  <= latch_accb;
4617 
             ix_ctrl    <= latch_ix;
4618 
             iy_ctrl    <= latch_iy;
4619 
             pc_ctrl    <= latch_pc;
4620 
             md_ctrl    <= latch_md;
4621 
                                 count_ctrl <= reset_count;
4622 
                            op_ctrl    <= latch_op;
4623 
                                 pre_ctrl   <= latch_pre;
4624 
             ea_ctrl    <= latch_ea;
4625 
             -- decrement sp
4626 
             left_ctrl  <= sp_left;
4627 
             right_ctrl <= one_right;
4628 
             alu_ctrl   <= alu_sub16;
4629 
             cc_ctrl    <= latch_cc;
4630 
             sp_ctrl    <= load_sp;
4631 
                                 -- write cc
4632 
             addr_ctrl  <= push_ad;
4633 
                            dout_ctrl  <= cc_dout;
4634 
                                 --
4635 
                            -- XIRQ is level sensitive
4636 
                                 --
4637 
                            if (xirq = '1') and (cc(XBIT) = '0') then
4638 
                                        iv_ctrl    <= xirq_iv;
4639 
                              next_state <= int_maskx_state;
4640 
                            else
4641 
                                        --
4642 
                                        -- IRQ is level sensitive
4643 
                                        --
4644 
                                   if (irq = '1') and (cc(IBIT) = '0') then
4645 
                                          iv_ctrl    <= irq_iv;
4646 
                                next_state <= int_maski_state;
4647 
               else
4648 
                                          case op_code is
4649 
                                          when "00111110" => -- WAI (wait for interrupt)
4650 
                   iv_ctrl    <= latch_iv;
4651 
                        next_state <= int_wai_state;
4652 
                                          when "00111111" => -- SWI (Software interrupt)
4653 
                   iv_ctrl    <= swi_iv;
4654 
                        next_state <= vect_hi_state;
4655 
                                          when others => -- bogus interrupt (return)
4656 
                   iv_ctrl    <= latch_iv;
4657 
                        next_state <= rti_state;
4658 
                                          end case;
4659 
                                        end if;
4660 
                                 end if;
4661 
 
4662 
                          when int_wai_state =>
4663 
                                 -- default
4664 
             acca_ctrl  <= latch_acca;
4665 
             accb_ctrl  <= latch_accb;
4666 
             ix_ctrl    <= latch_ix;
4667 
             iy_ctrl    <= latch_iy;
4668 
             pc_ctrl    <= latch_pc;
4669 
                                 count_ctrl <= reset_count;
4670 
             md_ctrl    <= latch_md;
4671 
                            op_ctrl    <= latch_op;
4672 
                                 pre_ctrl   <= latch_pre;
4673 
             ea_ctrl    <= latch_ea;
4674 
             -- enable interrupts
4675 
             left_ctrl  <= sp_left;
4676 
             right_ctrl <= one_right;
4677 
             alu_ctrl   <= alu_cli;
4678 
             cc_ctrl    <= load_cc;
4679 
             sp_ctrl    <= latch_sp;
4680 
                                 -- idle bus
4681 
             addr_ctrl  <= idle_ad;
4682 
                            dout_ctrl  <= cc_dout;
4683 
                            --
4684 
                                 -- XIRQ is level sensitive
4685 
                                 --
4686 
                            if (xirq = '1') and (cc(XBIT) = '0') then
4687 
                                        iv_ctrl    <= xirq_iv;
4688 
                              next_state <= int_maskx_state;
4689 
                            else
4690 
                                        --
4691 
                                        -- IRQ is level sensitive
4692 
                                        --
4693 
                                   if (irq = '1') and (cc(IBIT) = '0') then
4694 
                                          iv_ctrl    <= irq_iv;
4695 
                                next_state <= int_maski_state;
4696 
               else
4697 
                 iv_ctrl    <= latch_iv;
4698 
                      next_state <= int_wai_state;
4699 
                                        end if;
4700 
                                 end if;
4701 
 
4702 
                          when int_maskx_state =>
4703 
                                 -- default
4704 
             acca_ctrl  <= latch_acca;
4705 
             accb_ctrl  <= latch_accb;
4706 
             ix_ctrl    <= latch_ix;
4707 
             iy_ctrl    <= latch_iy;
4708 
             pc_ctrl    <= latch_pc;
4709 
             md_ctrl    <= latch_md;
4710 
             iv_ctrl    <= latch_iv;
4711 
                                 count_ctrl <= reset_count;
4712 
                            op_ctrl    <= latch_op;
4713 
                                 pre_ctrl   <= latch_pre;
4714 
             ea_ctrl    <= latch_ea;
4715 
                                 -- Mask IRQ
4716 
             left_ctrl  <= sp_left;
4717 
             right_ctrl <= zero_right;
4718 
                            alu_ctrl   <= alu_sex;
4719 
                                 cc_ctrl    <= load_cc;
4720 
             sp_ctrl    <= latch_sp;
4721 
                                 -- idle bus cycle
4722 
             addr_ctrl  <= idle_ad;
4723 
             dout_ctrl  <= md_lo_dout;
4724 
             next_state <= vect_hi_state;
4725 
 
4726 
                          when int_maski_state =>
4727 
                                 -- default
4728 
             acca_ctrl  <= latch_acca;
4729 
             accb_ctrl  <= latch_accb;
4730 
             ix_ctrl    <= latch_ix;
4731 
             iy_ctrl    <= latch_iy;
4732 
             pc_ctrl    <= latch_pc;
4733 
             md_ctrl    <= latch_md;
4734 
             iv_ctrl    <= latch_iv;
4735 
                                 count_ctrl <= reset_count;
4736 
                            op_ctrl    <= latch_op;
4737 
                                 pre_ctrl   <= latch_pre;
4738 
             ea_ctrl    <= latch_ea;
4739 
                                 -- Mask IRQ
4740 
             left_ctrl  <= sp_left;
4741 
             right_ctrl <= zero_right;
4742 
                            alu_ctrl   <= alu_sei;
4743 
                                 cc_ctrl    <= load_cc;
4744 
             sp_ctrl    <= latch_sp;
4745 
                                 -- idle bus cycle
4746 
             addr_ctrl  <= idle_ad;
4747 
             dout_ctrl  <= md_lo_dout;
4748 
             next_state <= vect_hi_state;
4749 
 
4750 
                          when others => -- halt on undefine states
4751 
                                 -- default
4752 
             acca_ctrl  <= latch_acca;
4753 
             accb_ctrl  <= latch_accb;
4754 
             ix_ctrl    <= latch_ix;
4755 
             iy_ctrl    <= latch_iy;
4756 
             sp_ctrl    <= latch_sp;
4757 
             pc_ctrl    <= latch_pc;
4758 
             md_ctrl    <= latch_md;
4759 
             iv_ctrl    <= latch_iv;
4760 
                                 count_ctrl <= reset_count;
4761 
                            op_ctrl    <= latch_op;
4762 
                                 pre_ctrl   <= latch_pre;
4763 
             ea_ctrl    <= latch_ea;
4764 
                                 -- do nothing in ALU
4765 
             left_ctrl  <= acca_left;
4766 
             right_ctrl <= zero_right;
4767 
             alu_ctrl   <= alu_nop;
4768 
             cc_ctrl    <= latch_cc;
4769 
                                 -- idle bus cycle
4770 
             addr_ctrl  <= idle_ad;
4771 
             dout_ctrl  <= md_lo_dout;
4772 
                            next_state <= halt_state;
4773 
                  end case;
4774 
end process;
4775 
 
4776 
--------------------------------
4777 
--
4778 
-- state machine
4779 
--
4780 
--------------------------------
4781 
 
4782 
change_state: process( clk, rst, state )
4783 
begin
4784 4 dilbert57 
  if rst = '1' then
4785 
         state <= reset_state;
4786 
  elsif clk'event and clk = '0' then
4787 
    state <= next_state;
4788 2 dilbert57 
  end if;
4789 
end process;
4790 
        -- output
4791 
 
4792 
end;
4793 
 

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