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dilbert57 |
--===========================================================================--
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--
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-- CPU11 Microprocessor Test Bench 4
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--
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-- Complete system test
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--
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-- John Kent 21st October 2002
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--
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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entity my_ram is
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port (
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clk : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector(5 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0));
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end;
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architecture ram_arch of my_ram is
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signal ram_reg00 : std_logic_vector(7 downto 0);
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signal ram_reg01 : std_logic_vector(7 downto 0);
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signal ram_reg02 : std_logic_vector(7 downto 0);
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signal ram_reg03 : std_logic_vector(7 downto 0);
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signal ram_reg04 : std_logic_vector(7 downto 0);
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signal ram_reg05 : std_logic_vector(7 downto 0);
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signal ram_reg06 : std_logic_vector(7 downto 0);
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signal ram_reg07 : std_logic_vector(7 downto 0);
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signal ram_reg08 : std_logic_vector(7 downto 0);
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signal ram_reg09 : std_logic_vector(7 downto 0);
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signal ram_reg010 : std_logic_vector(7 downto 0);
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signal ram_reg011 : std_logic_vector(7 downto 0);
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signal ram_reg012 : std_logic_vector(7 downto 0);
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signal ram_reg013 : std_logic_vector(7 downto 0);
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signal ram_reg014 : std_logic_vector(7 downto 0);
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signal ram_reg015 : std_logic_vector(7 downto 0);
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signal ram_reg10 : std_logic_vector(7 downto 0);
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signal ram_reg11 : std_logic_vector(7 downto 0);
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signal ram_reg12 : std_logic_vector(7 downto 0);
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signal ram_reg13 : std_logic_vector(7 downto 0);
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signal ram_reg14 : std_logic_vector(7 downto 0);
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signal ram_reg15 : std_logic_vector(7 downto 0);
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signal ram_reg16 : std_logic_vector(7 downto 0);
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signal ram_reg17 : std_logic_vector(7 downto 0);
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signal ram_reg18 : std_logic_vector(7 downto 0);
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signal ram_reg19 : std_logic_vector(7 downto 0);
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signal ram_reg110 : std_logic_vector(7 downto 0);
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signal ram_reg111 : std_logic_vector(7 downto 0);
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signal ram_reg112 : std_logic_vector(7 downto 0);
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signal ram_reg113 : std_logic_vector(7 downto 0);
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signal ram_reg114 : std_logic_vector(7 downto 0);
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signal ram_reg115 : std_logic_vector(7 downto 0);
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signal ram_reg20 : std_logic_vector(7 downto 0);
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signal ram_reg21 : std_logic_vector(7 downto 0);
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signal ram_reg22 : std_logic_vector(7 downto 0);
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signal ram_reg23 : std_logic_vector(7 downto 0);
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signal ram_reg24 : std_logic_vector(7 downto 0);
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signal ram_reg25 : std_logic_vector(7 downto 0);
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signal ram_reg26 : std_logic_vector(7 downto 0);
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signal ram_reg27 : std_logic_vector(7 downto 0);
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signal ram_reg28 : std_logic_vector(7 downto 0);
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signal ram_reg29 : std_logic_vector(7 downto 0);
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signal ram_reg210 : std_logic_vector(7 downto 0);
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signal ram_reg211 : std_logic_vector(7 downto 0);
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signal ram_reg212 : std_logic_vector(7 downto 0);
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signal ram_reg213 : std_logic_vector(7 downto 0);
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signal ram_reg214 : std_logic_vector(7 downto 0);
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signal ram_reg215 : std_logic_vector(7 downto 0);
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signal ram_reg30 : std_logic_vector(7 downto 0);
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signal ram_reg31 : std_logic_vector(7 downto 0);
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signal ram_reg32 : std_logic_vector(7 downto 0);
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signal ram_reg33 : std_logic_vector(7 downto 0);
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signal ram_reg34 : std_logic_vector(7 downto 0);
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signal ram_reg35 : std_logic_vector(7 downto 0);
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signal ram_reg36 : std_logic_vector(7 downto 0);
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signal ram_reg37 : std_logic_vector(7 downto 0);
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signal ram_reg38 : std_logic_vector(7 downto 0);
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signal ram_reg39 : std_logic_vector(7 downto 0);
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signal ram_reg310 : std_logic_vector(7 downto 0);
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signal ram_reg311 : std_logic_vector(7 downto 0);
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signal ram_reg312 : std_logic_vector(7 downto 0);
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signal ram_reg313 : std_logic_vector(7 downto 0);
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signal ram_reg314 : std_logic_vector(7 downto 0);
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signal ram_reg315 : std_logic_vector(7 downto 0);
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begin
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---------------------------------
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--
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-- Write DAT RAM
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--
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---------------------------------
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ram_write : process( clk, rst, addr, cs, rw, data_in )
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begin
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if rst = '1' then
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ram_reg00 <= "00000000";
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ram_reg01 <= "00000000";
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ram_reg02 <= "00000000";
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ram_reg03 <= "00000000";
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ram_reg04 <= "00000000";
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ram_reg05 <= "00000000";
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ram_reg06 <= "00000000";
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ram_reg07 <= "00000000";
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ram_reg08 <= "00000000";
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ram_reg09 <= "00000000";
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ram_reg010 <= "00000000";
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ram_reg011 <= "00000000";
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ram_reg012 <= "00000000";
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ram_reg013 <= "00000000";
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ram_reg014 <= "00000000";
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ram_reg015 <= "00000000";
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ram_reg10 <= "00000000";
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ram_reg11 <= "00000000";
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ram_reg12 <= "00000000";
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ram_reg13 <= "00000000";
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ram_reg14 <= "00000000";
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ram_reg15 <= "00000000";
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ram_reg16 <= "00000000";
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ram_reg17 <= "00000000";
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ram_reg18 <= "00000000";
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ram_reg19 <= "00000000";
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ram_reg110 <= "00000000";
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ram_reg111 <= "00000000";
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ram_reg112 <= "00000000";
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ram_reg113 <= "00000000";
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ram_reg114 <= "00000000";
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ram_reg115 <= "00000000";
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ram_reg20 <= "00000000";
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ram_reg21 <= "00000000";
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ram_reg22 <= "00000000";
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ram_reg23 <= "00000000";
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ram_reg24 <= "00000000";
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ram_reg25 <= "00000000";
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ram_reg26 <= "00000000";
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ram_reg27 <= "00000000";
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ram_reg28 <= "00000000";
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ram_reg29 <= "00000000";
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ram_reg210 <= "00000000";
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ram_reg211 <= "00000000";
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ram_reg212 <= "00000000";
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ram_reg213 <= "00000000";
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ram_reg214 <= "00000000";
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ram_reg215 <= "00000000";
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ram_reg30 <= "00000000";
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ram_reg31 <= "00000000";
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ram_reg32 <= "00000000";
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ram_reg33 <= "00000000";
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ram_reg34 <= "00000000";
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ram_reg35 <= "00000000";
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ram_reg36 <= "00000000";
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ram_reg37 <= "00000000";
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ram_reg38 <= "00000000";
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ram_reg39 <= "00000000";
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ram_reg310 <= "00000000";
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ram_reg311 <= "00000000";
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ram_reg312 <= "00000000";
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ram_reg313 <= "00000000";
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ram_reg314 <= "00000000";
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ram_reg315 <= "00000000";
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elsif clk'event and clk = '0' then
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if cs = '1' and rw = '0' then
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case addr is
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when "000000" =>
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ram_reg00(7 downto 0) <= data_in(7 downto 0);
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when "000001" =>
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ram_reg01(7 downto 0) <= data_in(7 downto 0);
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when "000010" =>
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ram_reg02(7 downto 0) <= data_in(7 downto 0);
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when "000011" =>
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ram_reg03(7 downto 0) <= data_in(7 downto 0);
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when "000100" =>
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ram_reg04(7 downto 0) <= data_in(7 downto 0);
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when "000101" =>
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ram_reg05(7 downto 0) <= data_in(7 downto 0);
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when "000110" =>
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ram_reg06(7 downto 0) <= data_in(7 downto 0);
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when "000111" =>
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ram_reg07(7 downto 0) <= data_in(7 downto 0);
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when "001000" =>
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ram_reg08(7 downto 0) <= data_in(7 downto 0);
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when "001001" =>
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ram_reg09(7 downto 0) <= data_in(7 downto 0);
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when "001010" =>
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ram_reg010(7 downto 0) <= data_in(7 downto 0);
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when "001011" =>
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ram_reg011(7 downto 0) <= data_in(7 downto 0);
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when "001100" =>
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ram_reg012(7 downto 0) <= data_in(7 downto 0);
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when "001101" =>
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ram_reg013(7 downto 0) <= data_in(7 downto 0);
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when "001110" =>
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ram_reg014(7 downto 0) <= data_in(7 downto 0);
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when "001111" =>
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ram_reg015(7 downto 0) <= data_in(7 downto 0);
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when "010000" =>
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ram_reg10(7 downto 0) <= data_in(7 downto 0);
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when "010001" =>
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ram_reg11(7 downto 0) <= data_in(7 downto 0);
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when "010010" =>
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ram_reg12(7 downto 0) <= data_in(7 downto 0);
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when "010011" =>
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ram_reg13(7 downto 0) <= data_in(7 downto 0);
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when "010100" =>
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ram_reg14(7 downto 0) <= data_in(7 downto 0);
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when "010101" =>
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ram_reg15(7 downto 0) <= data_in(7 downto 0);
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when "010110" =>
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ram_reg16(7 downto 0) <= data_in(7 downto 0);
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when "010111" =>
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ram_reg17(7 downto 0) <= data_in(7 downto 0);
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when "011000" =>
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ram_reg18(7 downto 0) <= data_in(7 downto 0);
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when "011001" =>
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ram_reg19(7 downto 0) <= data_in(7 downto 0);
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when "011010" =>
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ram_reg110(7 downto 0) <= data_in(7 downto 0);
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when "011011" =>
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ram_reg111(7 downto 0) <= data_in(7 downto 0);
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when "011100" =>
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ram_reg112(7 downto 0) <= data_in(7 downto 0);
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when "011101" =>
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ram_reg113(7 downto 0) <= data_in(7 downto 0);
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when "011110" =>
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ram_reg114(7 downto 0) <= data_in(7 downto 0);
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when "011111" =>
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ram_reg115(7 downto 0) <= data_in(7 downto 0);
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when "100000" =>
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ram_reg20(7 downto 0) <= data_in(7 downto 0);
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when "100001" =>
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ram_reg21(7 downto 0) <= data_in(7 downto 0);
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when "100010" =>
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ram_reg22(7 downto 0) <= data_in(7 downto 0);
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when "100011" =>
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ram_reg23(7 downto 0) <= data_in(7 downto 0);
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when "100100" =>
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ram_reg24(7 downto 0) <= data_in(7 downto 0);
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when "100101" =>
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ram_reg25(7 downto 0) <= data_in(7 downto 0);
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when "100110" =>
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ram_reg26(7 downto 0) <= data_in(7 downto 0);
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when "100111" =>
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ram_reg27(7 downto 0) <= data_in(7 downto 0);
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when "101000" =>
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ram_reg28(7 downto 0) <= data_in(7 downto 0);
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when "101001" =>
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ram_reg29(7 downto 0) <= data_in(7 downto 0);
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when "101010" =>
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ram_reg210(7 downto 0) <= data_in(7 downto 0);
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when "101011" =>
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ram_reg211(7 downto 0) <= data_in(7 downto 0);
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when "101100" =>
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ram_reg212(7 downto 0) <= data_in(7 downto 0);
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when "101101" =>
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ram_reg213(7 downto 0) <= data_in(7 downto 0);
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when "101110" =>
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ram_reg214(7 downto 0) <= data_in(7 downto 0);
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when "101111" =>
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ram_reg215(7 downto 0) <= data_in(7 downto 0);
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when "110000" =>
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ram_reg30(7 downto 0) <= data_in(7 downto 0);
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when "110001" =>
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ram_reg31(7 downto 0) <= data_in(7 downto 0);
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when "110010" =>
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ram_reg32(7 downto 0) <= data_in(7 downto 0);
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when "110011" =>
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ram_reg33(7 downto 0) <= data_in(7 downto 0);
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when "110100" =>
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ram_reg34(7 downto 0) <= data_in(7 downto 0);
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when "110101" =>
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ram_reg35(7 downto 0) <= data_in(7 downto 0);
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when "110110" =>
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ram_reg36(7 downto 0) <= data_in(7 downto 0);
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when "110111" =>
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ram_reg37(7 downto 0) <= data_in(7 downto 0);
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when "111000" =>
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ram_reg38(7 downto 0) <= data_in(7 downto 0);
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when "111001" =>
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ram_reg39(7 downto 0) <= data_in(7 downto 0);
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when "111010" =>
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ram_reg310(7 downto 0) <= data_in(7 downto 0);
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when "111011" =>
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ram_reg311(7 downto 0) <= data_in(7 downto 0);
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when "111100" =>
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ram_reg312(7 downto 0) <= data_in(7 downto 0);
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when "111101" =>
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ram_reg313(7 downto 0) <= data_in(7 downto 0);
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when "111110" =>
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ram_reg314(7 downto 0) <= data_in(7 downto 0);
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when "111111" =>
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ram_reg315(7 downto 0) <= data_in(7 downto 0);
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when others =>
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null;
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end case;
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end if;
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end if;
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end process;
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dat_read : process( addr,
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|
|
ram_reg00, ram_reg01, ram_reg02, ram_reg03,
|
311 |
|
|
ram_reg04, ram_reg05, ram_reg06, ram_reg07,
|
312 |
|
|
ram_reg08, ram_reg09, ram_reg010, ram_reg011,
|
313 |
|
|
ram_reg012, ram_reg013, ram_reg014, ram_reg015,
|
314 |
|
|
ram_reg10, ram_reg11, ram_reg12, ram_reg13,
|
315 |
|
|
ram_reg14, ram_reg15, ram_reg16, ram_reg17,
|
316 |
|
|
ram_reg18, ram_reg19, ram_reg110, ram_reg111,
|
317 |
|
|
ram_reg112, ram_reg113, ram_reg114, ram_reg115,
|
318 |
|
|
ram_reg20, ram_reg21, ram_reg22, ram_reg23,
|
319 |
|
|
ram_reg24, ram_reg25, ram_reg26, ram_reg27,
|
320 |
|
|
ram_reg28, ram_reg29, ram_reg210, ram_reg211,
|
321 |
|
|
ram_reg212, ram_reg213, ram_reg214, ram_reg215,
|
322 |
|
|
ram_reg30, ram_reg31, ram_reg32, ram_reg33,
|
323 |
|
|
ram_reg34, ram_reg35, ram_reg36, ram_reg37,
|
324 |
|
|
ram_reg38, ram_reg39, ram_reg310, ram_reg311,
|
325 |
|
|
ram_reg312, ram_reg313, ram_reg314, ram_reg315
|
326 |
|
|
)
|
327 |
|
|
begin
|
328 |
|
|
case addr is
|
329 |
|
|
when "000000" =>
|
330 |
|
|
data_out <= ram_reg00;
|
331 |
|
|
when "000001" =>
|
332 |
|
|
data_out <= ram_reg01;
|
333 |
|
|
when "000010" =>
|
334 |
|
|
data_out <= ram_reg02;
|
335 |
|
|
when "000011" =>
|
336 |
|
|
data_out <= ram_reg03;
|
337 |
|
|
when "000100" =>
|
338 |
|
|
data_out <= ram_reg04;
|
339 |
|
|
when "000101" =>
|
340 |
|
|
data_out <= ram_reg05;
|
341 |
|
|
when "000110" =>
|
342 |
|
|
data_out <= ram_reg06;
|
343 |
|
|
when "000111" =>
|
344 |
|
|
data_out <= ram_reg07;
|
345 |
|
|
when "001000" =>
|
346 |
|
|
data_out <= ram_reg08;
|
347 |
|
|
when "001001" =>
|
348 |
|
|
data_out <= ram_reg09;
|
349 |
|
|
when "001010" =>
|
350 |
|
|
data_out <= ram_reg010;
|
351 |
|
|
when "001011" =>
|
352 |
|
|
data_out <= ram_reg011;
|
353 |
|
|
when "001100" =>
|
354 |
|
|
data_out <= ram_reg012;
|
355 |
|
|
when "001101" =>
|
356 |
|
|
data_out <= ram_reg013;
|
357 |
|
|
when "001110" =>
|
358 |
|
|
data_out <= ram_reg014;
|
359 |
|
|
when "001111" =>
|
360 |
|
|
data_out <= ram_reg015;
|
361 |
|
|
when "010000" =>
|
362 |
|
|
data_out <= ram_reg10;
|
363 |
|
|
when "010001" =>
|
364 |
|
|
data_out <= ram_reg11;
|
365 |
|
|
when "010010" =>
|
366 |
|
|
data_out <= ram_reg12;
|
367 |
|
|
when "010011" =>
|
368 |
|
|
data_out <= ram_reg13;
|
369 |
|
|
when "010100" =>
|
370 |
|
|
data_out <= ram_reg14;
|
371 |
|
|
when "010101" =>
|
372 |
|
|
data_out <= ram_reg15;
|
373 |
|
|
when "010110" =>
|
374 |
|
|
data_out <= ram_reg16;
|
375 |
|
|
when "010111" =>
|
376 |
|
|
data_out <= ram_reg17;
|
377 |
|
|
when "011000" =>
|
378 |
|
|
data_out <= ram_reg18;
|
379 |
|
|
when "011001" =>
|
380 |
|
|
data_out <= ram_reg19;
|
381 |
|
|
when "011010" =>
|
382 |
|
|
data_out <= ram_reg110;
|
383 |
|
|
when "011011" =>
|
384 |
|
|
data_out <= ram_reg111;
|
385 |
|
|
when "011100" =>
|
386 |
|
|
data_out <= ram_reg112;
|
387 |
|
|
when "011101" =>
|
388 |
|
|
data_out <= ram_reg113;
|
389 |
|
|
when "011110" =>
|
390 |
|
|
data_out <= ram_reg114;
|
391 |
|
|
when "011111" =>
|
392 |
|
|
data_out <= ram_reg115;
|
393 |
|
|
when "100000" =>
|
394 |
|
|
data_out <= ram_reg20;
|
395 |
|
|
when "100001" =>
|
396 |
|
|
data_out <= ram_reg21;
|
397 |
|
|
when "100010" =>
|
398 |
|
|
data_out <= ram_reg22;
|
399 |
|
|
when "100011" =>
|
400 |
|
|
data_out <= ram_reg23;
|
401 |
|
|
when "100100" =>
|
402 |
|
|
data_out <= ram_reg24;
|
403 |
|
|
when "100101" =>
|
404 |
|
|
data_out <= ram_reg25;
|
405 |
|
|
when "100110" =>
|
406 |
|
|
data_out <= ram_reg26;
|
407 |
|
|
when "100111" =>
|
408 |
|
|
data_out <= ram_reg27;
|
409 |
|
|
when "101000" =>
|
410 |
|
|
data_out <= ram_reg28;
|
411 |
|
|
when "101001" =>
|
412 |
|
|
data_out <= ram_reg29;
|
413 |
|
|
when "101010" =>
|
414 |
|
|
data_out <= ram_reg210;
|
415 |
|
|
when "101011" =>
|
416 |
|
|
data_out <= ram_reg211;
|
417 |
|
|
when "101100" =>
|
418 |
|
|
data_out <= ram_reg212;
|
419 |
|
|
when "101101" =>
|
420 |
|
|
data_out <= ram_reg213;
|
421 |
|
|
when "101110" =>
|
422 |
|
|
data_out <= ram_reg214;
|
423 |
|
|
when "101111" =>
|
424 |
|
|
data_out <= ram_reg215;
|
425 |
|
|
when "110000" =>
|
426 |
|
|
data_out <= ram_reg30;
|
427 |
|
|
when "110001" =>
|
428 |
|
|
data_out <= ram_reg31;
|
429 |
|
|
when "110010" =>
|
430 |
|
|
data_out <= ram_reg32;
|
431 |
|
|
when "110011" =>
|
432 |
|
|
data_out <= ram_reg33;
|
433 |
|
|
when "110100" =>
|
434 |
|
|
data_out <= ram_reg34;
|
435 |
|
|
when "110101" =>
|
436 |
|
|
data_out <= ram_reg35;
|
437 |
|
|
when "110110" =>
|
438 |
|
|
data_out <= ram_reg36;
|
439 |
|
|
when "110111" =>
|
440 |
|
|
data_out <= ram_reg37;
|
441 |
|
|
when "111000" =>
|
442 |
|
|
data_out <= ram_reg38;
|
443 |
|
|
when "111001" =>
|
444 |
|
|
data_out <= ram_reg39;
|
445 |
|
|
when "111010" =>
|
446 |
|
|
data_out <= ram_reg310;
|
447 |
|
|
when "111011" =>
|
448 |
|
|
data_out <= ram_reg311;
|
449 |
|
|
when "111100" =>
|
450 |
|
|
data_out <= ram_reg312;
|
451 |
|
|
when "111101" =>
|
452 |
|
|
data_out <= ram_reg313;
|
453 |
|
|
when "111110" =>
|
454 |
|
|
data_out <= ram_reg314;
|
455 |
|
|
when "111111" =>
|
456 |
|
|
data_out <= ram_reg315;
|
457 |
|
|
when others =>
|
458 |
|
|
null;
|
459 |
|
|
end case;
|
460 |
|
|
end process;
|
461 |
|
|
|
462 |
|
|
end;
|
463 |
|
|
|