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dilbert57 |
--===========================================================================--
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--
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-- CPU11 Microprocessor Test Bench 1
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-- Print out "Hello World" on the (non existant) Uart
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--
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--
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-- John Kent 21st October 2002
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--
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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4 |
dilbert57 |
entity my_testbench1 is
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end my_testbench1;
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2 |
dilbert57 |
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-------------------------------------------------------------------------------
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4 |
dilbert57 |
-- Architecture for Testbench 1
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dilbert57 |
-------------------------------------------------------------------------------
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dilbert57 |
architecture behavior of my_testbench1 is
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dilbert57 |
-----------------------------------------------------------------------------
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-- Signals
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-----------------------------------------------------------------------------
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signal uart_irq : Std_Logic;
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signal timer_irq : std_logic;
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-- CPU Interface signals
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signal SysClk : Std_Logic;
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signal cpu_reset : Std_Logic;
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signal cpu_rw : Std_Logic;
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signal cpu_vma : Std_Logic;
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signal cpu_addr : Std_Logic_Vector(15 downto 0);
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signal cpu_data_in : Std_Logic_Vector(7 downto 0);
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signal cpu_data_out: Std_Logic_Vector(7 downto 0);
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signal cpu_alu : Std_Logic_Vector(15 downto 0);
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signal cpu_cc : Std_Logic_Vector(7 downto 0);
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constant width : integer := 8;
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constant memsize : integer := 64;
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type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
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constant rom_data : rom_array :=
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(
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"11001110", "11111111", "11101000", -- E000 - CE E028 RESET LDX #MSG
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"10000110", "00010001", -- E003 - 86 11 LDAA #$11
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"10110111", "10000000", "00000100", -- E005 - B7 8004 STAA UARTCR
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"10110110", "10000000", "00000100", -- E008 - B6 8004 POLL1 LDAA UARTCR
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"10000101", "00000010", -- E00B - 85 02 BITA #TXBE
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-- "00100111", "11111001", -- E00D - 27 F9 BEQ POLL1
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"00100110", "11111001", -- E00D - 26 F9 BNE POLL1
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"10100110", "00000000", -- E00F - A6 00 LDAA 0,X
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"00100111", "00000110", -- E011 - 27 06 BEQ POLL2
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"00001000", -- E013 - 08 INX
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"10110111", "10000000", "00000101", -- E014 - B7 8005 STA UARTDR
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"00100110", "11101111", -- E017 - 26 EF BNE POLL1
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"00001000", "10000000", "00000100", -- E019 - B6 8004 POLL2 LDAA UARTCR
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"10000101", "00000001", -- E01C - 85 01 BITA #RXBF
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"00100111", "11111001", -- E01E - 27 F9 BEQ POLL2
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-- "00100110", "11111001", -- E01E - 26 F9 BEQ POLL2
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"10110110", "10000000", "00000101", -- E020 - B6 8005 LDAA UARTDR
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"00100000", "11100000", "00000000", -- E023 - 7E E000 JMP RESET
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"00000000", "00000000", -- E026 - 00 00 fcb $00,$00
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"01001000", "01100101", "01101100", -- E028 - 48 65 6c MSG FCC "Hel"
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"01101100", "01101111", "00100000", -- E02B - 6c 6f 20 FCC "lo "
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"01010111", "01101111", "01110010", -- E02E - 57 6f 72 FCC "Wor"
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"01101100", "01100100", -- E031 - 6c 64 FCC "ld"
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"00001010", "00001101", "00000000", -- E033 - 0a 0d 00 FCB LF,CR,NULL
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"00000000", "00000000", -- E036 - 00 00 fcb null,null
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"11100000", "00000000", -- E038 - E0 00 fdb $E000 ; Timer irq
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"11100000", "00000000", -- E03A - E0 00 fdb $E000 ; Ext IRQ
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"11100000", "00000000", -- E03C - E0 00 fcb $E000 ; SWI
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"11100000", "00000000" -- E03E - E0 00 fdb $E000 ; Reset
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);
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component cpu11
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port (
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clk: in std_logic;
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rst: in std_logic;
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rw: out std_logic; -- Asynchronous memory interface
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vma: out std_logic;
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address: out std_logic_vector(15 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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irq: in std_logic;
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dilbert57 |
xirq: in std_logic
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dilbert57 |
);
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end component;
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begin
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cpu : cpu11 port map (
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clk => SysClk,
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rst => cpu_reset,
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rw => cpu_rw,
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vma => cpu_vma,
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address => cpu_addr(15 downto 0),
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data_in => cpu_data_in,
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data_out => cpu_data_out,
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irq => uart_irq,
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xirq => timer_irq
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);
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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variable count : integer;
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BEGIN
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cpu_reset <= '0';
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SysClk <= '0';
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uart_irq <= '0';
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timer_irq <= '0';
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for count in 0 to 256 loop
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SysClk <= '0';
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if count = 0 then
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cpu_reset <= '1';
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elsif count = 1 then
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cpu_reset <= '0';
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end if;
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wait for 100 ns;
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SysClk <= '1';
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wait for 100 ns;
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end loop;
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wait; -- will wait forever
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END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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rom : PROCESS( cpu_addr )
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begin
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cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
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end process;
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end behavior; --===================== End of architecture =======================--
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