| 1 |
2 |
dilbert57 |
--===========================================================================--
|
| 2 |
|
|
--
|
| 3 |
|
|
-- CPU11 Microprocessor Test Bench 2
|
| 4 |
|
|
--
|
| 5 |
|
|
-- Subroutine test code.
|
| 6 |
|
|
--
|
| 7 |
|
|
-- John Kent 21st October 2002
|
| 8 |
|
|
--
|
| 9 |
|
|
--
|
| 10 |
|
|
-------------------------------------------------------------------------------
|
| 11 |
|
|
library ieee;
|
| 12 |
|
|
use ieee.std_logic_1164.all;
|
| 13 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
| 14 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
| 15 |
|
|
use ieee.numeric_std.all;
|
| 16 |
|
|
|
| 17 |
4 |
dilbert57 |
entity my_testbench2 is
|
| 18 |
|
|
end my_testbench2;
|
| 19 |
2 |
dilbert57 |
|
| 20 |
|
|
-------------------------------------------------------------------------------
|
| 21 |
4 |
dilbert57 |
-- Architecture for CPU11 Testbench 2
|
| 22 |
2 |
dilbert57 |
-------------------------------------------------------------------------------
|
| 23 |
4 |
dilbert57 |
architecture behavior of my_testbench2 is
|
| 24 |
2 |
dilbert57 |
-----------------------------------------------------------------------------
|
| 25 |
|
|
-- Signals
|
| 26 |
|
|
-----------------------------------------------------------------------------
|
| 27 |
|
|
signal uart_irq : Std_Logic;
|
| 28 |
|
|
signal timer_irq : std_logic;
|
| 29 |
|
|
|
| 30 |
|
|
-- Sequencer Interface signals
|
| 31 |
|
|
signal SysClk : Std_Logic;
|
| 32 |
|
|
signal cpu_reset : Std_Logic;
|
| 33 |
|
|
signal cpu_rw : std_logic;
|
| 34 |
|
|
signal cpu_vma : std_logic;
|
| 35 |
|
|
signal cpu_addr : Std_Logic_Vector(15 downto 0);
|
| 36 |
|
|
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
|
| 37 |
|
|
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
|
| 38 |
|
|
|
| 39 |
|
|
constant width : integer := 8;
|
| 40 |
|
|
constant memsize : integer := 64;
|
| 41 |
|
|
|
| 42 |
|
|
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
|
| 43 |
|
|
|
| 44 |
|
|
constant rom_data : rom_array :=
|
| 45 |
|
|
(
|
| 46 |
|
|
"10001110", "11111111", "11011101", -- FFC0 - 8E FFDD RESET LDS #$FFDD
|
| 47 |
|
|
"11001110", "00010010", "00110100", -- FFC3 - CE 1234 LDX #$1234
|
| 48 |
|
|
"10001101", "00000100", -- FFC6 - 8D 04 BSR SAVGET
|
| 49 |
|
|
"00100111", "11110110", -- FFC8 - 27 F6 REENT BEQ RESET
|
| 50 |
|
|
"00100000", "11111110", -- FFCA - 20 FF BRA *
|
| 51 |
|
|
"11111111", "11111111", "11110000", -- FFCC - FF FFF0 SAVGET STX $FFF0
|
| 52 |
|
|
"11111110", "11111111", "11011001", -- FFCF - FE FFD9 LDX $FFD9
|
| 53 |
|
|
"00110111", -- FFD2 - 37 PSHB
|
| 54 |
|
|
"11100110", "00000001", -- FFD3 - E6 01 LDAB 1,X
|
| 55 |
|
|
"11100001", "00000011", -- FFD5 - E1 03 CMPB 3,X
|
| 56 |
|
|
"00110011", -- FFD7 - 33 PULB
|
| 57 |
|
|
"00111001", -- FFD8 - 39 RTS
|
| 58 |
|
|
"11111111", "11100000", -- FFD9 - FF E0 FDB $FFE0
|
| 59 |
|
|
"01010101", -- FFDB - 55 FCB $55
|
| 60 |
|
|
"11111111", "11001000", -- FFDC - FFC8 FDB REENT
|
| 61 |
|
|
"00100000", "11100000", -- FFDE - 20 E0 BRA RESET
|
| 62 |
|
|
"00000000", "00000000", -- FFE0 - 00 00 fcb $00,$00
|
| 63 |
|
|
"00000000", "00000000", -- FFE2 - 00 00 fcb $00,$00
|
| 64 |
|
|
"00000000", "00000000", -- FFE4 - 00 00 fcb $00,$00
|
| 65 |
|
|
"00000000", "00000000", -- FFE6 - 00 00 fcb $00,$00
|
| 66 |
|
|
"01001000", "01100101", "01101100", -- FFE8 - 48 65 6c MSG FCC "Hel"
|
| 67 |
|
|
"01101100", "01101111", "00100000", -- FFEB - 6c 6f 20 FCC "lo "
|
| 68 |
|
|
"01010111", "01101111", "01110010", -- FFEE - 57 6f 72 FCC "Wor"
|
| 69 |
|
|
"01101100", "01100100", -- FFF1 - 6c 64 FCC "ld"
|
| 70 |
|
|
"00001010", "00001101", "00000000", -- FFF3 - 0a 0d 00 FCB LF,CR,NULL
|
| 71 |
|
|
"00000000", "00000000", -- FFF6 - 00 00 fcb null,null
|
| 72 |
|
|
"11111111", "11000000", -- FFF8 - FF C0 fdb $FFC0 ; Timer irq
|
| 73 |
|
|
"11111111", "11000000", -- FFFA - FF C0 fdb $FFC0 ; Ext IRQ
|
| 74 |
|
|
"11111111", "11000000", -- FFFC - FF C0 fcb $FFC0 ; SWI
|
| 75 |
|
|
"11111111", "11000000" -- FFFE - FF C0 fdb $FFC0 ; Reset
|
| 76 |
|
|
);
|
| 77 |
|
|
|
| 78 |
|
|
component cpu11
|
| 79 |
|
|
port (
|
| 80 |
|
|
data_in: in std_logic_vector(7 downto 0);
|
| 81 |
|
|
data_out: out std_logic_vector(7 downto 0);
|
| 82 |
|
|
address: out std_logic_vector(15 downto 0);
|
| 83 |
|
|
vma: out std_logic;
|
| 84 |
|
|
rw: out std_logic; -- Asynchronous memory interface
|
| 85 |
|
|
rst: in std_logic;
|
| 86 |
|
|
clk: in std_logic;
|
| 87 |
|
|
irq: in std_logic;
|
| 88 |
|
|
xirq: in std_logic
|
| 89 |
|
|
);
|
| 90 |
|
|
end component;
|
| 91 |
|
|
|
| 92 |
|
|
|
| 93 |
|
|
begin
|
| 94 |
|
|
cpu : cpu11 port map (
|
| 95 |
|
|
data_in => cpu_data_in,
|
| 96 |
|
|
data_out => cpu_data_out,
|
| 97 |
|
|
address => cpu_addr(15 downto 0),
|
| 98 |
|
|
vma => cpu_vma,
|
| 99 |
|
|
rw => cpu_rw,
|
| 100 |
|
|
rst => cpu_reset,
|
| 101 |
|
|
clk => SysClk,
|
| 102 |
|
|
irq => uart_irq,
|
| 103 |
|
|
xirq => timer_irq
|
| 104 |
|
|
);
|
| 105 |
|
|
|
| 106 |
|
|
-- *** Test Bench - User Defined Section ***
|
| 107 |
|
|
tb : PROCESS
|
| 108 |
|
|
variable count : integer;
|
| 109 |
|
|
BEGIN
|
| 110 |
|
|
|
| 111 |
|
|
cpu_reset <= '0';
|
| 112 |
|
|
SysClk <= '0';
|
| 113 |
|
|
uart_irq <= '0';
|
| 114 |
|
|
timer_irq <= '0';
|
| 115 |
|
|
|
| 116 |
|
|
for count in 0 to 256 loop
|
| 117 |
|
|
SysClk <= '0';
|
| 118 |
|
|
if count = 0 then
|
| 119 |
|
|
cpu_reset <= '1';
|
| 120 |
|
|
elsif count = 1 then
|
| 121 |
|
|
cpu_reset <= '0';
|
| 122 |
|
|
end if;
|
| 123 |
|
|
wait for 100 ns;
|
| 124 |
|
|
SysClk <= '1';
|
| 125 |
|
|
wait for 100 ns;
|
| 126 |
|
|
end loop;
|
| 127 |
|
|
|
| 128 |
|
|
wait; -- will wait forever
|
| 129 |
|
|
END PROCESS;
|
| 130 |
|
|
-- *** End Test Bench - User Defined Section ***
|
| 131 |
|
|
|
| 132 |
|
|
|
| 133 |
|
|
rom : PROCESS( cpu_addr )
|
| 134 |
|
|
begin
|
| 135 |
|
|
cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
|
| 136 |
|
|
end process;
|
| 137 |
|
|
|
| 138 |
|
|
end behavior; --===================== End of architecture =======================--
|
| 139 |
|
|
|
