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1 4 dilbert57 
--===========================================================================--
2 
--
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-- CPU11 Microprocessor Test Bench 5
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--
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-- CPU11, ROM & RAM test
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--
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-- John Kent 21st October 2002
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--
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--
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-------------------------------------------------------------------------------
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library ieee;
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   use ieee.std_logic_1164.all;
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   use IEEE.STD_LOGIC_ARITH.ALL;
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   use IEEE.STD_LOGIC_UNSIGNED.ALL;
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   use ieee.numeric_std.all;
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entity my_testbench5 is
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end my_testbench5;
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20 
-------------------------------------------------------------------------------
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-- Architecture for CPU11 Testbench 5
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-------------------------------------------------------------------------------
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architecture behavior of my_testbench5 is
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  -----------------------------------------------------------------------------
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  -- Signals
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  -----------------------------------------------------------------------------
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  signal uart_irq    : Std_Logic;
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  signal timer_irq   : std_logic;
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  -- Sequencer Interface signals
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  signal SysClk      : Std_Logic;
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  signal cpu_reset   : Std_Logic;
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  signal cpu_rw      : std_logic;
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  signal cpu_vma     : std_logic;
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  signal cpu_addr    : Std_Logic_Vector(15 downto 0);
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  signal cpu_data_in : Std_Logic_Vector(7 downto 0);
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  signal cpu_data_out: Std_Logic_Vector(7 downto 0);
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  signal rom_data_out: Std_Logic_Vector(7 downto 0);
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  signal ram0_data_out: Std_Logic_Vector(7 downto 0);
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  signal ram0_cs      : std_logic;
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  signal ram1_data_out: Std_Logic_Vector(7 downto 0);
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  signal ram1_cs      : std_logic;
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  signal ram2_data_out: Std_Logic_Vector(7 downto 0);
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  signal ram2_cs      : std_logic;
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  signal ram3_data_out: Std_Logic_Vector(7 downto 0);
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  signal ram3_cs      : std_logic;
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  signal ram4_data_out: Std_Logic_Vector(7 downto 0);
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  signal ram4_cs      : std_logic;
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  signal ram5_data_out: Std_Logic_Vector(7 downto 0);
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  signal ram5_cs      : std_logic;
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  signal ram6_data_out: Std_Logic_Vector(7 downto 0);
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  signal ram6_cs      : std_logic;
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  signal ram7_data_out: Std_Logic_Vector(7 downto 0);
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  signal ram7_cs      : std_logic;
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component cpu11
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  port (
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    data_in:  in        std_logic_vector(7 downto 0);
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         data_out: out std_logic_vector(7 downto 0);
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    address:  out       std_logic_vector(15 downto 0);
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    vma:             out        std_logic;
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    rw:      out        std_logic;              -- Asynchronous memory interface
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    rst:             in std_logic;
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         clk:        in std_logic;
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         irq:      in  std_logic;
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         xirq:     in  std_logic
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  );
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end component;
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component my_ram
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        port (
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         clk       : in  std_logic;
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    rst       : in  std_logic;
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    cs        : in  std_logic;
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    rw        : in  std_logic;
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    addr      : in  std_logic_vector(3 downto 0);
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         data_in   : in  std_logic_vector(7 downto 0);
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         data_out  : out std_logic_vector(7 downto 0)
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         );
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end component;
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component boot_rom
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  port (
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    addr  : in  Std_Logic_Vector(9 downto 0);  -- 1K byte boot rom
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         data  : out Std_Logic_Vector(7 downto 0)
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  );
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end component;
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begin
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cpu : cpu11  port map (
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    data_in   => cpu_data_in,
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         data_out  => cpu_data_out,
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    address   => cpu_addr(15 downto 0),
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    vma       => cpu_vma,
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    rw       => cpu_rw,
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    rst      => cpu_reset,
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         clk         => SysClk,
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         irq       => uart_irq,
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         xirq      => timer_irq
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  );
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sram0 : my_ram port map (
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         clk       => SysClk,
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    rst       => cpu_reset,
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    cs        => ram0_cs,
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    rw        => cpu_rw,
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    addr      => cpu_addr(3 downto 0),
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         data_in   => cpu_data_out,
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         data_out  => ram0_data_out
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         );
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sram1 : my_ram port map (
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         clk       => SysClk,
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    rst       => cpu_reset,
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    cs        => ram1_cs,
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    rw        => cpu_rw,
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    addr      => cpu_addr(3 downto 0),
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         data_in   => cpu_data_out,
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         data_out  => ram1_data_out
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         );
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sram2 : my_ram port map (
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         clk       => SysClk,
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    rst       => cpu_reset,
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    cs        => ram2_cs,
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    rw        => cpu_rw,
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    addr      => cpu_addr(3 downto 0),
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         data_in   => cpu_data_out,
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         data_out  => ram2_data_out
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         );
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sram3 : my_ram port map (
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         clk       => SysClk,
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    rst       => cpu_reset,
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    cs        => ram3_cs,
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    rw        => cpu_rw,
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    addr      => cpu_addr(3 downto 0),
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         data_in   => cpu_data_out,
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         data_out  => ram3_data_out
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         );
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sram4 : my_ram port map (
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         clk       => SysClk,
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    rst       => cpu_reset,
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    cs        => ram4_cs,
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    rw        => cpu_rw,
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    addr      => cpu_addr(3 downto 0),
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         data_in   => cpu_data_out,
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         data_out  => ram4_data_out
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         );
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sram5 : my_ram port map (
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         clk       => SysClk,
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    rst       => cpu_reset,
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    cs        => ram5_cs,
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    rw        => cpu_rw,
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    addr      => cpu_addr(3 downto 0),
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         data_in   => cpu_data_out,
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         data_out  => ram5_data_out
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         );
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sram6 : my_ram port map (
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         clk       => SysClk,
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    rst       => cpu_reset,
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    cs        => ram6_cs,
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    rw        => cpu_rw,
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    addr      => cpu_addr(3 downto 0),
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         data_in   => cpu_data_out,
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         data_out  => ram6_data_out
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         );
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sram7 : my_ram port map (
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         clk       => SysClk,
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    rst       => cpu_reset,
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    cs        => ram7_cs,
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    rw        => cpu_rw,
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    addr      => cpu_addr(3 downto 0),
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         data_in   => cpu_data_out,
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         data_out  => ram7_data_out
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         );
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  rom : boot_rom port map (
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         addr       => cpu_addr(9 downto 0),
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    data       => rom_data_out
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         );
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decode : process( cpu_addr, cpu_vma, rom_data_out,
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                  ram0_data_out, ram1_data_out, ram2_data_out, ram3_data_out,
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                                                ram4_data_out, ram5_data_out, ram6_data_out, ram7_data_out  )
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begin
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   ram0_cs <= '0';
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   ram1_cs <= '0';
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   ram2_cs <= '0';
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   ram3_cs <= '0';
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   ram4_cs <= '0';
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   ram5_cs <= '0';
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   ram6_cs <= '0';
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   ram7_cs <= '0';
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   case cpu_addr(15 downto 13) is
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        when "111" =>
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           cpu_data_in <= rom_data_out;
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   when "101" =>
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           case cpu_addr(6 downto 4 ) is
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                when "000" =>
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             cpu_data_in <= ram0_data_out;
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                  ram0_cs <= cpu_vma;
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                when "001" =>
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             cpu_data_in <= ram1_data_out;
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                  ram1_cs <= cpu_vma;
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                when "010" =>
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             cpu_data_in <= ram2_data_out;
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                  ram2_cs <= cpu_vma;
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                when "011" =>
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             cpu_data_in <= ram3_data_out;
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                  ram3_cs <= cpu_vma;
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                when "100" =>
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             cpu_data_in <= ram4_data_out;
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                  ram4_cs <= cpu_vma;
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                when "101" =>
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             cpu_data_in <= ram5_data_out;
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                  ram5_cs <= cpu_vma;
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                when "110" =>
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             cpu_data_in <= ram6_data_out;
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                  ram6_cs <= cpu_vma;
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                when "111" =>
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             cpu_data_in <= ram7_data_out;
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                  ram7_cs <= cpu_vma;
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      when others =>
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                  null;
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      end case;
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   when others =>
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           cpu_data_in <= "00000000";
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   end case;
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end process;
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  -- *** Test Bench - User Defined Section ***
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   tb : PROCESS
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        variable count : integer;
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   BEGIN
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        cpu_reset <= '0';
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        SysClk <= '0';
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   uart_irq <= '0';
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        timer_irq <= '0';
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                for count in 0 to 256 loop
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                        SysClk <= '0';
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                        if count = 0 then
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                                cpu_reset <= '1';
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                        elsif count = 1 then
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                                cpu_reset <= '0';
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                        end if;
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                        wait for 100 ns;
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                        SysClk <= '1';
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                        wait for 100 ns;
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                end loop;
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      wait; -- will wait forever
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   END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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end behavior; --===================== End of architecture =======================--
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