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dilbert57 |
--===========================================================================--
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--
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-- S Y N T H E Z I A B L E miniUART C O R E
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--
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-- www.OpenCores.Org - January 2000
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-- This core adheres to the GNU public license
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--
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-- Design units : miniUART core for the System68
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--
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-- File name : txunit2.vhd
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--
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-- Purpose : Implements an miniUART device for communication purposes
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-- between the CPU68 processor and the Host computer through
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-- an RS-232 communication protocol.
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--
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-- Dependencies : IEEE.Std_Logic_1164
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--
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--===========================================================================--
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-------------------------------------------------------------------------------
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-- Revision list
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-- Version Author Date Changes
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--
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- 2.0 Ovidiu Lupas 17 April 2000 unnecessary variable removed
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-- olupas@opencores.org
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--
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-- 3.0 John Kent 5 January 2003 added 6850 word format control
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-- 3.1 John Kent 12 January 2003 Rearranged state machine code
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-- 3.2 John Kent 30 March 2003 Revamped State machine
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-- 3.3 John Kent 16 January 2004 Major re-write - added baud rate gen
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--
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-- dilbert57@opencores.org
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--
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-------------------------------------------------------------------------------
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-- Description :
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-------------------------------------------------------------------------------
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-- Entity for the Tx Unit --
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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-------------------------------------------------------------------------------
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-- Transmitter unit
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-------------------------------------------------------------------------------
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entity TxUnit is
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port (
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Clk : in Std_Logic; -- Clock signal
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Reset : in Std_Logic; -- Reset input
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LoadD : in Std_Logic; -- Load transmit data
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DAIn : in Std_Logic_Vector(7 downto 0);
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WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
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BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
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TxClk : in Std_Logic; -- Enable input
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TxDat : out Std_Logic; -- RS-232 data output
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TBE : out Std_Logic ); -- Tx buffer empty
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end; --================== End of entity ==============================--
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-------------------------------------------------------------------------------
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-- Architecture for TxUnit
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-------------------------------------------------------------------------------
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architecture Behaviour of TxUnit is
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type TxStateType is ( TxIdle_State, Start_State, Data_State, Parity_State, Stop_State );
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-----------------------------------------------------------------------------
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-- Signals
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-----------------------------------------------------------------------------
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signal TxClkDel : Std_Logic; -- Delayed Tx Input Clock
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signal TxClkEdge : Std_Logic; -- Tx Input Clock Edge pulse
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signal TxClkCnt : Std_Logic_Vector(5 downto 0); -- Tx Baud Clock Counter
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signal TxBdDel : Std_Logic; -- Delayed Tx Baud Clock
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signal TxBdEdge : Std_Logic; -- Tx Baud Clock Edge pulse
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signal TxBdClk : Std_Logic; -- Tx Baud Clock
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signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer
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signal TBufE : Std_Logic; -- Transmit Buffer Empty
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signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register
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signal TxParity : Std_logic; -- Parity Bit
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signal DataCnt : Std_Logic_Vector(3 downto 0); -- Data Bit Counter
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signal TRegE : Std_Logic; -- Transmit Register empty
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signal TRegEDel : Std_Logic; -- Transmit Register empty
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signal TRegEEdge : Std_Logic;
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signal TxState : TxStateType;
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signal TxDbit : Std_Logic;
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begin
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---------------------------------------------------------------------
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-- Transmit Clock Edge Detection
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-- A falling edge will produce a one clock cycle pulse
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---------------------------------------------------------------------
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txunit_clock_edge : process(Clk, Reset, TxClk, TxClkDel )
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begin
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if Reset = '1' then
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TxClkDel <= TxClk;
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TxClkEdge <= '0';
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elsif Clk'event and Clk = '0' then
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TxClkDel <= TxClk;
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TxClkEdge <= TxClkDel and (not TxClk);
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end if;
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end process;
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---------------------------------------------------------------------
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-- Transmit Clock Divider
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-- Advance the count only on an input clock pulse
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---------------------------------------------------------------------
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txunit_clock_divide : process(Clk, Reset, TxClkEdge, TxClkCnt )
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begin
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if Reset = '1' then
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TxClkCnt <= "000000";
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elsif Clk'event and Clk = '0' then
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if TxClkEdge = '1' then
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TxClkCnt <= TxClkCnt + "000001";
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else
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TxClkCnt <= TxClkCnt;
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end if; -- TxClkEdge
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end if; -- reset / clk
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end process;
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---------------------------------------------------------------------
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-- Receiver Clock Selector
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-- Select output then look for rising edge
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---------------------------------------------------------------------
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txunit_clock_select : process(Clk, Reset, BdFmt, TxClk, TxClkCnt,
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TxBdDel, TxBdEdge )
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begin
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-- BdFmt
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-- 0 0 - Baud Clk divide by 1
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-- 0 1 - Baud Clk divide by 16
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-- 1 0 - Baud Clk divide by 64
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-- 1 1 - reset
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case BdFmt is
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when "00" => -- Div by 1
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TxBdClk <= TxClk;
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when "01" => -- Div by 16
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TxBdClk <= TxClkCnt(3);
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when "10" => -- Div by 64
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TxBdClk <= TxClkCnt(5);
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when others => -- reset
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TxBdClk <= '0';
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end case;
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if Reset = '1' then
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TxBdDel <= TxBdClk;
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TxBdEdge <= '0';
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elsif Clk'event and Clk = '0' then
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TxBdDel <= TxBdClk;
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TxBdEdge <= TxBdClk and (not TxBdDel);
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end if;
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end process;
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---------------------------------------------------------------------
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-- Transmit Buffer Empty Edge
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-- generate a negative edge pulse
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---------------------------------------------------------------------
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txunit_busy : process(Clk, Reset, TRegE, TRegEDel )
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begin
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if Reset = '1' then
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TRegEDel <= '0';
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TRegEEdge <= '0';
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elsif Clk'event and Clk = '0' then
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TRegEDel <= TRegE;
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TRegEEdge <= TregEDel and (not TRegE ); -- falling edge
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end if;
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end process;
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---------------------------------------------------------------------
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-- Transmitter activation process
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---------------------------------------------------------------------
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txunit_write : process(Clk, Reset, LoadD, DAIn, TBufE, TRegEEdge )
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begin
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if Reset = '1' then
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TBufE <= '1';
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TBuff <= "00000000";
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elsif Clk'event and Clk = '0' then
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if LoadD = '1' then
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TBuff <= DAIn;
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TBufE <= '0';
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else
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TBuff <= TBuff;
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if (TBufE = '0') and (TRegEEdge = '1') then
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-- Once the transmitter is started
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-- We can flag the buffer empty again.
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TBufE <= '1';
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else
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TBufE <= TBufE;
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end if;
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end if;
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end if; -- clk / reset
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TBE <= TBufE;
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end process;
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-----------------------------------------------------------------------------
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-- Implements the Tx unit
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-----------------------------------------------------------------------------
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txunit_transmit : process(Reset, Clk, TxState, TxDbit, TBuff, TReg,
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TxBdEdge, TxParity, DataCnt, WdFmt,
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TBufE, TRegE )
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begin
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if Reset = '1' then
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TxDbit <= '1';
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TReg <= "00000000";
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TxParity <= '0';
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DataCnt <= "0000";
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TRegE <= '1';
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TxState <= TxIdle_State;
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elsif Clk'event and Clk = '0' then
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if TxBdEdge = '1' then
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case TxState is
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when TxIdle_State => -- TxIdle_State (also 1st or 2nd Stop bit)
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TxDbit <= '1';
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TReg <= TBuff;
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TxParity <= '0';
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DataCnt <= "0000";
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TRegE <= '1';
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if TBufE = '0' then
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TxState <= Start_State;
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else
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TxState <= TxIdle_State;
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end if;
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when Start_State =>
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TxDbit <= '0'; -- Start bit
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TReg <= TReg;
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TxParity <= '0';
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if WdFmt(2) = '0' then
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DataCnt <= "0110"; -- 7 data + parity
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else
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DataCnt <= "0111"; -- 8 data
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end if;
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TRegE <= '0';
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TxState <= Data_State;
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when Data_State =>
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TxDbit <= TReg(0);
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TReg <= '1' & TReg(7 downto 1);
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TxParity <= TxParity xor TReg(0);
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TRegE <= '0';
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DataCnt <= DataCnt - "0001";
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if DataCnt = "0000" then
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if (WdFmt(2) = '1') and (WdFmt(1) = '0') then
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if WdFmt(0) = '0' then -- 8 data bits
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TxState <= Stop_State; -- 2 stops
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else
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TxState <= TxIdle_State; -- 1 stop
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end if;
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else
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TxState <= Parity_State; -- parity
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end if;
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else
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TxState <= Data_State;
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end if;
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when Parity_State => -- 7/8 data + parity bit
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if WdFmt(0) = '0' then
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TxDbit <= not( TxParity ); -- even parity
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else
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TXDbit <= TxParity; -- odd parity
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end if;
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Treg <= Treg;
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TxParity <= '0';
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TRegE <= '0';
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DataCnt <= "0000";
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if WdFmt(1) = '0' then
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TxState <= Stop_State; -- 2 stops
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else
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TxState <= TxIdle_State; -- 1 stop
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end if;
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when Stop_State => -- first stop bit
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TxDbit <= '1'; -- 2 stop bits
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Treg <= Treg;
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TxParity <= '0';
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DataCnt <= "0000";
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TRegE <= '0';
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TxState <= TxIdle_State;
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when others => -- Undefined
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TxDbit <= TxDbit;
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Treg <= Treg;
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TxParity <= '0';
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DataCnt <= "0000";
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TRegE <= TregE;
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TxState <= TxIdle_State;
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end case; -- TxState
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else -- TxBdEdge
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TxDbit <= TxDbit;
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TReg <= TReg;
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TxParity <= TxParity;
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DataCnt <= DataCnt;
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TRegE <= TRegE;
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TxState <= TxState;
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end if; -- TxBdEdge
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end if; -- clk / reset
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TxDat <= TxDbit;
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end process;
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end Behaviour; --=================== End of architecture ====================--
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