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dilbert57 |
--===========================================================================--
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--
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-- S Y N T H E Z I A B L E miniUART C O R E
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--
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-- www.OpenCores.Org - January 2000
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-- This core adheres to the GNU public license
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--
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-- Design units : miniUART core for the OCRP-1
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--
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-- File name : miniuart.vhd
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--
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-- Purpose : Implements an miniUART device for communication purposes
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-- between the OR1K processor and the Host computer through
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-- an RS-232 communication protocol.
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--
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-- Library : uart_lib.vhd
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--
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-- Dependencies : IEEE.Std_Logic_1164
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--
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-- Simulator : ModelSim PE/PLUS version 4.7b on a Windows95 PC
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--===========================================================================--
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-------------------------------------------------------------------------------
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-- Revision list
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-- Version Author Date Changes
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--
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
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-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
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-- the RSBusCtrl did not process all possible situations
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--
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-- olupas@opencores.org
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--
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-- 3.0 John Kent October 2002 Changed Status bits to match mc6805
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-- Added CTS, RTS, Baud rate control & Software Reset
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-------------------------------------------------------------------------------
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-- Entity for miniUART Unit - 9600 baudrate --
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity miniUART is
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port (
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SysClk : in Std_Logic; -- System Clock
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rst : in Std_Logic; -- Reset input (active high)
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cs : in Std_Logic;
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rw : in Std_Logic;
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RxD : in Std_Logic;
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TxD : out Std_Logic;
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CTS_n : in Std_Logic;
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RTS_n : out Std_Logic;
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Irq : out Std_Logic; -- interrupt
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Addr : in Std_Logic; -- Register Select
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DataIn : in Std_Logic_Vector(7 downto 0); --
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DataOut : out Std_Logic_Vector(7 downto 0)); --
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end entity; --================== End of entity ==============================--
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-------------------------------------------------------------------------------
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-- Architecture for miniUART Controller Unit
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-------------------------------------------------------------------------------
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architecture uart of miniUART is
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-----------------------------------------------------------------------------
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-- Signals
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-----------------------------------------------------------------------------
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signal RxData : Std_Logic_Vector(7 downto 0); --
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signal TxData : Std_Logic_Vector(7 downto 0); --
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signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
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signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
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-- StatReg detailed
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-----------+--------+--------+--------+--------+--------+--------+--------+
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-- Int | PErr | ORErr | FErr | CTS | DCD | TBufE | DRdy |
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-----------+--------+--------+--------+--------+--------+--------+--------+
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signal EnabRx : Std_Logic; -- Enable RX unit
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signal EnabTx : Std_Logic; -- Enable TX unit
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signal DRdy : Std_Logic; -- Receive Data ready
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signal TBufE : Std_Logic; -- Transmit buffer empty
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signal FErr : Std_Logic; -- Frame error
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signal OErr : Std_Logic; -- Output error
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signal Read : Std_Logic; -- Read receive buffer
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signal Load : Std_Logic; -- Load transmit buffer
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signal Int : Std_Logic; -- Interrupt bit
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signal Reset : Std_Logic; -- Reset (Software & Hardware)
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-----------------------------------------------------------------------------
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-- Baud rate Generator
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-----------------------------------------------------------------------------
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component ClkUnit is
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port (
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Clk : in Std_Logic; -- System Clock
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Reset : in Std_Logic; -- Reset input
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EnableRX : out Std_Logic; -- Control signal
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EnableTX : out Std_Logic; -- Control signal
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BaudRate : in Std_Logic_Vector(1 downto 0));
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end component;
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-----------------------------------------------------------------------------
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-- Receive Unit
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-----------------------------------------------------------------------------
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component RxUnit is
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port (
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Clk : in Std_Logic; -- Clock signal
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Reset : in Std_Logic; -- Reset input
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Enable : in Std_Logic; -- Enable input
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RxD : in Std_Logic; -- RS-232 data input
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ReadD : in Std_Logic; -- Read data signal
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FRErr : out Std_Logic; -- Status signal
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ORErr : out Std_Logic; -- Status signal
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DARdy : out Std_Logic; -- Status signal
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DataI : out Std_Logic_Vector(7 downto 0));
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end component;
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-----------------------------------------------------------------------------
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-- Transmitter Unit
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-----------------------------------------------------------------------------
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component TxUnit is
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port (
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Clk : in Std_Logic; -- Clock signal
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Reset : in Std_Logic; -- Reset input
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Enable : in Std_Logic; -- Enable input
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LoadD : in Std_Logic; -- Load transmit data
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TxD : out Std_Logic; -- RS-232 data output
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TBE : out Std_Logic; -- Tx buffer empty
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DataO : in Std_Logic_Vector(7 downto 0));
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end component;
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begin
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-----------------------------------------------------------------------------
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-- Instantiation of internal components
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-----------------------------------------------------------------------------
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ClkDiv : ClkUnit port map (
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Clk => SysClk,
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EnableRx => EnabRX,
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EnableTx => EnabTX,
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BaudRate => CtrlReg(1 downto 0),
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Reset => Reset);
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TxDev : TxUnit port map (
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Clk => SysClk,
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Reset => Reset,
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Enable => EnabTX,
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LoadD => Load,
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TxD => TxD,
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TBE => TBufE,
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DataO => TxData);
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RxDev : RxUnit port map (
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Clk => SysClk,
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Reset => Reset,
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Enable => EnabRX,
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RxD => RxD,
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ReadD => Read,
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FRErr => FErr,
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ORErr => OErr,
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DARdy => DRdy,
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DataI => RxData);
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-----------------------------------------------------------------------------
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-- Implements the controller for Rx&Tx units
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-----------------------------------------------------------------------------
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RSBusCtrl : process(SysClk, Reset, DRdy, TBufE, FErr, OErr, Int, CtrlReg)
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variable StatM : Std_Logic_Vector(7 downto 0);
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begin
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if SysClk'event and SysClk='0' then
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if Reset = '1' then
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StatM := "00000000";
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Int <= '0';
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else
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StatM(0) := DRdy;
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StatM(1) := TBufE;
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StatM(2) := '0'; -- DCD
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StatM(3) := CTS_n;
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StatM(4) := FErr;
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StatM(5) := OErr;
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StatM(6) := '0'; -- Parrity error
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StatM(7) := Int;
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Int <= (CtrlReg(7) and DRdy) or
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((not CtrlReg(6)) and CtrlReg(5) and TBufE);
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end if;
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RTS_n <= CtrlReg(6) and not CtrlReg(5);
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Irq <= Int;
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StatReg <= StatM;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- Combinational section
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-----------------------------------------------------------------------------
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control_strobe: process(SysClk, Reset, cs, rw, Addr, DataIn, CtrlReg )
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begin
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if SysClk'event and SysClk='1' then
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if (reset = '1') then
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CtrlReg <= "00000000";
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Load <= '0';
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Read <= '0';
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else
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if cs = '1' then
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if Addr = '1' then
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CtrlReg <= CtrlReg;
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if rw = '0' then -- write data register
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Load <= '1';
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Read <= '0';
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else -- read Data Register
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Load <= '0';
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Read <= '1';
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end if; -- rw
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else -- read Status Register
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Load <= '0';
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Read <= '0';
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if rw = '0' then -- write data register
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CtrlReg <= DataIn;
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else -- read Data Register
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CtrlReg <= CtrlReg;
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end if; -- rw
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end if; -- Addr
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else -- not selected
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Load <= '0';
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Read <= '0';
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CtrlReg <= CtrlReg;
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end if; -- cs
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end if; -- reset
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end if; -- SysClk
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end process;
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---------------------------------------------------------------
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--
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-- set data output mux
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--
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--------------------------------------------------------------
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data_port: process(Addr, StatReg, RxData, DataIn )
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begin
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TxData <= DataIn;
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if Addr = '1' then
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DataOut <= RxData; -- read data register
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else
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DataOut <= StatReg; -- read status register
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end if; -- Addr
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end process;
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---------------------------------------------------------------
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--
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-- reset may be hardware or software
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--
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---------------------------------------------------------------
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uart_reset: process(CtrlReg, rst )
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begin
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Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
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end process;
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end uart; --===================== End of architecture =======================--
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