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dilbert57 |
--===========================================================================--
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--
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-- CPU68 Microprocessor Test Bench 2
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--
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--
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-- John Kent 21st October 2002
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--
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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entity my_testbench is
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end my_testbench;
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-------------------------------------------------------------------------------
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-- Architecture for memio Controller Unit
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-------------------------------------------------------------------------------
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architecture behavior of my_testbench is
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-----------------------------------------------------------------------------
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-- Signals
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-----------------------------------------------------------------------------
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signal uart_irq : Std_Logic;
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signal timer_irq : std_logic;
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-- Sequencer Interface signals
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signal SysClk : Std_Logic;
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signal cpu_reset : Std_Logic;
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signal cpu_rw : std_logic;
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signal cpu_vma : std_logic;
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signal cpu_addr : Std_Logic_Vector(15 downto 0);
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signal cpu_data_in : Std_Logic_Vector(7 downto 0);
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signal cpu_data_out: Std_Logic_Vector(7 downto 0);
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constant width : integer := 8;
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constant memsize : integer := 64;
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type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
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constant rom_data : rom_array :=
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(
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"10001110", "11111111", "11011101", -- FFC0 - 8E FFDD RESET LDS #$FFDD
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"11001110", "00010010", "00110100", -- FFC3 - CE 1234 LDX #$1234
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"10001101", "00000100", -- FFC6 - 8D 04 BSR SAVGET
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"00100111", "11110110", -- FFC8 - 27 F6 REENT BEQ RESET
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"00100000", "11111110", -- FFCA - 20 FF BRA *
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"11111111", "11111111", "11110000", -- FFCC - FF FFF0 SAVGET STX $FFF0
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"11111110", "11111111", "11011001", -- FFCF - FE FFD9 LDX $FFD9
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"00110111", -- FFD2 - 37 PSHB
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"11100110", "00000001", -- FFD3 - E6 01 LDAB 1,X
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"11100001", "00000011", -- FFD5 - E1 03 CMPB 3,X
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"00110011", -- FFD7 - 33 PULB
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"00111001", -- FFD8 - 39 RTS
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"11111111", "11100000", -- FFD9 - FF E0 FDB $FFE0
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"01010101", -- FFDB - 55 FCB $55
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"11111111", "11001000", -- FFDC - FFC8 FDB REENT
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"00100000", "11100000", -- FFDE - 20 E0 BRA RESET
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"00000000", "00000000", -- FFE0 - 00 00 fcb $00,$00
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"00000000", "00000000", -- FFE2 - 00 00 fcb $00,$00
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"00000000", "00000000", -- FFE4 - 00 00 fcb $00,$00
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"00000000", "00000000", -- FFE6 - 00 00 fcb $00,$00
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"01001000", "01100101", "01101100", -- FFE8 - 48 65 6c MSG FCC "Hel"
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"01101100", "01101111", "00100000", -- FFEB - 6c 6f 20 FCC "lo "
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"01010111", "01101111", "01110010", -- FFEE - 57 6f 72 FCC "Wor"
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"01101100", "01100100", -- FFF1 - 6c 64 FCC "ld"
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"00001010", "00001101", "00000000", -- FFF3 - 0a 0d 00 FCB LF,CR,NULL
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"00000000", "00000000", -- FFF6 - 00 00 fcb null,null
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"11111111", "11000000", -- FFF8 - FF C0 fdb $FFC0 ; Timer irq
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"11111111", "11000000", -- FFFA - FF C0 fdb $FFC0 ; Ext IRQ
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"11111111", "11000000", -- FFFC - FF C0 fcb $FFC0 ; SWI
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"11111111", "11000000" -- FFFE - FF C0 fdb $FFC0 ; Reset
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);
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component cpu68
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port (
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data_in: in std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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address: out std_logic_vector(15 downto 0);
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vma: out std_logic;
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rw: out std_logic; -- Asynchronous memory interface
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rst: in std_logic;
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clk: in std_logic;
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irq: in std_logic;
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nmi: in std_logic
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);
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end component cpu68;
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begin
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cpu : cpu68 port map (
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data_in => cpu_data_in,
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data_out => cpu_data_out,
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address => cpu_addr(15 downto 0),
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vma => cpu_vma,
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rw => cpu_rw,
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rst => cpu_reset,
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clk => SysClk,
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irq => uart_irq,
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nmi => timer_irq
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);
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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variable count : integer;
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BEGIN
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cpu_reset <= '0';
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SysClk <= '0';
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uart_irq <= '0';
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timer_irq <= '0';
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for count in 0 to 256 loop
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SysClk <= '0';
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if count = 0 then
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cpu_reset <= '1';
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elsif count = 1 then
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cpu_reset <= '0';
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end if;
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wait for 100 ns;
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SysClk <= '1';
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wait for 100 ns;
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end loop;
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wait; -- will wait forever
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END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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rom : PROCESS( cpu_addr )
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begin
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cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
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end process;
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end behavior; --===================== End of architecture =======================--
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