OpenCores
URL https://opencores.org/ocsvn/System68/System68/trunk

Subversion Repositories System68

[/] [System68/] [tags/] [arelease/] [vhdl/] [uart_lib.vhd] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 dilbert57
--===========================================================================--
2
--
3
--  S Y N T H E Z I A B L E    miniUART   C O R E
4
--
5
--  www.OpenCores.Org - January 2000
6
--  This core adheres to the GNU public license  
7
--
8
-- Design units   : UART_Def
9
--
10
-- File name      : uart_lib.vhd
11
--
12
-- Purpose        : Implements an miniUART device for communication purposes 
13
--                  between the OR1K processor and the Host computer through
14
--                  an RS-232 communication protocol.
15
--                  
16
-- Library        : uart_lib.vhd
17
--
18
-- Dependencies   : IEEE.Std_Logic_1164
19
--
20
--===========================================================================--
21
-------------------------------------------------------------------------------
22
-- Revision list
23
-- Version   Author                 Date                        Changes
24
--
25
-- 0.1      Ovidiu Lupas     15 January 2000                   New model
26
--        olupas@opencores.org
27
-------------------------------------------------------------------------------
28
-------------------------------------------------------------------------------- 
29
-- package UART_Def
30
-------------------------------------------------------------------------------- 
31
library IEEE;
32
use IEEE.Std_Logic_1164.all;
33
use IEEE.Numeric_Std.all;
34
--**--
35
package UART_Def is
36
      -----------------------------------------------------------------------------
37
      -- Converts unsigned Std_LOGIC_Vector to Integer, leftmost bit is MSB
38
      -- Error message for unknowns (U, X, W, Z, -), converted to 0
39
      -- Verifies whether vector is too long (> 16 bits)
40
      -----------------------------------------------------------------------------
41
      function  ToInteger (
42
         Invector : in  Unsigned(3 downto 0))
43
       return     Integer;
44
end UART_Def; --==================== End of package header ======================--
45
package body UART_Def is
46
  function  ToInteger (
47
       InVector : in Unsigned(3 downto 0))
48
      return  Integer is
49
    variable Result       : Integer         := 0;
50
    constant HeaderMsg   : String          := "To_Integer:";
51
    constant MsgSeverity : Severity_Level  := Warning;
52
  begin
53
    for i in 0 to 3 loop
54
      if (InVector(i) = '1') then
55
         Result := Result + (2**I);
56
      end if;
57
    end loop;
58
    return Result;
59
  end ToInteger;
60
end UART_Def; --================ End of package body ================--
61
 
62
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.