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[/] [System68/] [trunk/] [vhdl/] [miniUART3.vhd] - Blame information for rev 8

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--===========================================================================--
--
--  S Y N T H E Z I A B L E    miniUART   C O R E
--
--  www.OpenCores.Org - January 2000
--  This core adheres to the GNU public license  
--
-- Design units   : miniUART core for the System68
--
-- File name      : miniuart2.vhd
--
-- Purpose        : Implements an miniUART device for communication purposes 
--                  between the CPU68 processor and the Host computer through
--                  an RS-232 communication protocol.
--                  
-- Dependencies   : ieee.std_logic_1164
--                  ieee.numeric_std
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version   Author                 Date           Changes
--
-- 0.1      Ovidiu Lupas     15 January 2000       New model
-- 1.0      Ovidiu Lupas     January  2000         Synthesis optimizations
-- 2.0      Ovidiu Lupas     April    2000         Bugs removed - RSBusCtrl
--          the RSBusCtrl did not process all possible situations
--
--        olupas@opencores.org
--
-- 3.0      John Kent        October  2002         Changed Status bits to match mc6805
--                                                 Added CTS, RTS, Baud rate control
--                                                 & Software Reset
-- 3.1      John Kent        5 January 2003        Added Word Format control a'la mc6850
-- 3.2      John Kent        19 July 2003          Latched Data input to UART
-- 3.3      John Kent        16 January 2004       Integrated clkunit in rxunit & txunit
--                                                 Now has external TX 7 RX Baud Clock
--                                                 inputs like the MC6850... 
--                                                 also supports x1 clock and DCD. 
--
--        dilbert57@opencores.org
--
-------------------------------------------------------------------------------
-- Entity for miniUART Unit - 9600 baudrate                                  --
-------------------------------------------------------------------------------
library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
 
entity miniUART is
  port (
     --
          -- CPU signals
          --
     clk      : in  Std_Logic;  -- System Clock
     rst      : in  Std_Logic;  -- Reset input (active high)
     cs       : in  Std_Logic;  -- miniUART Chip Select
     rw       : in  Std_Logic;  -- Read / Not Write
     irq      : out Std_Logic;  -- Interrupt
     Addr     : in  Std_Logic;  -- Register Select
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
     DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
     --
          -- Uart Signals
          --
     RxC      : in  Std_Logic;  -- Receive Baud Clock
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
     RxD      : in  Std_Logic;  -- Receive Data
     TxD      : out Std_Logic;  -- Transmit Data
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
     CTS_n    : in  Std_Logic;  -- Clear To Send
     RTS_n    : out Std_Logic );  -- Request To send
end; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for miniUART Controller Unit
-------------------------------------------------------------------------------
architecture uart of miniUART is
  -----------------------------------------------------------------------------
  -- Signals
  -----------------------------------------------------------------------------
  signal RxData : Std_Logic_Vector(7 downto 0); -- 
  signal TxData : Std_Logic_Vector(7 downto 0); -- 
  signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
  --             StatReg detailed 
  -----------+--------+--------+--------+--------+--------+--------+--------+
  --  Irq    | PErr   | ORErr  | FErr   | CTS    | DCD    | TBufE  | DRdy   |
  -----------+--------+--------+--------+--------+--------+--------+--------+
  signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
  --             CtrlReg detailed 
  -----------+--------+--------+--------+--------+--------+--------+--------+
  --  RxIEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
  -----------+--------+--------+--------+--------+--------+--------+--------+
  -- RxIEnb
  -- 0       - Rx Interrupt disabled
  -- 1       - Rx Interrupt enabled
  -- TxCtl
  -- 0 1     - Tx Interrupt Enable
  -- 1 0     - RTS high
  -- WdFmt
  -- 0 0 0   - 7 data, even parity, 2 stop
  -- 0 0 1   - 7 data, odd  parity, 2 stop
  -- 0 1 0   - 7 data, even parity, 1 stop
  -- 0 1 1   - 7 data, odd  parity, 1 stop
  -- 1 0 0   - 8 data, no   parity, 2 stop
  -- 1 0 1   - 8 data, no   parity, 1 stop
  -- 1 1 0   - 8 data, even parity, 1 stop
  -- 1 1 1   - 8 data, odd  parity, 1 stop
  -- BdCtl
  -- 0 0     - Baud Clk divide by 1
  -- 0 1     - Baud Clk divide by 16
  -- 1 0     - Baud Clk divide by 64
  -- 1 1     - reset
 
  signal TxDbit   : Std_Logic;  -- Transmit data bit
  signal DRdy     : Std_Logic;  -- Receive Data ready
  signal TBufE    : Std_Logic;  -- Transmit buffer empty
  signal FErr     : Std_Logic;  -- Frame error
  signal OErr     : Std_Logic;  -- Output error
  signal PErr     : Std_Logic;  -- Parity Error
  signal TxIEnb   : Std_Logic;  -- Transmit interrupt enable
  signal Read     : Std_Logic;  -- Read receive buffer
  signal Load     : Std_Logic;  -- Load transmit buffer
  signal ReadCS   : Std_Logic;  -- Read Status register
  signal LoadCS   : Std_Logic;  -- Load Control register
  signal Reset    : Std_Logic;  -- Reset (Software & Hardware)
  signal RxRst    : Std_Logic;  -- Receive Reset (Software & Hardware)
  signal TxRst    : Std_Logic;  -- Transmit Reset (Software & Hardware)
  signal DCDDel   : Std_Logic;  -- Delayed DCD_n
  signal DCDEdge  : Std_Logic;  -- Rising DCD_N Edge Pulse
  signal DCDState : Std_Logic;  -- DCD Reset sequencer
  signal DCDInt   : Std_Logic;  -- DCD Interrupt
 
  -----------------------------------------------------------------------------
  -- Receive Unit
  -----------------------------------------------------------------------------
  component RxUnit
  port (
     Clk     : in  Std_Logic;  -- Clock signal
     Reset   : in  Std_Logic;  -- Reset input
     ReadD   : in  Std_Logic;  -- Read data signal
     WdFmt   : in  Std_Logic_Vector(2 downto 0); -- word format
     BdFmt   : in  Std_Logic_Vector(1 downto 0); -- baud format
     RxClk   : in  Std_Logic;  -- RS-232 clock input
     RxDat   : in  Std_Logic;  -- RS-232 data input
     FRErr   : out Std_Logic;  -- Status signal
     ORErr   : out Std_Logic;  -- Status signal
          PAErr   : out Std_logic;  -- Status signal
     DARdy   : out Std_Logic;  -- Status signal
     DAOut   : out Std_Logic_Vector(7 downto 0));
  end component;
  -----------------------------------------------------------------------------
  -- Transmitter Unit
  -----------------------------------------------------------------------------
  component TxUnit
  port (
     Clk    : in  Std_Logic;  -- Clock signal
     Reset  : in  Std_Logic;  -- Reset input
     LoadD  : in  Std_Logic;  -- Load transmit data
     DAIn   : in  Std_Logic_Vector(7 downto 0);
     WdFmt  : in  Std_Logic_Vector(2 downto 0); -- word format
     BdFmt  : in  Std_Logic_Vector(1 downto 0); -- baud format
     TxClk  : in  Std_Logic;  -- Enable input
     TxDat  : out Std_Logic;  -- RS-232 data output
     TBE    : out Std_Logic );  -- Tx buffer empty
  end component;
begin
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
 
  RxDev   : RxUnit  port map (
                Clk      => clk,
                                         Reset    => RxRst,
                                         ReadD    => Read,
                                         WdFmt    => CtrlReg(4 downto 2),
                                         BdFmt    => CtrlReg(1 downto 0),
                                         RxClk    => RxC,
                                         RxDat    => RxD,
                                         FRErr    => FErr,
                                         ORErr    => OErr,
                                         PAErr    => PErr,
                                         DARdy    => DRdy,
                                         DAOut    => RxData
                                         );
 
 
  TxDev   : TxUnit  port map (
                Clk      => clk,
                                         Reset    => TxRst,
                                         LoadD    => Load,
                                         DAIn     => TxData,
                                         WdFmt    => CtrlReg(4 downto 2),
                                         BdFmt    => CtrlReg(1 downto 0),
                                         TxClk    => TxC,
                                         TxDat    => TxDbit,
                                         TBE      => TBufE
                                         );
 
  -----------------------------------------------------------------------------
  -- Implements the controller for Rx&Tx units
  -----------------------------------------------------------------------------
miniUart_Status : process(clk, Reset, CtrlReg, TxIEnb,
                          DRdy, TBufE, DCD_n, CTS_n, DCDInt,
                          FErr, OErr,  PErr )
variable Int : Std_Logic;
  begin
    if Reset = '1' then
            Int     := '0';
       StatReg <= "00000000";
                 irq     <= '0';
    elsif clk'event and clk='0' then
                 Int        := (CtrlReg(7) and DRdy)   or
                               (CtrlReg(7) and DCDInt) or
                               (TxIEnb     and TBufE);
       StatReg(0) <= DRdy;  -- Receive Data Ready
       StatReg(1) <= TBufE and (not CTS_n); -- Transmit Buffer Empty
            StatReg(2) <= DCDInt; -- Data Carrier Detect
                 StatReg(3) <= CTS_n; -- Clear To Send
       StatReg(4) <= FErr;  -- Framing error
       StatReg(5) <= OErr;  -- Overrun error
       StatReg(6) <= PErr;  -- Parity error
                 StatReg(7) <= Int;
                 irq        <= Int;
    end if;
  end process;
 
 
-----------------------------------------------------------------------------
-- Transmit control
-----------------------------------------------------------------------------
 
miniUart_TxControl : process( CtrlReg, TxDbit )
begin
    case CtrlReg(6 downto 5) is
         when "00" => -- Disable TX Interrupts, Assert RTS
           RTS_n  <= '0';
                TxIEnb <= '0';
                TxD    <= TxDbit;
    when "01" => -- Enable TX interrupts, Assert RTS
           RTS_n  <= '0';
                TxIEnb <= '1';
                TxD    <= TxDbit;
    when "10" => -- Disable Tx Interrupts, Clear RTS
           RTS_n  <= '1';
                TxIEnb <= '0';
                TxD    <= TxDbit;
    when "11" => -- Disable Tx interrupts, Assert RTS, send break
           RTS_n  <= '0';
                TxIEnb <= '0';
                TxD    <= '0';
    when others =>
           RTS_n  <= '0';
                TxIEnb <= '0';
                TxD    <= TxDbit;
         end case;
end process;
 
-----------------------------------------------------------------------------
-- Write to control register
-----------------------------------------------------------------------------
 
miniUart_Control:  process(clk, Reset, cs, rw, Addr, DataIn, CtrlReg, TxData )
begin
  if (reset = '1') then
                 TxData  <= "00000000";
                 Load    <= '0';
                 Read    <= '0';
            CtrlReg <= "00000000";
                 LoadCS  <= '0';
                 ReadCS <= '0';
        elsif clk'event and clk='0' then
            if cs = '1' then
              if Addr = '1' then        -- Data Register
                     if rw = '0' then   -- write data register
             TxData <= DataIn;
                  Load   <= '1';
                       Read   <= '0';
                else               -- read Data Register
             TxData <= TxData;
                  Load   <= '0';
             Read   <= '1';
                          end if; -- rw
                     CtrlReg <= CtrlReg;
                          LoadCS  <= '0';
                          ReadCS         <= '0';
              else                                        -- Control / Status register
           TxData <= TxData;
                Load   <= '0';
                     Read   <= '0';
                     if rw = '0' then   -- write control register
                            CtrlReg <= DataIn;
                                 LoadCS  <= '1';
                                 ReadCS <= '0';
                else               -- read status Register
                       CtrlReg <= CtrlReg;
                                 LoadCS  <= '0';
                                 ReadCS <= '1';
                          end if; -- rw
                   end if; -- Addr
            else                   -- not selected
         TxData  <= TxData;
              Load    <= '0';
                   Read    <= '0';
                        CtrlReg <= CtrlReg;
                        LoadCS  <= '0';
                        ReadCS  <= '0';
 
            end if;  -- cs
   end if; -- clk / reset
end process;
 
---------------------------------------------------------------
--
-- set data output mux
--
--------------------------------------------------------------
 
miniUart_data_read: process(Addr, StatReg, RxData)
begin
          if Addr = '1' then
                 DataOut <= RxData;    -- read data register
          else
                 DataOut <= StatReg;   -- read status register
          end if; -- Addr
end process;
 
 
---------------------------------------------------------------
--
-- Data Carrier Detect Edge rising edge detect
--
---------------------------------------------------------------
miniUart_DCD_edge : process( reset, clk, DCD_n, DCDDel  )
begin
   if reset = '1' then
           DCDEdge <= '0';
                DCDDel  <= '0';
   elsif clk'event and clk = '0' then
           DCDDel <= DCD_n;
                DCDEdge <= DCD_n and (not DCDDel);
   end if;
end process;
 
 
---------------------------------------------------------------
--
-- Data Carrier Detect Interrupt
--
---------------------------------------------------------------
miniUart_DCD_int : process( reset, clk, DCDEdge, DCDState, Read, ReadCS, DCDInt )
begin
   if reset = '1' then
           DCDInt   <= '0';
                DCDState <= '0';
   elsif clk'event and clk = '0' then
                if DCDEdge = '1' then
                   DCDInt   <= '1';
                        DCDState <= '0';
      elsif DCDState    = '0' then
                     -- To reset DCD interrupt, First read status
                          if (ReadCS <= '1') and (DCDInt = '1') then
                             DCDState <= '1';
           else
                             DCDState <= '0';
           end if;
                     DCDInt <= DCDInt;
      else      -- DCDstate = '1'
                     -- Then read the data register
                          if Read <= '1' then
                             DCDState <= '0';
                                  DCDInt <= '0';
           else
                             DCDState <= DCDState;
                                  DCDInt   <= DCDInt;
           end if;
      end if; -- DCDState
   end if; -- clk / reset
end process;
 
---------------------------------------------------------------
--
-- reset may be hardware or software
--
---------------------------------------------------------------
 
miniUart_reset: process(rst, CtrlReg, Reset, DCD_n )
begin
          Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
          TxRst <= Reset;
          RxRst <= Reset or DCD_n;
end process;
 
end; --===================== End of architecture =======================--
 

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[/] [System68/] [trunk/] [vhdl/] [miniUART3.vhd] - Blame information for rev 8

Line No.	Rev	Author	Line
1	6	dilbert57	`--===========================================================================--`
2			`--`
3			`-- S Y N T H E Z I A B L E miniUART C O R E`
4			`--`
5			`-- www.OpenCores.Org - January 2000`
6			`-- This core adheres to the GNU public license`
7			`--`
8			`-- Design units : miniUART core for the System68`
9			`--`
10			`-- File name : miniuart2.vhd`
11			`--`
12			`-- Purpose : Implements an miniUART device for communication purposes`
13			`-- between the CPU68 processor and the Host computer through`
14			`-- an RS-232 communication protocol.`
15			`--`
16			`-- Dependencies : ieee.std_logic_1164`
17			`-- ieee.numeric_std`
18			`--`
19			`--===========================================================================--`
20			`-------------------------------------------------------------------------------`
21			`-- Revision list`
22			`-- Version Author Date Changes`
23			`--`
24			`-- 0.1 Ovidiu Lupas 15 January 2000 New model`
25			`-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations`
26			`-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl`
27			`-- the RSBusCtrl did not process all possible situations`
28			`--`
29			`-- olupas@opencores.org`
30			`--`
31			`-- 3.0 John Kent October 2002 Changed Status bits to match mc6805`
32			`-- Added CTS, RTS, Baud rate control`
33			`-- & Software Reset`
34			`-- 3.1 John Kent 5 January 2003 Added Word Format control a'la mc6850`
35			`-- 3.2 John Kent 19 July 2003 Latched Data input to UART`
36			`-- 3.3 John Kent 16 January 2004 Integrated clkunit in rxunit & txunit`
37			`-- Now has external TX 7 RX Baud Clock`
38			`-- inputs like the MC6850...`
39			`-- also supports x1 clock and DCD.`
40			`--`
41			`-- dilbert57@opencores.org`
42			`--`
43			`-------------------------------------------------------------------------------`
44			`-- Entity for miniUART Unit - 9600 baudrate --`
45			`-------------------------------------------------------------------------------`
46			`library ieee;`
47			`use ieee.std_logic_1164.all;`
48			`use ieee.numeric_std.all;`
49
50			`entity miniUART is`
51			`port (`
52			`--`
53			`-- CPU signals`
54			`--`
55			`clk : in Std_Logic; -- System Clock`
56			`rst : in Std_Logic; -- Reset input (active high)`
57			`cs : in Std_Logic; -- miniUART Chip Select`
58			`rw : in Std_Logic; -- Read / Not Write`
59			`irq : out Std_Logic; -- Interrupt`
60			`Addr : in Std_Logic; -- Register Select`
61			`DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In`
62			`DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out`
63			`--`
64			`-- Uart Signals`
65			`--`
66			`RxC : in Std_Logic; -- Receive Baud Clock`
67			`TxC : in Std_Logic; -- Transmit Baud Clock`
68			`RxD : in Std_Logic; -- Receive Data`
69			`TxD : out Std_Logic; -- Transmit Data`
70			`DCD_n : in Std_Logic; -- Data Carrier Detect`
71			`CTS_n : in Std_Logic; -- Clear To Send`
72			`RTS_n : out Std_Logic ); -- Request To send`
73			`end; --================== End of entity ==============================--`
74			`-------------------------------------------------------------------------------`
75			`-- Architecture for miniUART Controller Unit`
76			`-------------------------------------------------------------------------------`
77			`architecture uart of miniUART is`
78			`-----------------------------------------------------------------------------`
79			`-- Signals`
80			`-----------------------------------------------------------------------------`
81			`signal RxData : Std_Logic_Vector(7 downto 0); --`
82			`signal TxData : Std_Logic_Vector(7 downto 0); --`
83			`signal StatReg : Std_Logic_Vector(7 downto 0); -- status register`
84			`-- StatReg detailed`
85			`-----------+--------+--------+--------+--------+--------+--------+--------+`
86			`-- Irq \| PErr \| ORErr \| FErr \| CTS \| DCD \| TBufE \| DRdy \|`
87			`-----------+--------+--------+--------+--------+--------+--------+--------+`
88			`signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register`
89			`-- CtrlReg detailed`
90			`-----------+--------+--------+--------+--------+--------+--------+--------+`
91			`-- RxIEnb \|TxCtl(1)\|TxCtl(0)\|WdFmt(2)\|WdFmt(1)\|WdFmt(0)\|BdCtl(1)\|BdCtl(0)\|`
92			`-----------+--------+--------+--------+--------+--------+--------+--------+`
93			`-- RxIEnb`
94			`-- 0 - Rx Interrupt disabled`
95			`-- 1 - Rx Interrupt enabled`
96			`-- TxCtl`
97			`-- 0 1 - Tx Interrupt Enable`
98			`-- 1 0 - RTS high`
99			`-- WdFmt`
100			`-- 0 0 0 - 7 data, even parity, 2 stop`
101			`-- 0 0 1 - 7 data, odd parity, 2 stop`
102			`-- 0 1 0 - 7 data, even parity, 1 stop`
103			`-- 0 1 1 - 7 data, odd parity, 1 stop`
104			`-- 1 0 0 - 8 data, no parity, 2 stop`
105			`-- 1 0 1 - 8 data, no parity, 1 stop`
106			`-- 1 1 0 - 8 data, even parity, 1 stop`
107			`-- 1 1 1 - 8 data, odd parity, 1 stop`
108			`-- BdCtl`
109			`-- 0 0 - Baud Clk divide by 1`
110			`-- 0 1 - Baud Clk divide by 16`
111			`-- 1 0 - Baud Clk divide by 64`
112			`-- 1 1 - reset`
113
114			`signal TxDbit : Std_Logic; -- Transmit data bit`
115			`signal DRdy : Std_Logic; -- Receive Data ready`
116			`signal TBufE : Std_Logic; -- Transmit buffer empty`
117			`signal FErr : Std_Logic; -- Frame error`
118			`signal OErr : Std_Logic; -- Output error`
119			`signal PErr : Std_Logic; -- Parity Error`
120			`signal TxIEnb : Std_Logic; -- Transmit interrupt enable`
121			`signal Read : Std_Logic; -- Read receive buffer`
122			`signal Load : Std_Logic; -- Load transmit buffer`
123			`signal ReadCS : Std_Logic; -- Read Status register`
124			`signal LoadCS : Std_Logic; -- Load Control register`
125			`signal Reset : Std_Logic; -- Reset (Software & Hardware)`
126			`signal RxRst : Std_Logic; -- Receive Reset (Software & Hardware)`
127			`signal TxRst : Std_Logic; -- Transmit Reset (Software & Hardware)`
128			`signal DCDDel : Std_Logic; -- Delayed DCD_n`
129			`signal DCDEdge : Std_Logic; -- Rising DCD_N Edge Pulse`
130			`signal DCDState : Std_Logic; -- DCD Reset sequencer`
131			`signal DCDInt : Std_Logic; -- DCD Interrupt`
132
133			`-----------------------------------------------------------------------------`
134			`-- Receive Unit`
135			`-----------------------------------------------------------------------------`
136			`component RxUnit`
137			`port (`
138			`Clk : in Std_Logic; -- Clock signal`
139			`Reset : in Std_Logic; -- Reset input`
140			`ReadD : in Std_Logic; -- Read data signal`
141			`WdFmt : in Std_Logic_Vector(2 downto 0); -- word format`
142			`BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format`
143			`RxClk : in Std_Logic; -- RS-232 clock input`
144			`RxDat : in Std_Logic; -- RS-232 data input`
145			`FRErr : out Std_Logic; -- Status signal`
146			`ORErr : out Std_Logic; -- Status signal`
147			`PAErr : out Std_logic; -- Status signal`
148			`DARdy : out Std_Logic; -- Status signal`
149			`DAOut : out Std_Logic_Vector(7 downto 0));`
150			`end component;`
151			`-----------------------------------------------------------------------------`
152			`-- Transmitter Unit`
153			`-----------------------------------------------------------------------------`
154			`component TxUnit`
155			`port (`
156			`Clk : in Std_Logic; -- Clock signal`
157			`Reset : in Std_Logic; -- Reset input`
158			`LoadD : in Std_Logic; -- Load transmit data`
159			`DAIn : in Std_Logic_Vector(7 downto 0);`
160			`WdFmt : in Std_Logic_Vector(2 downto 0); -- word format`
161			`BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format`
162			`TxClk : in Std_Logic; -- Enable input`
163			`TxDat : out Std_Logic; -- RS-232 data output`
164			`TBE : out Std_Logic ); -- Tx buffer empty`
165			`end component;`
166			`begin`
167			`-----------------------------------------------------------------------------`
168			`-- Instantiation of internal components`
169			`-----------------------------------------------------------------------------`
170
171			`RxDev : RxUnit port map (`
172			`Clk => clk,`
173			`Reset => RxRst,`
174			`ReadD => Read,`
175			`WdFmt => CtrlReg(4 downto 2),`
176			`BdFmt => CtrlReg(1 downto 0),`
177			`RxClk => RxC,`
178			`RxDat => RxD,`
179			`FRErr => FErr,`
180			`ORErr => OErr,`
181			`PAErr => PErr,`
182			`DARdy => DRdy,`
183			`DAOut => RxData`
184			`);`
185
186
187			`TxDev : TxUnit port map (`
188			`Clk => clk,`
189			`Reset => TxRst,`
190			`LoadD => Load,`
191			`DAIn => TxData,`
192			`WdFmt => CtrlReg(4 downto 2),`
193			`BdFmt => CtrlReg(1 downto 0),`
194			`TxClk => TxC,`
195			`TxDat => TxDbit,`
196			`TBE => TBufE`
197			`);`
198
199			`-----------------------------------------------------------------------------`
200			`-- Implements the controller for Rx&Tx units`
201			`-----------------------------------------------------------------------------`
202			`miniUart_Status : process(clk, Reset, CtrlReg, TxIEnb,`
203			`DRdy, TBufE, DCD_n, CTS_n, DCDInt,`
204			`FErr, OErr, PErr )`
205			`variable Int : Std_Logic;`
206			`begin`
207			`if Reset = '1' then`
208			`Int := '0';`
209			`StatReg <= "00000000";`
210			`irq <= '0';`
211			`elsif clk'event and clk='0' then`
212			`Int := (CtrlReg(7) and DRdy) or`
213			`(CtrlReg(7) and DCDInt) or`
214			`(TxIEnb and TBufE);`
215			`StatReg(0) <= DRdy; -- Receive Data Ready`
216			`StatReg(1) <= TBufE and (not CTS_n); -- Transmit Buffer Empty`
217			`StatReg(2) <= DCDInt; -- Data Carrier Detect`
218			`StatReg(3) <= CTS_n; -- Clear To Send`
219			`StatReg(4) <= FErr; -- Framing error`
220			`StatReg(5) <= OErr; -- Overrun error`
221			`StatReg(6) <= PErr; -- Parity error`
222			`StatReg(7) <= Int;`
223			`irq <= Int;`
224			`end if;`
225			`end process;`
226
227
228			`-----------------------------------------------------------------------------`
229			`-- Transmit control`
230			`-----------------------------------------------------------------------------`
231
232			`miniUart_TxControl : process( CtrlReg, TxDbit )`
233			`begin`
234			`case CtrlReg(6 downto 5) is`
235			`when "00" => -- Disable TX Interrupts, Assert RTS`
236			`RTS_n <= '0';`
237			`TxIEnb <= '0';`
238			`TxD <= TxDbit;`
239			`when "01" => -- Enable TX interrupts, Assert RTS`
240			`RTS_n <= '0';`
241			`TxIEnb <= '1';`
242			`TxD <= TxDbit;`
243			`when "10" => -- Disable Tx Interrupts, Clear RTS`
244			`RTS_n <= '1';`
245			`TxIEnb <= '0';`
246			`TxD <= TxDbit;`
247			`when "11" => -- Disable Tx interrupts, Assert RTS, send break`
248			`RTS_n <= '0';`
249			`TxIEnb <= '0';`
250			`TxD <= '0';`
251			`when others =>`
252			`RTS_n <= '0';`
253			`TxIEnb <= '0';`
254			`TxD <= TxDbit;`
255			`end case;`
256			`end process;`
257
258			`-----------------------------------------------------------------------------`
259			`-- Write to control register`
260			`-----------------------------------------------------------------------------`
261
262			`miniUart_Control: process(clk, Reset, cs, rw, Addr, DataIn, CtrlReg, TxData )`
263			`begin`
264			`if (reset = '1') then`
265			`TxData <= "00000000";`
266			`Load <= '0';`
267			`Read <= '0';`
268			`CtrlReg <= "00000000";`
269			`LoadCS <= '0';`
270			`ReadCS <= '0';`
271			`elsif clk'event and clk='0' then`
272			`if cs = '1' then`
273			`if Addr = '1' then -- Data Register`
274			`if rw = '0' then -- write data register`
275			`TxData <= DataIn;`
276			`Load <= '1';`
277			`Read <= '0';`
278			`else -- read Data Register`
279			`TxData <= TxData;`
280			`Load <= '0';`
281			`Read <= '1';`
282			`end if; -- rw`
283			`CtrlReg <= CtrlReg;`
284			`LoadCS <= '0';`
285			`ReadCS <= '0';`
286			`else -- Control / Status register`
287			`TxData <= TxData;`
288			`Load <= '0';`
289			`Read <= '0';`
290			`if rw = '0' then -- write control register`
291			`CtrlReg <= DataIn;`
292			`LoadCS <= '1';`
293			`ReadCS <= '0';`
294			`else -- read status Register`
295			`CtrlReg <= CtrlReg;`
296			`LoadCS <= '0';`
297			`ReadCS <= '1';`
298			`end if; -- rw`
299			`end if; -- Addr`
300			`else -- not selected`
301			`TxData <= TxData;`
302			`Load <= '0';`
303			`Read <= '0';`
304			`CtrlReg <= CtrlReg;`
305			`LoadCS <= '0';`
306			`ReadCS <= '0';`
307
308			`end if; -- cs`
309			`end if; -- clk / reset`
310			`end process;`
311
312			`---------------------------------------------------------------`
313			`--`
314			`-- set data output mux`
315			`--`
316			`--------------------------------------------------------------`
317
318			`miniUart_data_read: process(Addr, StatReg, RxData)`
319			`begin`
320			`if Addr = '1' then`
321			`DataOut <= RxData; -- read data register`
322			`else`
323			`DataOut <= StatReg; -- read status register`
324			`end if; -- Addr`
325			`end process;`
326
327
328			`---------------------------------------------------------------`
329			`--`
330			`-- Data Carrier Detect Edge rising edge detect`
331			`--`
332			`---------------------------------------------------------------`
333			`miniUart_DCD_edge : process( reset, clk, DCD_n, DCDDel )`
334			`begin`
335			`if reset = '1' then`
336			`DCDEdge <= '0';`
337			`DCDDel <= '0';`
338			`elsif clk'event and clk = '0' then`
339			`DCDDel <= DCD_n;`
340			`DCDEdge <= DCD_n and (not DCDDel);`
341			`end if;`
342			`end process;`
343
344
345			`---------------------------------------------------------------`
346			`--`
347			`-- Data Carrier Detect Interrupt`
348			`--`
349			`---------------------------------------------------------------`
350			`miniUart_DCD_int : process( reset, clk, DCDEdge, DCDState, Read, ReadCS, DCDInt )`
351			`begin`
352			`if reset = '1' then`
353			`DCDInt <= '0';`
354			`DCDState <= '0';`
355			`elsif clk'event and clk = '0' then`
356			`if DCDEdge = '1' then`
357			`DCDInt <= '1';`
358			`DCDState <= '0';`
359			`elsif DCDState = '0' then`
360			`-- To reset DCD interrupt, First read status`
361			`if (ReadCS <= '1') and (DCDInt = '1') then`
362			`DCDState <= '1';`
363			`else`
364			`DCDState <= '0';`
365			`end if;`
366			`DCDInt <= DCDInt;`
367			`else -- DCDstate = '1'`
368			`-- Then read the data register`
369			`if Read <= '1' then`
370			`DCDState <= '0';`
371			`DCDInt <= '0';`
372			`else`
373			`DCDState <= DCDState;`
374			`DCDInt <= DCDInt;`
375			`end if;`
376			`end if; -- DCDState`
377			`end if; -- clk / reset`
378			`end process;`
379
380			`---------------------------------------------------------------`
381			`--`
382			`-- reset may be hardware or software`
383			`--`
384			`---------------------------------------------------------------`
385
386			`miniUart_reset: process(rst, CtrlReg, Reset, DCD_n )`
387			`begin`
388			`Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;`
389			`TxRst <= Reset;`
390			`RxRst <= Reset or DCD_n;`
391			`end process;`
392
393			`end; --===================== End of architecture =======================--`
394