OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [cpu/] [alu/] [test_core.sv] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 gdevic 
//==============================================================
2 
// Test ALU core
3 
//==============================================================
4 
`timescale 100 ns/ 100 ns
5 
 
6 
module test_core;
7 
 
8 
// ----------------- INPUT -----------------
9 
reg [3:0] op1_sig;          // Operand 1
10 
reg [3:0] op2_sig;          // Operand 2
11 
reg cy_in_sig;              // Carry in (to slice D)
12 
reg R_sig;                  // Operation control "R"
13 
reg S_sig;                  // Operation control "S"
14 
reg V_sig;                  // Operation control "V"
15 
 
16 
// ----------------- OUTPUT -----------------
17 
wire cy_out_sig;            // Carry out (from slice A)
18 
wire vf_out_sig;            // Overflow out
19 
wire [3:0] result_sig;      // Result bits
20 
 
21 
// ----------------- TEST -------------------
22 
`define CHECK(arg) \
23 
   assert(result_sig==arg);
24 
 
25 
initial begin
26 
    //------------------------------------------------------------
27 
    // Test ADD/ADC:    R=0  S=0  V=0    Cin for ADC operation
28 
    R_sig = 0;
29 
    S_sig = 0;
30 
    V_sig = 0;
31 
        op1_sig = 4'h0;     // 0 + 0 + 0 = 0
32 
        op2_sig = 4'h0;
33 
        cy_in_sig = 0;
34 
    #1 `CHECK(4'h0);
35 
        cy_in_sig = 1;      // 0 + 0 + 1 = 1
36 
    #1 `CHECK(4'h1);
37 
        op1_sig = 4'h2;     // 2 + 8 + 0 = A
38 
        op2_sig = 4'h8;
39 
        cy_in_sig = 0;
40 
    #1 `CHECK(4'hA);
41 
        cy_in_sig = 1;      // 2 + 8 + 1 = B
42 
    #1 `CHECK(4'hB);
43 
        op1_sig = 4'hB;     // B + 4 + 0 = F
44 
        op2_sig = 4'h4;
45 
        cy_in_sig = 0;
46 
    #1 `CHECK(4'hF);
47 
        cy_in_sig = 1;      // B + 4 + 1 = 0 + CY
48 
    #1 `CHECK(4'h0);
49 
        op1_sig = 4'hD;     // D + 6 + 0 = 3 + CY
50 
        op2_sig = 4'h6;
51 
        cy_in_sig = 0;
52 
    #1 `CHECK(4'h3);
53 
        cy_in_sig = 1;      // D + 6 + 1 = 4 + CY
54 
    #1 `CHECK(4'h4);
55 
 
56 
    //------------------------------------------------------------
57 
    // Test XOR:        R=1  S=0  V=0  Cin=0
58 
    #1
59 
    R_sig = 1;
60 
    S_sig = 0;
61 
    V_sig = 0;
62 
    cy_in_sig = 0;
63 
        op1_sig = 4'h0;     // 0 ^ 0 = 0
64 
        op2_sig = 4'h0;
65 
    #1 `CHECK(4'h0);
66 
        op1_sig = 4'h3;     // 3 ^ C = F
67 
        op2_sig = 4'hC;
68 
    #1 `CHECK(4'hF);
69 
        op1_sig = 4'h6;     // 6 ^ 3 = 5
70 
        op2_sig = 4'h3;
71 
    #1 `CHECK(4'h5);
72 
        op1_sig = 4'hF;     // F ^ F = 0
73 
        op2_sig = 4'hF;
74 
    #1 `CHECK(4'h0);
75 
 
76 
    //------------------------------------------------------------
77 
    // Test AND:        R=0  S=1  V=0  Cin=1
78 
    #1
79 
    R_sig = 0;
80 
    S_sig = 1;
81 
    V_sig = 0;
82 
    cy_in_sig = 1;
83 
        op1_sig = 4'h0;     // 0 & 0 = 0
84 
        op2_sig = 4'h0;
85 
    #1 `CHECK(4'h0);
86 
        op1_sig = 4'h3;     // 3 & C = 0
87 
        op2_sig = 4'hC;
88 
    #1 `CHECK(4'h0);
89 
        op1_sig = 4'h6;     // 6 & 3 = 2
90 
        op2_sig = 4'h3;
91 
    #1 `CHECK(4'h2);
92 
        op1_sig = 4'hF;     // F & F = F
93 
        op2_sig = 4'hF;
94 
    #1 `CHECK(4'hF);
95 
 
96 
    //------------------------------------------------------------
97 
    // Test OR:         R=1  S=1  V=1  Cin=0
98 
    #1
99 
    R_sig = 1;
100 
    S_sig = 1;
101 
    V_sig = 1;
102 
    cy_in_sig = 0;
103 
        op1_sig = 4'h0;     // 0 | 0 = 0
104 
        op2_sig = 4'h0;
105 
    #1 `CHECK(4'h0);
106 
        op1_sig = 4'h3;     // 3 | C = F
107 
        op2_sig = 4'hC;
108 
    #1 `CHECK(4'hF);
109 
        op1_sig = 4'h6;     // 6 | 3 = 7
110 
        op2_sig = 4'h3;
111 
    #1 `CHECK(4'h7);
112 
        op1_sig = 4'hF;     // F | F = F
113 
        op2_sig = 4'hF;
114 
    #1 `CHECK(4'hf);
115 
 
116 
    #1 $display("End of test");
117 
end
118 
 
119 
//--------------------------------------------------------------
120 
// Instantiate ALU core block
121 
//--------------------------------------------------------------
122 
alu_core alu_core_inst
123 
(
124 
    .cy_in(cy_in_sig) ,         // input  cy_in_sig
125 
    .op1(op1_sig[3:0]) ,        // input [3:0] op1_sig
126 
    .op2(op2_sig[3:0]) ,        // input [3:0] op2_sig
127 
    .S(S_sig) ,                 // input  S_sig
128 
    .V(V_sig) ,                 // input  V_sig
129 
    .R(R_sig) ,                 // input  R_sig
130 
    .cy_out(cy_out_sig) ,       // output  cy_out_sig
131 
    .vf_out(vf_out_sig) ,       // output  vf_out_sig
132 
    .result(result_sig[3:0])    // output [3:0] result_sig
133 
);
134 
 
135 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.