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[/] [a-z80/] [trunk/] [cpu/] [alu/] [test_shifter_core.sv] - Blame information for rev 17

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Line No. Rev Author Line
1 3 gdevic 
//==============================================================
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// Test ALU shifter core block
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//==============================================================
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`timescale 100 ns/ 100 ns
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module test_shifter_core;
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// ----------------- INPUT -----------------
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logic [7:0] db;                 // Input data bus
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logic shift_in;                 // Input bit to be shifted in
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logic shift_left;               // Input control to left-shift
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logic shift_right;              // Input control to right-shift
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// ----------------- OUTPUT -----------------
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wire shift_db0;                 // db[0] for shift logic
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wire shift_db7;                 // db[7] for shift logic
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wire [3:0] out_high;            // To internal ALU bus, high nibble
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wire [3:0] out_low;             // ..low nibble
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// ----------------- TEST -------------------
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`define CHECK(arg) \
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   assert({out_high,out_low}==arg);
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initial begin
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    db = 8'h00;
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    shift_left = 0;
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    shift_right = 0;
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    shift_in = 0;
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    //------------------------------------------------------------
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    // Test load without shifting
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        db = 8'hAA;
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    #1 `CHECK(8'hAA);
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        db = 8'h55;
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    #1 `CHECK(8'h55);
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    //------------------------------------------------------------
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    // Test right shift, no carry-in
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    #1  db =  8'b00000001;
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        shift_right = 1;
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        shift_in = 0;
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    #1 `CHECK(8'b00000000);
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        db =  8'b00000010;
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    #1 `CHECK(8'b00000001);
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        db =  8'b00000100;
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    #1 `CHECK(8'b00000010);
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        db =  8'b00001000;
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    #1 `CHECK(8'b00000100);
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        db =  8'b00010000;
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    #1 `CHECK(8'b00001000);
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        db =  8'b00100000;
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    #1 `CHECK(8'b00010000);
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        db =  8'b01000000;
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    #1 `CHECK(8'b00100000);
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        db =  8'b10000000;
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    #1 `CHECK(8'b01000000);
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    // With carry-in
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    #1  db =  8'b00000001;
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        shift_in = 1;
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    #1 `CHECK(8'b10000000);
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        db =  8'b00000010;
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    #1 `CHECK(8'b10000001);
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        db =  8'b00000100;
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    #1 `CHECK(8'b10000010);
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        db =  8'b00001000;
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    #1 `CHECK(8'b10000100);
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        db =  8'b00010000;
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    #1 `CHECK(8'b10001000);
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        db =  8'b00100000;
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    #1 `CHECK(8'b10010000);
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        db =  8'b01000000;
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    #1 `CHECK(8'b10100000);
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        db =  8'b10000000;
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    #1 `CHECK(8'b11000000);
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    //------------------------------------------------------------
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    // Test left shift, no carry-in
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    #1  db =  8'b00000001;
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        shift_right = 0;
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        shift_left = 1;
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        shift_in = 0;
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    #1 `CHECK(8'b00000010);
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        db =  8'b00000010;
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    #1 `CHECK(8'b00000100);
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        db =  8'b00000100;
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    #1 `CHECK(8'b00001000);
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        db =  8'b00001000;
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    #1 `CHECK(8'b00010000);
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        db =  8'b00010000;
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    #1 `CHECK(8'b00100000);
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        db =  8'b00100000;
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    #1 `CHECK(8'b01000000);
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        db =  8'b01000000;
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    #1 `CHECK(8'b10000000);
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        db =  8'b10000000;
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    #1 `CHECK(8'b00000000);
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    // With carry-in
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    #1  db =  8'b00000001;
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        shift_in = 1;
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    #1 `CHECK(8'b00000011);
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        db =  8'b00000010;
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    #1 `CHECK(8'b00000101);
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        db =  8'b00000100;
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    #1 `CHECK(8'b00001001);
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        db =  8'b00001000;
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    #1 `CHECK(8'b00010001);
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        db =  8'b00010000;
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    #1 `CHECK(8'b00100001);
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        db =  8'b00100000;
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    #1 `CHECK(8'b01000001);
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        db =  8'b01000000;
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    #1 `CHECK(8'b10000001);
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        db =  8'b10000000;
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    #1 `CHECK(8'b00000001);
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    //------------------------------------------------------------
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    // Test right shift, no carry-in - special SRA instruction
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    // This instruction simply duplicates bit [7] instead of using CY
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    #1  db =  8'b00000001;
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        shift_right = 1;
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        shift_left = 0;
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        shift_in = shift_db7;
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    #1 `CHECK(8'b10000000);
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        db =  8'b00000010;
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    #1 `CHECK(8'b10000001);
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        db =  8'b00000100;
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    #1 `CHECK(8'b10000010);
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        db =  8'b00001000;
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    #1 `CHECK(8'b10000100);
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        db =  8'b00010000;
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    #1 `CHECK(8'b10001000);
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        db =  8'b00100000;
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    #1 `CHECK(8'b10010000);
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        db =  8'b01000000;
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    #1 `CHECK(8'b10100000);
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        db =  8'b10000000;
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    #1 `CHECK(8'b11000000);
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    // With carry-in
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    #1  db =  8'b00000001;
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        shift_in = 1;
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    #1 `CHECK(8'b10000000);
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        db =  8'b00000010;
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    #1 `CHECK(8'b10000001);
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        db =  8'b00000100;
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    #1 `CHECK(8'b10000010);
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        db =  8'b00001000;
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    #1 `CHECK(8'b10000100);
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        db =  8'b00010000;
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    #1 `CHECK(8'b10001000);
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        db =  8'b00100000;
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    #1 `CHECK(8'b10010000);
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        db =  8'b01000000;
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    #1 `CHECK(8'b10100000);
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        db =  8'b10000000;
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    #1 `CHECK(8'b11000000);
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    #1 $display("End of test");
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end
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//--------------------------------------------------------------
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// Instantiate shifter core block and assign identical nets and variables
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//--------------------------------------------------------------
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alu_shifter_core alu_shifter_core_inst( .* );
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endmodule

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