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[/] [a-z80/] [trunk/] [cpu/] [control/] [Timings.csv] - Blame information for rev 12

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Line No. Rev Author Line
1 3 gdevic
A-Z80 Timing Table      M_      T_      Function        valid   nextM   setM1   A:reg rd        A:reg wr        inc/dec A:latch D:reg rd        D:reg wr        Reg gate        SW2     SW1     DB pads FLAGT   ALU     ALU bus op2 latch       op1 latch       nibble  operation               SZ      XY      HF      PF      NF      CF      CF2             Special Comments
2
 
3
// 8-bit Load Group
4
 
5 8 gdevic
"#if pla[17] & ~pla[50] : ld r,n"                       "4,3"
6 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 r8      <        d       <        R
7
#002H T2  AB:000 DB:46  M1      MREQ RD 1       2       fMFetch
8
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
9 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
10 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
11
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
12 8 gdevic
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead                  Y
13 3 gdevic
#end
14
 
15 8 gdevic
"#if pla[61] & ~pla[58] & ~pla[59] : ld r,r'"                   4
16 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 r8      <        u                               <        op1
17
#002H T2  AB:000 DB:05  M1      MREQ RD 1       2       fMFetch
18
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
19 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                       r8              >r8     -                               >s0                     bus
20 3 gdevic
#end
21
 
22 8 gdevic
"#if use_ixiy & pla[58] : ld r,(ix+d)"                  "4,3,5,3"
23 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch                                                                 r8      <        d       <        R
24
#006H T2  AB:001 DB:4E  M1      MREQ RD 1       2       fMFetch
25
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch
26 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
27 3 gdevic
#009H T5  AB:002 DB:--  2       1       fMRead                          PC                      W
28
#010H T6  AB:002 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
29 8 gdevic
#011H T7  AB:002 DB:01          MREQ RD 2       3       fMRead          Y
30 3 gdevic
#012H T8  AB:002 DB:--  3       1                                                                                                                                                                                                                                                       WZ=IX+d
31
#013H T9  AB:002 DB:--  3       2                                                                                                                                                                                                                                                       WZ=IX+d
32
#014H T10 AB:002 DB:--  3       3                                                                                                                                                                                                                                                       WZ=IX+d
33
#015H T11 AB:002 DB:--  3       4                                                                                                                                                                                                                                                       WZ=IX+d
34
#016H T12 AB:002 DB:--  3       5                       mr                                                                                                                                                                                                                              WZ=IX+d Clears the IX/IY and ...
35
#end
36
 
37 8 gdevic
"#if ~use_ixiy & pla[58] : ld r,(hl)"                   "4,3"
38 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 r8      <        d       <        R
39
#002H T2  AB:000 DB:46  M1      MREQ RD 1       2       fMFetch
40
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
41 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
42 3 gdevic
#005H T5  AB:003 DB:--  2       1       fMRead                          HL                      W
43
#006H T6  AB:003 DB:03          MREQ RD 2       2       fMRead
44 8 gdevic
#007H T7  AB:003 DB:03          MREQ RD 2       3       fMRead                  Y
45 3 gdevic
 
46
#017H T13 AB:001 DB:--  4       1       fMRead                                                  R                                                                                                                                                                                               ...continues here
47
#018H T14 AB:001 DB:4E          MREQ RD 4       2       fMRead
48 8 gdevic
#019H T15 AB:001 DB:4E          MREQ RD 4       3       fMRead                  Y
49 3 gdevic
#end
50
 
51 8 gdevic
"#if use_ixiy & pla[59] : ld (ix+d),r"                  "4,3,5,3"
52 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
53
#006H T2  AB:001 DB:70  M1      MREQ RD 1       2       fMFetch
54
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch
55 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
56 3 gdevic
#009H T5  AB:002 DB:--  2       1       fMRead                          PC                      W
57
#010H T6  AB:002 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
58 8 gdevic
#011H T7  AB:002 DB:01          MREQ RD 2       3       fMRead          Y
59 3 gdevic
#012H T8  AB:002 DB:--  3       1                                                                                                                                                                                                                                                       WZ=IX+d
60
#013H T9  AB:002 DB:--  3       2                                                                                                                                                                                                                                                       WZ=IX+d
61
#014H T10 AB:002 DB:--  3       3                                                                                                                                                                                                                                                       WZ=IX+d
62
#015H T11 AB:002 DB:--  3       4                                                                                                                                                                                                                                                       WZ=IX+d
63
#016H T12 AB:002 DB:--  3       5                       mw                                                                                                                                                                                                                              WZ=IX+d Clears the IX/IY and ...
64
#end
65
 
66 8 gdevic
"#if ~use_ixiy & pla[59] : ld (hl),r"                   "4,3"
67 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
68
#002H T2  AB:000 DB:70  M1      MREQ RD 1       2       fMFetch
69
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
70 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mw                                              r8              >r8     -       >       W
71 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMWrite                         HL                      W
72
#006H T6  AB:001 DB:01          MREQ    2       2       fMWrite
73 8 gdevic
#007H T7  AB:001 DB:01          MREQ    WR      2       3       fMWrite                 Y
74 3 gdevic
 
75 8 gdevic
#017H T13 AB:000 DB:--  4       1       fMWrite                                                 R       r8              >r8     -       >       W                                                                                                                                               ...continues here
76 3 gdevic
#018H T14 AB:000 DB:46          MREQ    4       2       fMWrite
77 8 gdevic
#019H T15 AB:000 DB:46          MREQ    WR      4       3       fMWrite                 Y
78 3 gdevic
#end
79
 
80
"#if pla[40] : ld (ix+d),n"                     "4,3,5,3"
81
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
82
#006H T2  AB:001 DB:36  M1      MREQ RD 1       2       fMFetch
83
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch
84 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
85 3 gdevic
#009H T5  AB:002 DB:--  2       1       fMRead                          PC                      W
86
#010H T6  AB:002 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
87
#011H T7  AB:002 DB:01          MREQ RD 2       3       fMRead          mr
88
#012H T8  AB:003 DB:--  3       1       fMRead                          PC                      W                                                                                                                                                                                       WZ=IX+d
89
#013H T9  AB:003 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R                                                                                                                                                                                       WZ=IX+d
90
#014H T10 AB:003 DB:02          MREQ RD 3       3       fMRead                                                                                                                                                                                                                                          WZ=IX+d "Reads ""n"" at the same time"
91
#015H T11 AB:003 DB:--  3       4                                                                                                                                                                                                                                                       WZ=IX+d
92
#016H T12 AB:003 DB:--  3       5                       mw                                                                                                                                                                                                                              WZ=IX+d Clears the IX/IY and ...
93
#end
94
 
95 8 gdevic
"#if pla[50] & ~pla[40] : ld (hl),n"                    "4,3,3"
96 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
97
#002H T2  AB:000 DB:36  M1      MREQ RD 1       2       fMFetch
98
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
99 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
100 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
101
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
102
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          mw
103
#008H T8  AB:001 DB:--  3       1       fMWrite                         HL                      W
104
#009H T9  AB:001 DB:01          MREQ    3       2       fMWrite
105 8 gdevic
#010H T10 AB:001 DB:01          MREQ    WR      3       3       fMWrite                 Y
106 3 gdevic
 
107
#017H T13 AB:002 DB:--  4       1       fMWrite                                                 R                                                                                                                                                                                               ...continues here
108
#018H T14 AB:002 DB:02          MREQ    4       2       fMWrite
109 8 gdevic
#019H T15 AB:002 DB:02          MREQ    WR      4       3       fMWrite                 Y
110 3 gdevic
#end
111
 
112 8 gdevic
"#if pla[8] & pla[13] : ld (rr),a"                      "4,3"
113 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
114
#002H T2  AB:000 DB:02  M1      MREQ RD 1       2       fMFetch
115
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
116 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mw                                              A               >h      u       >       W
117 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMWrite                         r16                     W
118
#006H T6  AB:001 DB:FF          MREQ    2       2       fMWrite                                 WZ      +       R
119 8 gdevic
#007H T7  AB:001 DB:FF          MREQ    WR      2       3       fMWrite                 Y
120 3 gdevic
#end
121
 
122 8 gdevic
"#if pla[8] & ~pla[13] : ld a,(rr)"                     "4,3"
123 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <        d       <        R
124
#002H T2  AB:000 DB:0A  M1      MREQ RD 1       2       fMFetch
125
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
126 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
127 3 gdevic
#005H T5  AB:002 DB:--  2       1       fMRead                          r16                     W
128
#006H T6  AB:002 DB:02          MREQ RD 2       2       fMRead                                  WZ      +       R
129 8 gdevic
#007H T7  AB:002 DB:02          MREQ RD 2       3       fMRead                  Y
130 3 gdevic
#end
131
 
132 8 gdevic
"#if pla[38] & pla[13] : ld (nn),a"                     "4,3,3,3"
133 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
134
#002H T2  AB:000 DB:32  M1      MREQ RD 1       2       fMFetch
135
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
136 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
137 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
138
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
139
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
140
#008H T8  AB:002 DB:--  3       1       fMRead                          PC                      W
141
#009H T9  AB:002 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R
142
#010H T10 AB:002 DB:02          MREQ RD 3       3       fMRead          mw              WZ                      W               W       
143 8 gdevic
#011H T11 AB:001 DB:--  4       1       fMWrite                                                 R       A               >h      u       >       W
144 3 gdevic
#012H T12 AB:001 DB:FE          MREQ    4       2       fMWrite                                 WZ      +       R
145 8 gdevic
#013H T13 AB:001 DB:FE          MREQ    WR      4       3       fMWrite                 Y
146 3 gdevic
#end
147
 
148 8 gdevic
"#if pla[38] & ~pla[13] : ld a,(nn)"                    "4,3,3,3"
149 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <        d       <        R
150
#002H T2  AB:000 DB:3A  M1      MREQ RD 1       2       fMFetch
151
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
152 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
153 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
154
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
155
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
156
#008H T8  AB:002 DB:--  3       1       fMRead                          PC                      W
157
#009H T9  AB:002 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R
158
#010H T10 AB:002 DB:02          MREQ RD 3       3       fMRead          mr                                                      W       
159
#011H T11 AB:001 DB:--  4       1       fMRead                          WZ                      W
160
#012H T12 AB:001 DB:01          MREQ RD 4       2       fMRead                                  WZ      +       R
161 8 gdevic
#013H T13 AB:001 DB:01          MREQ RD 4       3       fMRead                  Y
162 3 gdevic
#end
163
 
164
"#if pla[83] : ld a,i/a,r"                      5
165
#005H T1  AB:001 DB:--  M1      1       1       fMFetch                                                                 A       <                                alu     <        res                     H       OR              *       *       *       iff2    0
166
#006H T2  AB:001 DB:57  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <
167
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
168 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y                                                       I/R             >r8'    -                       alu     >s0             bus     bus     L       OR              *       *       *               0
169
#009H T5  AB:001 DB:--  1       5                               Y
170 3 gdevic
#end
171
 
172
"#if pla[57] : ld i,a/r,a"                      5
173
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
174
#006H T2  AB:001 DB:47  M1      MREQ RD 1       2       fMFetch
175
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
176 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y                                                               I/R     <        u                               <        op1
177
#009H T5  AB:001 DB:--  1       5                               Y
178 3 gdevic
#end
179
 
180
// 16-bit Load Group
181
 
182
"#if pla[7] : ld rr,nn"                 "4,3,3"
183
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 rh      <        d       <        R                                                                                                                                       USE_SP
184
#002H T2  AB:000 DB:01  M1      MREQ RD 1       2       fMFetch
185
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
186 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
187 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
188
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
189
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          mr
190
#008H T8  AB:002 DB:--  3       1       fMRead                          PC                      W               rl      <        d       <        R                                                                                                                                       USE_SP
191
#009H T9  AB:002 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R
192 8 gdevic
#010H T10 AB:002 DB:02          MREQ RD 3       3       fMRead                  Y
193 3 gdevic
#end
194
 
195 8 gdevic
"#if pla[30] & pla[13] : ld (nn),hl"                    "4,3,3,3,3"
196 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
197
#002H T2  AB:000 DB:22  M1      MREQ RD 1       2       fMFetch
198
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
199 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
200 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
201
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
202
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
203
#008H T8  AB:002 DB:--  3       1       fMRead                          PC                      W
204
#009H T9  AB:002 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R
205
#010H T10 AB:002 DB:02          MREQ RD 3       3       fMRead          mw              WZ                      W               W       
206 8 gdevic
#011H T11 AB:001 DB:--  4       1       fMWrite                                                 R       rl              >l              >       W
207 3 gdevic
#012H T12 AB:001 DB:01          MREQ    4       2       fMWrite                                 WZ      +       R
208
#013H T13 AB:001 DB:01          MREQ    WR      4       3       fMWrite         mw              WZ                      W
209 8 gdevic
#014H T14 AB:002 DB:--  5       1       fMWrite                                                 R       rh              >h      u       >       W
210 3 gdevic
#015H T15 AB:002 DB:02          MREQ    5       2       fMWrite                                 WZ      +       R
211 8 gdevic
#016H T16 AB:002 DB:02          MREQ    WR      5       3       fMWrite                 Y
212 3 gdevic
#end
213
 
214 8 gdevic
"#if pla[30] & ~pla[13] : ld hl,(nn)"                   "4,3,3,3,3"
215 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
216
#002H T2  AB:000 DB:2A  M1      MREQ RD 1       2       fMFetch
217
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
218 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
219 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
220
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
221
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
222
#008H T8  AB:002 DB:--  3       1       fMRead                          PC                      W
223
#009H T9  AB:002 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R
224
#010H T10 AB:002 DB:02          MREQ RD 3       3       fMRead          mr                                                      W       
225
#011H T11 AB:001 DB:--  4       1       fMRead                          WZ                      W
226
#012H T12 AB:001 DB:01          MREQ RD 4       2       fMRead                                  WZ      +       R
227
#013H T13 AB:001 DB:01          MREQ RD 4       3       fMRead          mr                                                      rl      <        d       <        R
228
#014H T14 AB:002 DB:--  5       1       fMRead                          WZ                      W
229
#015H T15 AB:002 DB:02          MREQ RD 5       2       fMRead                                  WZ      +       R
230 8 gdevic
#016H T16 AB:002 DB:02          MREQ RD 5       3       fMRead                  Y                                               rh      <        d       <        R
231 3 gdevic
#end
232
 
233 8 gdevic
"#if pla[31] & pla[33] : ld (nn),rr"                    "4,3,3,3,3"
234 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
235
#006H T2  AB:001 DB:43  M1      MREQ RD 1       2       fMFetch
236
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch
237 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
238 3 gdevic
#009H T5  AB:002 DB:--  2       1       fMRead                          PC                      W
239
#010H T6  AB:002 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
240
#011H T7  AB:002 DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
241
#012H T8  AB:003 DB:--  3       1       fMRead                          PC                      W
242
#013H T9  AB:003 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R
243
#014H T10 AB:003 DB:02          MREQ RD 3       3       fMRead          mw              WZ                      W               W       
244 8 gdevic
#015H T11 AB:001 DB:--  4       1       fMWrite                                                 R       rl              >l              >       W                                                                                                                                       USE_SP
245 3 gdevic
#016H T12 AB:001 DB:FF          MREQ    4       2       fMWrite                                 WZ      +       R
246
#017H T13 AB:001 DB:FF          MREQ    WR      4       3       fMWrite         mw              WZ                      W
247 8 gdevic
#018H T14 AB:002 DB:--  5       1       fMWrite                                                 R       rh              >h      u       >       W                                                                                                                                       USE_SP
248 3 gdevic
#019H T15 AB:002 DB:C3          MREQ    5       2       fMWrite                                 WZ      +       R
249 8 gdevic
#020H T16 AB:002 DB:C3          MREQ    WR      5       3       fMWrite                 Y
250 3 gdevic
#end
251
 
252 8 gdevic
"#if pla[31] & ~pla[33] : ld rr,(nn)"                   "4,3,3,3,3"
253 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
254
#006H T2  AB:001 DB:43  M1      MREQ RD 1       2       fMFetch
255
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch
256 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
257 3 gdevic
#009H T5  AB:002 DB:--  2       1       fMRead                          PC                      W
258
#010H T6  AB:002 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
259
#011H T7  AB:002 DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
260
#012H T8  AB:003 DB:--  3       1       fMRead                          PC                      W
261
#013H T9  AB:003 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R
262
#014H T10 AB:003 DB:02          MREQ RD 3       3       fMRead          mr                                                      W       
263
#015H T11 AB:001 DB:--  4       1       fMRead                          WZ                      W
264
#016H T12 AB:001 DB:FF          MREQ RD 4       2       fMRead                                  WZ      +       R
265
#017H T13 AB:001 DB:FF          MREQ RD 4       3       fMRead          mr                                                      rl      <        d       <        R                                                                                                                                       USE_SP
266
#018H T14 AB:002 DB:--  5       1       fMRead                          WZ                      W
267
#019H T15 AB:002 DB:C3          MREQ RD 5       2       fMRead                                  WZ      +       R
268 8 gdevic
#020H T16 AB:002 DB:C3          MREQ RD 5       3       fMRead                  Y                                               rh      <        d       <        R                                                                                                                                       USE_SP
269 3 gdevic
#end
270
 
271
"#if pla[5] : ld sp,hl"                 6
272
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
273
#002H T2  AB:000 DB:F9  M1      MREQ RD 1       2       fMFetch
274
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
275 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y                       HL                      W
276 3 gdevic
#005H T5  AB:000 DB:--  1       5                                               SP              R
277 8 gdevic
#006H T6  AB:000 DB:--  1       6                               Y
278 3 gdevic
#end
279
 
280 8 gdevic
#if pla[23] & pla[16] : push qq                 "5,3,3"
281 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
282
#002H T2  AB:000 DB:C5  M1      MREQ RD 1       2       fMFetch
283
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
284 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y
285 3 gdevic
#005H T5  AB:000 DB:--  1       5                       mw              SP              -       W
286 8 gdevic
#006H T6  AB:002 DB:--  2       1       fMWrite                                         -       P       rh              >h      u       >       W
287 3 gdevic
#007H T7  AB:002 DB:02          MREQ    2       2       fMWrite                                 SP      -       R
288
#008H T8  AB:002 DB:02          MREQ    WR      2       3       fMWrite         mw              SP              -       W
289 8 gdevic
#009H T9  AB:001 DB:--  3       1       fMWrite                                         -       P       rl              >l              >       W
290 3 gdevic
#010H T10 AB:001 DB:01          MREQ    3       2       fMWrite                                 SP      -       R
291 8 gdevic
#011H T11 AB:001 DB:01          MREQ    WR      3       3       fMWrite                 Y
292 3 gdevic
#end
293
 
294 8 gdevic
#if pla[23] & ~pla[16] : pop qq                 "4,3,3"
295 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
296
#002H T2  AB:000 DB:C1  M1      MREQ RD 1       2       fMFetch
297
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
298 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
299 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          SP                      W
300
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  SP      +       R
301
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          mr                                                      rl      <        d       <        R
302
#008H T8  AB:002 DB:--  3       1       fMRead                          SP                      W
303
#009H T9  AB:002 DB:02          MREQ RD 3       2       fMRead                                  SP      +       R
304 8 gdevic
#010H T10 AB:002 DB:02          MREQ RD 3       3       fMRead                  Y                                               rh      <        d       <        R
305 3 gdevic
#end
306
 
307
"// Exchange, Block Transfer and Search Groups"
308
 
309
"#if pla[2] : ex de,hl"                 4
310
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
311
#002H T2  AB:000 DB:EB  M1      MREQ RD 1       2       fMFetch                                                                                                                                                                                                                                         Ex_DE_HL
312
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
313 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y
314 3 gdevic
#end
315
 
316
"#if pla[39] : ex af,af'"                       4
317
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
318
#002H T2  AB:000 DB:08  M1      MREQ RD 1       2       fMFetch                                                                                                                                                                                                                                         Ex_AF_AF'
319
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
320 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y
321 3 gdevic
#end
322
 
323
#if pla[1] : exx                        4
324
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
325
#002H T2  AB:000 DB:D9  M1      MREQ RD 1       2       fMFetch                                                                                                                                                                                                                                         EXX
326
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
327 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y
328 3 gdevic
#end
329
 
330
"#if pla[10] : ex (sp),hl"                      "4,3,4,3,5"
331
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
332
#002H T2  AB:000 DB:E3  M1      MREQ RD 1       2       fMFetch
333
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
334 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
335 3 gdevic
#005H T5  AB:0FD DB:--  2       1       fMRead                          SP                      W
336
#006H T6  AB:0FD DB:03          MREQ RD 2       2       fMRead                                  SP      +       R
337
#007H T7  AB:0FD DB:03          MREQ RD 2       3       fMRead          mr                                                      Z       
338
#008H T8  AB:0FE DB:--  3       1       fMRead                          SP                      W
339
#009H T9  AB:0FE DB:D1          MREQ RD 3       2       fMRead                                  SP      +       R
340
#010H T10 AB:0FE DB:D1          MREQ RD 3       3       fMRead                                                                  W       
341
#011H T11 AB:0FE DB:--  3       4                       mw              SP              -       W
342 8 gdevic
#012H T12 AB:0FE DB:--  4       1       fMWrite                                         -       P       rh              >h      u       >       W
343 3 gdevic
#013H T13 AB:0FE DB:00          MREQ    4       2       fMWrite                                 SP      -       R
344
#014H T14 AB:0FE DB:00          MREQ    WR      4       3       fMWrite         mw              SP              -       W
345 8 gdevic
#015H T15 AB:0FD DB:--  5       1       fMWrite                                         -       P       rl              >l              >       W
346 3 gdevic
#016H T16 AB:0FD DB:01          MREQ    5       2       fMWrite                                 SP      -       R
347
#017H T17 AB:0FD DB:01          MREQ    WR      5       3       fMWrite                         WZ                      W
348
#018H T18 AB:0FD DB:01  5       4                                               HL              R
349 8 gdevic
#019H T19 AB:0FD DB:01  5       5                               Y
350 3 gdevic
#end
351
 
352
#if pla[0] : Non-repeating version of a block instruction                       "4,3,5,(5)"
353
#always                                                                                                                                                                                                                                                                 NonRep
354
#end
355
 
356
#if pla[12] : ldi/ldir/ldd/lddr                 "4,3,5,(5)"
357
#035H T1  AB:00A DB:--  M1      1       1       fMFetch                                                                                                         alu             res                     H       OR                      *       *       REP     0                R
358
#036H T2  AB:00A DB:B0  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <
359
#037H T3  AB:004 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
360 8 gdevic
#038H T4  AB:004 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
361 3 gdevic
#039H T5  AB:000 DB:--  2       1       fMRead                          HL                      W
362
#040H T6  AB:000 DB:21          MREQ RD 2       2       fMRead                                  HL      op3     R
363
#041H T7  AB:000 DB:21          MREQ RD 2       3       fMRead          mw                                                                      d       <	R	alu	>s0              bus             L       ADD                             *                               W
364
#042H T8  AB:000 DB:--  3       1       fMWrite                         DE                      W                                                       alu     <        res                     H       ADD                                                             R
365
#043H T9  AB:000 DB:21          MREQ    3       2       fMWrite                                 DE      op3     R
366
#044H T10 AB:000 DB:21          MREQ    WR      3       3       fMWrite                         BC                      W
367
#045H T11 AB:000 DB:21  3       4                                               BC      -       R                                                                                                                                                                                       WriteBC=1       Update repeat flag latch
368 8 gdevic
#046H T12 AB:000 DB:21  3       5                       Y       BR
369 3 gdevic
#047H T13 AB:000 DB:--  4       1                                       PC                      W
370
#048H T14 AB:000 DB:--  4       2                                               PC      -       R
371
#049H T15 AB:000 DB:--  4       3                                       PC                      W
372
#050H T16 AB:000 DB:--  4       4                                               PC      -       R
373 8 gdevic
#051H T17 AB:000 DB:--  4       5                               Y
374 3 gdevic
#end
375
 
376
#if pla[11] : cpi/cpir/cpd/cpdr                 "4,3,5,(5)"
377
#035H T1  AB:00A DB:--  M1      1       1       fMFetch                                                                                                         alu     <        res             0        H       SUB                     *               REP     1               R
378
#036H T2  AB:00A DB:B1  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                                                ?NF_HF
379
#037H T3  AB:004 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
380 8 gdevic
#038H T4  AB:004 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
381 3 gdevic
#039H T5  AB:000 DB:--  2       1       fMRead                          HL                      W
382
#040H T6  AB:000 DB:21          MREQ RD 2       2       fMRead                                  HL      op3     R
383 8 gdevic
#041H T7  AB:000 DB:21          MREQ RD 2       3       fMRead          Y                                                                       d       <	R	alu	>s0              bus             L       SUB                             *                               W
384 3 gdevic
#042H T8  AB:000 DB:--  3       1                                                                                                                       alu     <        res                     H       SUB             *                                               R
385
#043H T9  AB:000 DB:--  3       2
386
#044H T10 AB:000 DB:--  3       3                                       BC                      W
387
#045H T11 AB:000 DB:--  3       4                                               BC      -       R                                                                                                                                                                                       WriteBC=1       Update repeat flag latch
388 8 gdevic
#046H T12 AB:000 DB:--  3       5                       Y       BRZ
389 3 gdevic
#047H T13 AB:000 DB:--  4       1                                       PC                      W
390
#048H T14 AB:000 DB:--  4       2                                               PC      -       R
391
#049H T15 AB:000 DB:--  4       3                                       PC                      W
392
#050H T16 AB:000 DB:--  4       4                                               PC      -       R
393 8 gdevic
#051H T17 AB:000 DB:--  4       5                               Y
394 3 gdevic
#end
395
 
396
// 8-bit Arithmetic and Logic Group
397
 
398 8 gdevic
"#if pla[65] & ~pla[52] : add/sub/and/or/xor/cmp a,r"                   4
399 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 ?       <        u                       alu     <        res                     H       PLA             *       ?               ?       ?       *                               A is stored in each ALU PLA below
400
#002H T2  AB:000 DB:80  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                PLA                                                                             ?NF_HF_CF       "If (NF), complement HF, CF"
401
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
402 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                       r8              >r8     -                       alu     >s0             bus             L       PLA             *       *       *               ?
403 3 gdevic
#end
404
 
405
"#if pla[64] : add/sub/and/or/xor/cmp a,n"                      "4,3"
406
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 ?       <        u                       alu     <        res                     H       PLA             *       ?               ?       ?       *                               A is stored in each ALU PLA below
407
#002H T2  AB:000 DB:C6  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                PLA                                                                             ?NF_HF_CF       "If (NF), complement HF, CF"
408
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
409 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr                                              r8              >r8     -                       alu     >s0             bus             L       PLA             *       *       *               ?
410 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W                                                                                                       PLA
411
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
412 8 gdevic
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead                  Y                                                               d       <	R	alu	>s0              bus             L       PLA             *       *       *               ?
413 3 gdevic
#end
414
 
415 8 gdevic
#if use_ixiy & pla[52] : add/sub/and/or/xor/cp (ix+d)                   "4,3,5,3"
416 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
417
#006H T2  AB:001 DB:86  M1      MREQ RD 1       2       fMFetch
418
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
419 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
420 3 gdevic
#009H T5  AB:002 DB:--  2       1       fMRead                          PC                      W
421
#010H T6  AB:002 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
422 8 gdevic
#011H T7  AB:002 DB:01          MREQ RD 2       3       fMRead          Y
423 3 gdevic
#012H T8  AB:002 DB:--  3       1                                                                                                                                                                                                                                                       WZ=IX+d
424
#013H T9  AB:002 DB:--  3       2                                                                                                                                                                                                                                                       WZ=IX+d
425
#014H T10 AB:002 DB:--  3       3                                                                                                                                                                                                                                                       WZ=IX+d "Reads ""n"" at the same time"
426
#015H T11 AB:002 DB:--  3       4                                                                                                                                                                                                                                                       WZ=IX+d
427
#016H T12 AB:002 DB:--  3       5                       mr                                                                                                                                                                                                                              WZ=IX+d Clears the IX/IY and ...
428
#end
429
 
430 8 gdevic
#if ~use_ixiy & pla[52] : add/sub/and/or/xor/cp (hl)                    "4,3"
431 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 ?       <        u                       alu     <        res                     H       PLA             *       ?               ?       ?       *                               A is stored in each ALU PLA below
432
#002H T2  AB:000 DB:86  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                PLA                                                                             ?NF_HF_CF       "If (NF), complement HF, CF"
433
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
434 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
435 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          HL                      W
436
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  WZ      +       R
437 8 gdevic
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead                  Y                                                               d       <	R	alu	>s0              bus             L       PLA             *       *       *               ?
438 3 gdevic
 
439
#017H T13 AB:000 DB:--  4       1       fMRead                                                  R                                                                                                                                                                                               ...continues here
440
#018H T14 AB:000 DB:DD          MREQ RD 4       2       fMRead                                                          AF              >                               >       >s0             bus     bus                             *       *       *               *       *                               Reloads AF since (IX+d) used ALU core
441 8 gdevic
#019H T15 AB:000 DB:DD          MREQ RD 4       3       fMRead                  Y                                                               d       <	R	alu	>s0              bus             L       PLA             *       *       *               ?
442 3 gdevic
#end
443
 
444 8 gdevic
#if pla[66] & ~pla[53] : inc/dec r                      4
445 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 r8      <        u                       alu     <        res                     H       ADC             *       *               V                       R
446
#002H T2  AB:000 DB:05  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                                                ?NF_HF  "If (NF), complement HF"
447
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
448 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                       r8'             >r8'    -                       alu     >s0             0        bus     L       ADC             *       *       *               0        1       W
449 3 gdevic
#end
450
 
451
#if pla[75] : dec
452
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                                                                                                                                                         1       0                        NEG_OP2
453
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch                                                                                                                                                                                                         1       0                        NEG_OP2
454
#end
455
 
456 8 gdevic
#if (M2 | M4) & pla[75] : dec
457 3 gdevic
#always                                                                                                                                                                                                                                 1       0                        NEG_OP2
458
#end
459
 
460 8 gdevic
#if use_ixiy & pla[53] : inc/dec (ix+d)                 "4,3,5,4,3"
461 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
462
#006H T2  AB:001 DB:34  M1      MREQ RD 1       2       fMFetch
463
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
464 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
465 3 gdevic
#009H T5  AB:002 DB:--  2       1       fMRead                          PC                      W
466
#010H T6  AB:002 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
467 8 gdevic
#011H T7  AB:002 DB:01          MREQ RD 2       3       fMRead          Y
468 3 gdevic
#012H T8  AB:002 DB:--  3       1                                                                                                                                                                                                                                                       WZ=IX+d
469
#013H T9  AB:002 DB:--  3       2                                                                                                                                                                                                                                                       WZ=IX+d
470
#014H T10 AB:002 DB:--  3       3                                                                                                                                                                                                                                                       WZ=IX+d
471
#015H T11 AB:002 DB:--  3       4                                                                                                                                                                                                                                                       WZ=IX+d
472
#016H T12 AB:002 DB:--  3       5                       mr                                                                                                                                                                                                                              WZ=IX+d Clears the IX/IY and ...
473
#end
474
 
475 8 gdevic
#if ~use_ixiy & pla[53] : inc/dec (hl)                  "4,4,3"
476 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
477
#002H T2  AB:000 DB:34  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                                                ?NF_HF  "If (NF), complement HF"
478
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
479 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
480 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          HL                      W
481
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead
482
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead                                                                                  d       <	R	alu	>s0              0        bus     L       ADC                             *               0        1       W
483
#008H T8  AB:001 DB:--  2       4                       mw                                                                      u       >       W       alu     <        res                     H       ADC             *       *               V                       R
484
#009H T9  AB:001 DB:--  3       1       fMWrite                                                 R
485
#010H T10 AB:001 DB:02          MREQ    3       2       fMWrite
486 8 gdevic
#011H T11 AB:001 DB:02          MREQ    WR      3       3       fMWrite                 Y
487 3 gdevic
 
488
#017H T13 AB:002 DB:--  4       1       fMRead                                                  R                                                                                                                                                                                               ...continues here
489
#018H T14 AB:002 DB:01          MREQ RD 4       2       fMRead
490
#019H T15 AB:002 DB:01          MREQ RD 4       3       fMRead                                                                                  d       <	R	alu	>s0              0        bus     L       ADC                             *               0        1       W
491
#020H T16 AB:002 DB:--  4       4                       mw                                                                      u       >       W       alu     <        res                     H       ADC             *       *               V                       R
492
#021H T17 AB:002 DB:--  5       1       fMWrite                                                 R
493
#022H T18 AB:002 DB:02          MREQ    5       2       fMWrite
494 8 gdevic
#023H T19 AB:002 DB:02          MREQ    WR      5       3       fMWrite                 Y
495 3 gdevic
#end
496
 
497
// 16-bit Arithmetic Group
498
 
499
"#if pla[69] : add hl,ss"                       "4,4,3"
500
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
501
#002H T2  AB:000 DB:09  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <
502
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       0        *
503 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       Y                                               L               >l      d                               >s0                     bus
504
#005H T5  AB:000 DB:--  2       1                                                                       rl              >l      d                       alu     >s0             bus             L       ADD                             *                                               USE_SP
505 3 gdevic
#006H T6  AB:000 DB:--  2       2                                                                               Z       
506 8 gdevic
#007H T7  AB:000 DB:--  2       3                                                                       H               >                                       >s0                     bus
507
#008H T8  AB:000 DB:--  2       4                       Y                                               rh              >                               alu     >s0             bus             L       ADC                             *                                               USE_SP
508 3 gdevic
#009H T9  AB:000 DB:--  3       1                                       WZ                      W               W       
509
#010H T10 AB:000 DB:--  3       2                                               HL              R
510 8 gdevic
#011H T11 AB:000 DB:--  3       3                               Y
511 3 gdevic
#end
512
 
513 8 gdevic
"#if op3 & pla[68] : adc hl,ss"                 "4,4,3"
514 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
515
#006H T2  AB:001 DB:42  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <
516
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       0        *
517 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       Y                                               L               >l      d                               >s0                     bus
518
#009H T5  AB:001 DB:--  2       1                                                                       rl              >l      d                       alu     >s0             bus             L       ADC                             *                                               USE_SP
519 3 gdevic
#010H T6  AB:001 DB:--  2       2                                                                               Z       
520 8 gdevic
#011H T7  AB:001 DB:--  2       3                                                                       H               >                                       >s0                     bus
521
#012H T8  AB:001 DB:--  2       4                       Y                                               rh              >                               alu     >s0             bus             L       ADC                             *                                               USE_SP
522 3 gdevic
#013H T9  AB:001 DB:--  3       1                                       WZ                      W               W       
523
#014H T10 AB:001 DB:--  3       2                                               HL              R
524 8 gdevic
#015H T11 AB:001 DB:--  3       3                               Y
525 3 gdevic
#end
526
 
527 8 gdevic
"#if ~op3 & pla[68] : sbc hl,ss"                        "4,4,3"
528 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
529
#006H T2  AB:001 DB:42  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                                                ?NF_HF_CF
530
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       1       *
531 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       Y                                               L               >l      d                               >s0                     bus
532
#009H T5  AB:001 DB:--  2       1                                                                       rl              >l      d                       alu     >s0             bus             L       SBC                             *                                               USE_SP
533 3 gdevic
#010H T6  AB:001 DB:--  2       2                                                                               Z       
534 8 gdevic
#011H T7  AB:001 DB:--  2       3                                                                       H               >                                       >s0                     bus
535
#012H T8  AB:001 DB:--  2       4                       Y                                               rh              >                               alu     >s0             bus             L       SBCh                            *                                               USE_SP
536 3 gdevic
#013H T9  AB:001 DB:--  3       1                                       WZ                      W               W       
537
#014H T10 AB:001 DB:--  3       2                                               HL              R
538 8 gdevic
#015H T11 AB:001 DB:--  3       3                               Y
539 3 gdevic
#end
540
 
541
#if pla[9] : inc/dec ss                 6
542
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
543
#002H T2  AB:000 DB:03  M1      MREQ RD 1       2       fMFetch
544
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
545 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y                       r16                     W                                                                                                                                                                                       USE_SP
546 3 gdevic
#005H T5  AB:000 DB:--  1       5                                               r16     op3     R                                                                                                                                                                                       USE_SP
547 8 gdevic
#006H T6  AB:000 DB:--  1       6                               Y
548 3 gdevic
#end
549
 
550
// General Purpose Arithmetic and CPU Control Groups
551
 
552
#if pla[77] : daa                       4
553
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <                                alu     <        res                     H       ADC             *       *               P               *                       ?NF_SUB
554
#002H T2  AB:000 DB:27  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                                R               ?NF_HF
555
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       W2      *       *       *                               "Only for DAA, write HF2 flag"
556 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                                               d                       alu     >s0             bus             L       ADC             *       *       *                       1       W.daa           "DAA,?NF_SUB"
557 3 gdevic
#end
558
 
559
#if pla[81] : cpl                       4
560
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <                                alu     <        res                     H       OR                      *                       1                               NEG_OP2
561
#002H T2  AB:000 DB:2F  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                                                ?NF_HF
562
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
563 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                                                                       alu                             0        L       OR                      *       *               1                               NEG_OP2
564 3 gdevic
#end
565
 
566
#if pla[82] : neg                       4
567
#005H T1  AB:001 DB:--  M1      1       1       fMFetch                                                                 A       <                                alu     <        res                     H       SUB             *       *               V       1       *
568
#006H T2  AB:001 DB:44  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                                                ?NF_HF_CF
569
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
570 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                                                                       alu                             0        L       SUB             *       *       *               1       *
571 3 gdevic
#end
572
 
573
#if pla[89] : ccf                       4
574
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                                                         alu     <        res                     H       OR                      *                       0
575
#002H T2  AB:000 DB:3F  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                        ^                       ?~CF_HF
576
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
577 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                                                                       alu                                     L       OR                      *       *               0
578 3 gdevic
#end
579
 
580
#if pla[92] : scf                       4
581
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                                                         alu     <        res                     H       OR                      *                       0
582
#002H T2  AB:000 DB:37  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                        1
583
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
584 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                                                                       alu                                     L       OR                      *       *               0
585 3 gdevic
#end
586
 
587
#if pla[95] : halt                      4
588
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
589
#002H T2  AB:000 DB:76  M1      MREQ RD 1       2       fMFetch
590
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                                                                                                                                                                                                         HALT
591 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y
592 3 gdevic
#end
593
 
594
#if pla[97] : di/ei                     4
595
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
596
#002H T2  AB:000 DB:F3  M1      MREQ RD 1       2       fMFetch
597
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                                                                                                                                                                                                         DI_EI
598 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                                                                                                                                                                                                       NO_INTS "At last M/T, inhibit interrupts"
599 3 gdevic
#end
600
 
601
#if pla[96] : im n                      4
602
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
603
#006H T2  AB:001 DB:46  M1      MREQ RD 1       2       fMFetch
604
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                                                         <        R                                                                                                                                       IM      M1/T3 reads in mode # from opcode[4:3]
605 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y               Y
606 3 gdevic
#end
607
 
608
// Rotate and Shift Group
609
 
610
#if pla[25] : rlca/rla/rrca/rra                 4
611
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <                                alu     <        res                     H       OR                      *       *               0        *
612
#002H T2  AB:000 DB:07  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                                R
613
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
614 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                       A               >                               alu     >s1             bus     bus     L       OR                      *       *               0                W.sh
615 3 gdevic
#end
616
 
617 8 gdevic
#if ~use_ixiy & pla[70] & ~pla[55] : rlc r                      4
618 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch                                                                 r8'     <        u                       alu     <        res                     H       OR              *       *       *       P       0        *
619
#006H T2  AB:001 DB:00  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                                R
620
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
621 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                       r8              >r8     -                       alu     >s1             bus     bus     L       OR              *       *       *               0                W.sh
622 3 gdevic
 
623
#017H T13 AB:000 DB:--  4       1       fMRead                          WZ                      W                                               R                                                                                                                                       OpcodeToIR      ...continues here from the (ix+d) addressing mode
624
#018H T14 AB:000 DB:DD          MREQ RD 4       2       fMRead
625
#019H T15 AB:000 DB:DD          MREQ RD 4       3       fMRead          mw                                                                      d       <	R	alu	>s1              bus     bus     L       OR                                              0                W.sh
626
#029H T17 AB:002 DB:--  5       1       fMWrite                                                 R                               u       >       W       alu     <        res                     H       OR              *       *       *       P       0        *
627
#030H T18 AB:002 DB:BB          MREQ    5       2       fMWrite
628 8 gdevic
#031H T19 AB:002 DB:BB          MREQ    WR      5       3       fMWrite                 Y
629 3 gdevic
#end
630
 
631 8 gdevic
#if ~use_ixiy & pla[70] & pla[55] : rlc (hl)                    "4,4,3"
632 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
633
#006H T2  AB:001 DB:00  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <                                                                                                                R
634
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
635 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
636 3 gdevic
#009H T5  AB:006 DB:--  2       1       fMRead                          HL                      W
637
#010H T6  AB:006 DB:05          MREQ RD 2       2       fMRead
638
#011H T7  AB:006 DB:05          MREQ RD 2       3       fMRead
639
#012H T8  AB:006 DB:--  2       4                       mw                                                                      d       <	R	alu	>s1              bus     bus     L       OR                                              0                W.sh
640
#013H T9  AB:006 DB:--  3       1       fMWrite                                                 R                               u       >       W       alu     <        res                     H       OR              *       *       *       P       0        *
641
#014H T10 AB:006 DB:0A          MREQ    3       2       fMWrite
642 8 gdevic
#015H T11 AB:006 DB:0A          MREQ    WR      3       3       fMWrite                 Y
643 3 gdevic
 
644
#017H T13 AB:000 DB:--  4       1       fMRead                          WZ                      W                                               R                                                                                                                                       OpcodeToIR      ...continues here from the (ix+d) addressing mode
645
#018H T14 AB:000 DB:DD          MREQ RD 4       2       fMRead
646
#019H T15 AB:000 DB:DD          MREQ RD 4       3       fMRead          mw                                                                      d       <	R	alu	>s1              bus     bus     L       OR                                              0                W.sh
647
#029H T17 AB:002 DB:--  5       1       fMWrite                                                 R                               u       >       W       alu     <        res                     H       OR              *       *       *       P       0        *
648
#030H T18 AB:002 DB:BB          MREQ    5       2       fMWrite
649 8 gdevic
#031H T19 AB:002 DB:BB          MREQ    WR      5       3       fMWrite                 Y
650 3 gdevic
#end
651
 
652 8 gdevic
#if pla[15] & op3 : rld                 "4,3,4,3"
653 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch                                                                 A       <                                alu     <        res                     H       OR              *       *               P       0
654
#006H T2  AB:001 DB:67  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <
655
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
656 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
657 3 gdevic
#009H T5  AB:000 DB:--  2       1       fMRead                          HL                      W
658
#010H T6  AB:000 DB:ED          MREQ RD 2       2       fMRead                                  WZ      +       R
659 8 gdevic
#011H T7  AB:000 DB:ED          MREQ RD 2       3       fMRead          Y
660 3 gdevic
#012H T8  AB:000 DB:--  3       1                                                                                               d       <	R		>s0              lq              L
661
#013H T9  AB:000 DB:--  3       2
662
#014H T10 AB:000 DB:--  3       3
663
#015H T11 AB:000 DB:--  3       4                       mw                                                                      d       <	R		>s0                      low     H
664
#016H T12 AB:000 DB:--  4       1       fMWrite                                                 R                               u       >       W               <        op2
665
#017H T13 AB:000 DB:EE          MREQ    4       2       fMWrite                                                                                                                         op1     bus
666 8 gdevic
#018H T14 AB:000 DB:EE          MREQ    WR      4       3       fMWrite                 Y                                                                                       alu                                     L       OR              *       *       *               0
667 3 gdevic
#end
668
 
669 8 gdevic
#if pla[15] & ~op3 : rrd                        "4,3,4,3"
670 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch                                                                 A       <                                alu     <        res                     H       OR              *       *               P       0
671
#006H T2  AB:001 DB:67  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <
672
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
673 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
674 3 gdevic
#009H T5  AB:000 DB:--  2       1       fMRead                          HL                      W
675
#010H T6  AB:000 DB:ED          MREQ RD 2       2       fMRead                                  WZ      +       R
676 8 gdevic
#011H T7  AB:000 DB:ED          MREQ RD 2       3       fMRead          Y
677 3 gdevic
#012H T8  AB:000 DB:--  3       1                                                                                               d       <	R		>s0              lq      low     L
678
#013H T9  AB:000 DB:--  3       2                                                                                               u       >       W               <        op2
679
#014H T10 AB:000 DB:--  3       3                                                                       A               >                                       >s0             lq              L
680
#015H T11 AB:000 DB:--  3       4                       mw                                                                      d       <	R		>s0                      low     H
681
#016H T12 AB:000 DB:--  4       1       fMWrite                                                 R                               u       >       W               <        op2
682
#017H T13 AB:000 DB:EE          MREQ    4       2       fMWrite                                                                                                                         op1     bus
683 8 gdevic
#018H T14 AB:000 DB:EE          MREQ    WR      4       3       fMWrite                 Y                                                                                       alu                                     L       OR              *       *       *               0
684 3 gdevic
#end
685
 
686
// Bit Manipulation Group
687
 
688 8 gdevic
"#if ~use_ixiy & pla[72] & ~pla[55] : bit b,r"                  4
689 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch                                                                                                         alu     <        res                     H       AND             *               *       P       0
690
#006H T2  AB:001 DB:40  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <
691
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                       R       >       >bs             bus     bus                             *       *       *       *       *       *                               Override M1/T3 load with a bit select
692 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                       r8              >r8     -                       alu     >s0                     bus     L       AND             *       *       *               0
693 3 gdevic
 
694
#017H T13 AB:000 DB:--  4       1       fMRead                                                  R                                               R               >bs             bus     bus                                                                                             OpcodeToIR      ...continues here from the (ix+d) addressing mode
695
#018H T14 AB:000 DB:DD          MREQ RD 4       2       fMRead
696
#019H T15 AB:000 DB:DD          MREQ RD 4       3       fMRead
697 8 gdevic
#020H T16 AB:000 DB:--  4       4                               Y                                                               d       <	R	alu	>s0                      bus     L       AND             *               *               0
698 3 gdevic
#end
699
 
700 8 gdevic
"#if ~use_ixiy & pla[72] & pla[55] : bit b,(hl)"                        "4,4"
701 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch                                                                                                         alu     <        res                     H       AND             *               *       P       0
702
#006H T2  AB:001 DB:06  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <
703
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                       R       >       >bs             bus     bus                             *       *       *       *       *       *                               Override M1/T3 load with a bit select
704 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
705 3 gdevic
#009H T5  AB:006 DB:--  2       1       fMRead                          HL                      W
706
#010H T6  AB:006 DB:05          MREQ RD 2       2       fMRead
707
#011H T7  AB:006 DB:05          MREQ RD 2       3       fMRead                                                          WZ              >                               >                                                                       *                                                               "BIT n,(HL) saves WZ in X,Y (""MEMPTR"")"
708 8 gdevic
#012H T8  AB:006 DB:--  2       4                               Y                                                               d       <	R	alu	>s0                      bus     L       AND             *               *               0
709 3 gdevic
 
710
#017H T13 AB:000 DB:--  4       1       fMRead                          WZ                      W                                               R               >bs             bus     bus                                                                                             OpcodeToIR      ...continues here from the (ix+d) addressing mode
711
#018H T14 AB:000 DB:DD          MREQ RD 4       2       fMRead
712
#019H T15 AB:000 DB:DD          MREQ RD 4       3       fMRead
713 8 gdevic
#020H T16 AB:000 DB:--  4       4                               Y                                                               d       <	R	alu	>s0                      bus     L       AND             *               *               0
714 3 gdevic
#end
715
 
716 8 gdevic
"#if ~use_ixiy & pla[74] & ~pla[55] : set b,r"                  4
717 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch                                                                 r8'     <        u                               <        res                     H       OR
718
#006H T2  AB:001 DB:40  M1      MREQ RD 1       2       fMFetch
719
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                       R       >       >bs             bus     bus                             *       *       *       *       *       *                               Override M1/T3 load with a bit select
720 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                       r8              >r8     -                               >s0                     bus     L       OR
721 3 gdevic
 
722
#017H T13 AB:000 DB:--  4       1       fMRead                          WZ                      W                                               R               >bs             bus     bus                                                                                             OpcodeToIR      ...continues here from the (ix+d) addressing mode
723
#018H T14 AB:000 DB:DD          MREQ RD 4       2       fMRead
724
#019H T15 AB:000 DB:DD          MREQ RD 4       3       fMRead          mw                                                                      d       <	R	alu	>s0                      bus     L       OR
725
#029H T17 AB:002 DB:--  5       1       fMWrite                                                 R                               u       >       W               <        res                     H       OR
726
#030H T18 AB:002 DB:BB          MREQ    5       2       fMWrite
727 8 gdevic
#031H T19 AB:002 DB:BB          MREQ    WR      5       3       fMWrite                 Y
728 3 gdevic
#end
729
 
730 8 gdevic
"#if ~use_ixiy & pla[74] & pla[55] : set b,(hl)"                        "4,4,3"
731 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
732
#006H T2  AB:001 DB:06  M1      MREQ RD 1       2       fMFetch
733
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                       R       >       >bs             bus     bus                             *       *       *       *       *       *                               Override M1/T3 load with a bit select
734 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
735 3 gdevic
#009H T5  AB:006 DB:--  2       1       fMRead                          HL                      W
736
#010H T6  AB:006 DB:05          MREQ RD 2       2       fMRead
737
#011H T7  AB:006 DB:05          MREQ RD 2       3       fMRead                                                                                  d       <	R		>s0                      bus     L       OR
738
#012H T8  AB:006 DB:--  2       4                       mw                                                                      u       >       W               <        res                     H       OR
739
#013H T9  AB:006 DB:--  3       1       fMWrite                                                 R
740
#014H T10 AB:006 DB:0A          MREQ    3       2       fMWrite
741 8 gdevic
#015H T11 AB:006 DB:0A          MREQ    WR      3       3       fMWrite                 Y
742 3 gdevic
 
743
#017H T13 AB:000 DB:--  4       1       fMRead                          WZ                      W                                               R               >bs             bus     bus                                                                                             OpcodeToIR      ...continues here from the (ix+d) addressing mode
744
#018H T14 AB:000 DB:DD          MREQ RD 4       2       fMRead
745
#019H T15 AB:000 DB:DD          MREQ RD 4       3       fMRead          mw                                                                      d       <	R	alu	>s0                      bus     L       OR
746
#029H T17 AB:002 DB:--  5       1       fMWrite                                                 R                               u       >       W               <        res                     H       OR
747
#030H T18 AB:002 DB:BB          MREQ    5       2       fMWrite
748 8 gdevic
#031H T19 AB:002 DB:BB          MREQ    WR      5       3       fMWrite                 Y
749 3 gdevic
#end
750
 
751 8 gdevic
"#if ~use_ixiy & pla[73] & ~pla[55] : res b,r"                  4
752 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch                                                                 r8'     <        u                               <        res                     H       NAND
753
#006H T2  AB:001 DB:40  M1      MREQ RD 1       2       fMFetch
754
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                       R       >       >bs             bus     bus                             *       *       *       *       *       *                               Override M1/T3 load with a bit select
755 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                       r8              >r8     -                               >s0                     bus     L       NAND
756 3 gdevic
 
757
#017H T13 AB:000 DB:--  4       1       fMRead                          WZ                      W                                               R               >bs             bus     bus                                                                                             OpcodeToIR      ...continues here from the (ix+d) addressing mode
758
#018H T14 AB:000 DB:DD          MREQ RD 4       2       fMRead
759
#019H T15 AB:000 DB:DD          MREQ RD 4       3       fMRead          mw                                                                      d       <	R	alu	>s0                      bus     L       NAND
760
#029H T17 AB:002 DB:--  5       1       fMWrite                                                 R                               u       >       W               <        res                     H       NAND
761
#030H T18 AB:002 DB:BB          MREQ    5       2       fMWrite
762 8 gdevic
#031H T19 AB:002 DB:BB          MREQ    WR      5       3       fMWrite                 Y
763 3 gdevic
#end
764
 
765 8 gdevic
"#if ~use_ixiy & pla[73] & pla[55] : res b,(hl)"                        "4,4,3"
766 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
767
#006H T2  AB:001 DB:06  M1      MREQ RD 1       2       fMFetch
768
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                       R       >       >bs             bus     bus                             *       *       *       *       *       *                               Override M1/T3 load with a bit select
769 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
770 3 gdevic
#009H T5  AB:006 DB:--  2       1       fMRead                          HL                      W
771
#010H T6  AB:006 DB:05          MREQ RD 2       2       fMRead
772
#011H T7  AB:006 DB:05          MREQ RD 2       3       fMRead                                                                                  d       <	R		>s0                      bus     L       NAND
773
#012H T8  AB:006 DB:--  2       4                       mw                                                                      u       >       W               <        res                     H       NAND
774
#013H T9  AB:006 DB:--  3       1       fMWrite                                                 R
775
#014H T10 AB:006 DB:0A          MREQ    3       2       fMWrite
776 8 gdevic
#015H T11 AB:006 DB:0A          MREQ    WR      3       3       fMWrite                 Y
777 3 gdevic
 
778
#017H T13 AB:000 DB:--  4       1       fMRead                          WZ                      W                                               R               >bs             bus     bus                                                                                             OpcodeToIR      ...continues here from the (ix+d) addressing mode
779
#018H T14 AB:000 DB:DD          MREQ RD 4       2       fMRead
780
#019H T15 AB:000 DB:DD          MREQ RD 4       3       fMRead          mw                                                                      d       <	R	alu	>s0                      bus     L       NAND
781
#029H T17 AB:002 DB:--  5       1       fMWrite                                                 R                               u       >       W               <        res                     H       NAND
782
#030H T18 AB:002 DB:BB          MREQ    5       2       fMWrite
783 8 gdevic
#031H T19 AB:002 DB:BB          MREQ    WR      5       3       fMWrite                 Y
784 3 gdevic
#end
785
 
786
// Input and Output Groups
787
 
788 8 gdevic
"#if pla[37] & ~pla[28] : in a,(n)"                     "4,3,4"
789 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <        d       <        R
790
#002H T2  AB:000 DB:DB  M1      MREQ RD 1       2       fMFetch
791
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
792 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
793 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
794
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
795
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          ior
796
#008H T8  AB:001 DB:--  3       1       fIORead                         A                       W               ?       <                <        R
797
#009H T9  AB:001 DB:--               RD    IORQ 3       2       fIORead
798
#010H T10 AB:001 DB:--               RD    IORQ 3       3       fIORead
799 8 gdevic
#011H T11 AB:001 DB:--               RD    IORQ 3       4       fIORead                 Y
800 3 gdevic
#end
801
 
802 8 gdevic
"#if pla[27] & ~pla[34] : in r,(c)"                     "4,4"
803 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch                                                                 r8      <        d       <        R       alu             res                     H       OR              *       *               P       0
804
#006H T2  AB:001 DB:40  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <
805
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
806 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       ior
807 3 gdevic
#009H T5  AB:0FF DB:--  2       1       fIORead                         BC                      W
808
#010H T6  AB:0FF DB:--               RD    IORQ 2       2       fIORead
809
#011H T7  AB:0FF DB:--               RD    IORQ 2       3       fIORead
810 8 gdevic
#012H T8  AB:0FF DB:--               RD    IORQ 2       4       fIORead                 Y                                                               d       <	R	alu	>s0              bus     bus     L       OR              *       *       *               0
811 3 gdevic
#end
812
 
813 8 gdevic
"#if pla[37] & pla[28] : out (n),a"                     "4,3,4"
814 3 gdevic
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
815
#002H T2  AB:000 DB:D3  M1      MREQ RD 1       2       fMFetch
816
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
817 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
818 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
819
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
820
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          iow             A                       W                       
821 8 gdevic
#008H T8  AB:001 DB:--  3       1       fIOWrite                                                        R       A               >h      u       >       W
822 3 gdevic
#009H T9  AB:001 DB:03                  WR IORQ 3       2       fIOWrite
823
#010H T10 AB:001 DB:03                  WR IORQ 3       3       fIOWrite
824 8 gdevic
#011H T11 AB:001 DB:03                  WR IORQ 3       4       fIOWrite                        Y
825 3 gdevic
#end
826
 
827 8 gdevic
"#if pla[27] & pla[34] : out (c),r"                     "4,4"
828 3 gdevic
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
829
#006H T2  AB:001 DB:41  M1      MREQ RD 1       2       fMFetch
830
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch
831 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       iow                                             r8'             >r8'    -       >       W
832 3 gdevic
#009H T5  AB:0FF DB:--  2       1       fIOWrite                                BC                      W
833
#010H T6  AB:0FF DB:C3                  WR IORQ 2       2       fIOWrite
834
#011H T7  AB:0FF DB:C3                  WR IORQ 2       3       fIOWrite
835 8 gdevic
#012H T8  AB:0FF DB:C3                  WR IORQ 2       4       fIOWrite                        Y
836 3 gdevic
#end
837
 
838 8 gdevic
#if pla[91] & pla[21] : ini/inir/ind/indr                       "5,4,3,(5)"
839 3 gdevic
#035H T1  AB:00A DB:--  M1      1       1       fMFetch                                                                                                                 <        res                     H       XOR                                     P
840
#036H T2  AB:00A DB:B2  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <
841
#037H T3  AB:004 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
842 8 gdevic
#038H T4  AB:004 DB:--     RFSH MREQ    1       4       fMFetch Y
843 3 gdevic
#039H T5  AB:004 DB:--  1       5                       ior
844
#040H T6  AB:000 DB:--  2       1       fIORead                         BC                      W
845
#041H T7  AB:000 DB:--               RD    IORQ 2       2       fIORead                                                         B               >                               alu     >s0             0        bus     L       ADD                             *                                               NEG_OP2
846
#042H T8  AB:000 DB:--               RD    IORQ 2       3       fIORead                                                                 B       <                                alu     <        res                     H       ADD             *       *                               *                       NEG_OP2
847
#043H T9  AB:000 DB:--               RD    IORQ 2       4       fIORead         mw                                                                      d       <	R	alu	>s0                      bus                                                             S                               NEG_OP2
848
#044H T10 AB:000 DB:--  3       1       fMWrite                         HL                      W
849
#045H T11 AB:000 DB:B1          MREQ    3       2       fMWrite                                 HL      op3     R
850 8 gdevic
#046H T12 AB:000 DB:B1          MREQ    WR      3       3       fMWrite         Y       BZ
851 7 gdevic
#047H T13 AB:000 DB:--  4       1                                       PC                      W
852 3 gdevic
#048H T14 AB:000 DB:--  4       2                                               PC      -       R
853 7 gdevic
#049H T15 AB:000 DB:--  4       3                                       PC                      W
854 3 gdevic
#050H T16 AB:000 DB:--  4       4                                               PC      -       R
855 8 gdevic
#051H T17 AB:000 DB:--  4       5                               Y
856 3 gdevic
#end
857
 
858 8 gdevic
#if pla[91] & pla[20] : outi/outir/outd/outdr                   "5,4,3,(5)"
859 3 gdevic
#035H T1  AB:00A DB:--  M1      1       1       fMFetch                                                                                                         alu     <        res                     H       XOR                                     P
860
#036H T2  AB:00A DB:B3  M1      MREQ RD 1       2       fMFetch                                                                 F       <                                <
861
#037H T3  AB:004 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
862 8 gdevic
#038H T4  AB:004 DB:--     RFSH MREQ    1       4       fMFetch Y                                                       B               >                               alu     >s0             0        bus     L       ADD                             *                                               NEG_OP2
863 3 gdevic
#039H T5  AB:004 DB:--  1       5                       mr                                                      B       <                                alu     <        res                     H       ADD             *       *                                                       NEG_OP2
864
#040H T6  AB:000 DB:--  2       1       fMRead                          HL                      W
865
#041H T7  AB:000 DB:21          MREQ RD 2       2       fMRead                                  HL      op3     R
866 8 gdevic
#042H T8  AB:000 DB:21          MREQ RD 2       3       fMRead          iow                                             L               >l      d                               >s0                     bus
867 3 gdevic
#043H T9  AB:000 DB:--  3       1       fIOWrite                                BC                      W
868
#044H T10 AB:000 DB:21                  WR IORQ 3       2       fIOWrite                                                                                        d       <	R	alu	>s0              bus             L       ADD                             *               S
869
#045H T11 AB:000 DB:21                  WR IORQ 3       3       fIOWrite                                                                                                                alu     <        res                     H       ADD                                                     *
870 8 gdevic
#046H T12 AB:000 DB:21                  WR IORQ 3       4       fIOWrite                Y       BZ
871 7 gdevic
#047H T13 AB:000 DB:--  4       1                                       PC                      W
872 3 gdevic
#048H T14 AB:000 DB:--  4       2                                               PC      -       R
873 7 gdevic
#049H T15 AB:000 DB:--  4       3                                       PC                      W
874 3 gdevic
#050H T16 AB:000 DB:--  4       4                                               PC      -       R
875 8 gdevic
#051H T17 AB:000 DB:--  4       5                               Y
876 3 gdevic
#end
877
 
878
// Jump Group
879
 
880
#if pla[29] : jp nn                     "4,3,3"
881
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
882
#002H T2  AB:000 DB:C3  M1      MREQ RD 1       2       fMFetch
883
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
884 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
885 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
886
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
887
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
888
#008H T8  AB:002 DB:--  3       1       fMRead                          PC                      W
889
#009H T9  AB:002 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R
890 8 gdevic
#010H T10 AB:002 DB:02          MREQ RD 3       3       fMRead                  Y       WZ                      W               W       
891 3 gdevic
#end
892
 
893
"#if pla[43] : jp cc,nn"                        "4,3,3"
894
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
895
#002H T2  AB:000 DB:C2  M1      MREQ RD 1       2       fMFetch
896
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
897 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
898 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
899
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
900
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
901
#008H T8  AB:002 DB:--  3       1       fMRead                          PC                      W
902
#009H T9  AB:002 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R
903 8 gdevic
#010H T10 AB:002 DB:02          MREQ RD 3       3       fMRead                  Y       WZ?                     W               W?      
904 3 gdevic
#end
905
 
906
#if pla[47] : jr e                      "4,3,5"
907
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
908
#002H T2  AB:000 DB:18  M1      MREQ RD 1       2       fMFetch
909
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
910 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
911 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
912
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
913 8 gdevic
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          Y
914 3 gdevic
#008H T8  AB:001 DB:--  3       1                                                                                               d       <	R	alu	>s0              bus                                     *                                                                       "Reads ""e"" from the data latch"
915 8 gdevic
#009H T9  AB:001 DB:--  3       2                                                                       PCl             >l      d                       alu     >s0                     bus     L       ADD                             *
916 3 gdevic
#010H T10 AB:001 DB:--  3       3                                                                               Z       
917
#011H T11 AB:001 DB:--  3       4                                                                       PCh             >                               alu     >s0             0        bus     L       ADC                             *                                               ?SF_NEG
918 8 gdevic
#012H T12 AB:001 DB:--  3       5                               Y       WZ                      W               W       
919 3 gdevic
#end
920
 
921
"#if pla[48] : jr ss,e"                 "4,3,(5)"
922
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
923
#002H T2  AB:000 DB:20  M1      MREQ RD 1       2       fMFetch
924
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
925 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr                                                                                                                                                                                                                              CondShort       M1/T4 evaluates a condition: force short
926 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
927
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
928 8 gdevic
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          Y       SS
929 3 gdevic
#008H T8  AB:001 DB:--  3       1                                                                                               d       <	R	alu	>s0              bus                                     *                                                                       "Reads ""e"" from the data latch"
930 8 gdevic
#009H T9  AB:001 DB:--  3       2                                                                       PCl             >l      d                       alu     >s0                     bus     L       ADD                             *
931 3 gdevic
#010H T10 AB:001 DB:--  3       3                                                                               Z       
932
#011H T11 AB:001 DB:--  3       4                                                                       PCh             >                               alu     >s0             0        bus     L       ADC                             *                                               ?SF_NEG
933 8 gdevic
#012H T12 AB:001 DB:--  3       5                               Y       WZ                      W               W       
934 3 gdevic
#end
935
 
936
#if pla[6] : jp hl                      4
937
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
938
#002H T2  AB:000 DB:E9  M1      MREQ RD 1       2       fMFetch
939
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
940 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y       HL                      W                                                                                                                                                                                       NOT_PC!
941 3 gdevic
#end
942
 
943
#if pla[26] : djnz e                    "5,3,(5)"
944
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
945
#002H T2  AB:000 DB:10  M1      MREQ RD 1       2       fMFetch
946
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
947 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y                                                       B               >h                              alu     >s0             0        bus     L       ADD                             *                                               NEG_OP2 B=B-1
948 3 gdevic
#005H T5  AB:000 DB:--  1       5                       mr                                                      B       <                                alu     <        res                     H       ADD             *                                                               NEG_OP2
949
#006H T6  AB:001 DB:--  2       1       fMRead                          PC                      W
950
#007H T7  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
951 8 gdevic
#008H T8  AB:001 DB:01          MREQ RD 2       3       fMRead          Y       ZF
952 3 gdevic
#009H T9  AB:001 DB:--  3       1                                                                                               d       <	R	alu	>s0              bus                                     *                                                                       "Reads ""e"" from the data latch"
953 8 gdevic
#010H T10 AB:001 DB:--  3       2                                                                       PCl             >l      d                       alu     >s0                     bus     L       ADD                             *
954 3 gdevic
#011H T11 AB:001 DB:--  3       3                                                                               Z       
955 8 gdevic
#012H T12 AB:001 DB:--  3       4                                                                       PCh             >h                              alu     >s0             0        bus     L       ADC                             *                                               ?SF_NEG
956
#013H T13 AB:001 DB:--  3       5                               Y       WZ                      W               W       
957 3 gdevic
#end
958
 
959
// Call and Return Group
960
 
961
#if pla[24] : call nn                   "4,3,4,3,3"
962
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
963
#002H T2  AB:000 DB:CD  M1      MREQ RD 1       2       fMFetch
964
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
965 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
966 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
967
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
968
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
969
#008H T8  AB:002 DB:--  3       1       fMRead                          PC                      W
970
#009H T9  AB:002 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R
971
#010H T10 AB:002 DB:02          MREQ RD 3       3       fMRead                                                                  W       
972
#011H T11 AB:002 DB:--  3       4                       mw              SP              -       W
973 8 gdevic
#012H T12 AB:000 DB:--  4       1       fMWrite                                         -       P       PCh             >h      u       >       W
974 3 gdevic
#013H T13 AB:000 DB:00          MREQ    4       2       fMWrite                                 SP      -       R
975
#014H T14 AB:000 DB:00          MREQ    WR      4       3       fMWrite         mw              SP              -       W
976 8 gdevic
#015H T15 AB:0FF DB:--  5       1       fMWrite                                         -       P       PCl             >l              >       W
977 3 gdevic
#016H T16 AB:0FF DB:03          MREQ    5       2       fMWrite                                 SP      -       R
978 8 gdevic
#017H T17 AB:0FF DB:03          MREQ    WR      5       3       fMWrite                 Y       WZ                      W                                                                                                                                                                                       NOT_PC!
979 3 gdevic
#end
980
 
981
"#if pla[42] : call cc,nn"                      "4,3,3/(4,3,4,3,3)"
982
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
983
#002H T2  AB:000 DB:C4  M1      MREQ RD 1       2       fMFetch
984
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
985 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
986 3 gdevic
#005H T5  AB:001 DB:--  2       1       fMRead                          PC                      W
987
#006H T6  AB:001 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
988
#007H T7  AB:001 DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
989
#008H T8  AB:002 DB:--  3       1       fMRead                          PC                      W
990
#009H T9  AB:002 DB:02          MREQ RD 3       2       fMRead                                  PC      +       R
991
#010H T10 AB:002 DB:02          MREQ RD 3       3       fMRead          CC      CC                                              W?      
992
#011H T11 AB:002 DB:--  3       4                       mw              SP              -       W
993 8 gdevic
#012H T12 AB:000 DB:--  4       1       fMWrite                                         -       P       PCh             >h      u       >       W
994 3 gdevic
#013H T13 AB:000 DB:00          MREQ    4       2       fMWrite                                 SP      -       R
995
#014H T14 AB:000 DB:00          MREQ    WR      4       3       fMWrite         mw              SP              -       W
996 8 gdevic
#015H T15 AB:0FF DB:--  5       1       fMWrite                                         -       P       PCl             >l              >       W
997 3 gdevic
#016H T16 AB:0FF DB:03          MREQ    5       2       fMWrite                                 SP      -       R
998 8 gdevic
#017H T17 AB:0FF DB:03          MREQ    WR      5       3       fMWrite                 Y       WZ                      W                                                                                                                                                                                       NOT_PC!
999 3 gdevic
#end
1000
 
1001
#if pla[35] : ret                       "4,3,3"
1002
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
1003
#002H T2  AB:000 DB:C9  M1      MREQ RD 1       2       fMFetch
1004
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
1005 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
1006 3 gdevic
#005H T5  AB:0FF DB:--  2       1       fMRead                          SP                      W
1007
#006H T6  AB:0FF DB:01          MREQ RD 2       2       fMRead                                  SP      +       R
1008
#007H T7  AB:0FF DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
1009
#008H T8  AB:000 DB:--  3       1       fMRead                          SP                      W
1010
#009H T9  AB:000 DB:C9          MREQ RD 3       2       fMRead                                  SP      +       R
1011 8 gdevic
#010H T10 AB:000 DB:C9          MREQ RD 3       3       fMRead                  Y       WZ                      W               W       
1012 3 gdevic
#end
1013
 
1014
#if pla[45] : ret cc                    "5/(5,3,3)"
1015
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
1016
#002H T2  AB:000 DB:C0  M1      MREQ RD 1       2       fMFetch
1017
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *
1018 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y
1019 3 gdevic
#005H T5  AB:000 DB:--  1       5                       mr      CC
1020
#006H T6  AB:001 DB:--  2       1       fMRead                          SP                      W
1021
#007H T7  AB:001 DB:01          MREQ RD 2       2       fMRead                                  SP      +       R
1022
#008H T8  AB:001 DB:01          MREQ RD 2       3       fMRead          mr                                                      Z       
1023
#009H T9  AB:002 DB:--  3       1       fMRead                          SP                      W
1024
#010H T10 AB:002 DB:02          MREQ RD 3       2       fMRead                                  SP      +       R
1025 8 gdevic
#011H T11 AB:002 DB:02          MREQ RD 3       3       fMRead                  Y       WZ                      W               W       
1026 3 gdevic
#end
1027
 
1028
#if pla[46] : reti/retn                 "4,3,3"
1029
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
1030
#006H T2  AB:001 DB:45  M1      MREQ RD 1       2       fMFetch
1031
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch
1032 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr                                                                                                                                                                                                                              RETN    IFF1<=IFF2
1033 3 gdevic
#009H T5  AB:001 DB:--  2       1       fMRead                          SP                      W
1034
#010H T6  AB:001 DB:45          MREQ RD 2       2       fMRead                                  SP      +       R
1035
#011H T7  AB:001 DB:45          MREQ RD 2       3       fMRead          mr                                                      Z       
1036
#012H T8  AB:002 DB:--  3       1       fMRead                          SP                      W
1037
#013H T9  AB:002 DB:01          MREQ RD 3       2       fMRead                                  SP      +       R
1038 8 gdevic
#014H T10 AB:002 DB:01          MREQ RD 3       3       fMRead                  Y       WZ                      W               W       
1039 3 gdevic
#end
1040
 
1041
#if pla[56] : rst p                     "5,3,3"
1042
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
1043
#002H T2  AB:000 DB:C7  M1      MREQ RD 1       2       fMFetch
1044
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                                                 WZ      <                        R               <        op1             0                                                                                                "MASK_543, RST_NMI, RST_INT"    RST instruction also executes on NMI and INT
1045 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y
1046 3 gdevic
#005H T5  AB:000 DB:--  1       5                       mw              SP              -       W                               d       <	R		>s0                      bus                                                                                                     Store im2 vector into the ALU op1
1047
#006H T6  AB:000 DB:--  2       1       fMWrite                                         -       P       PCh             >h      u       >       W
1048
#007H T7  AB:000 DB:00          MREQ    2       2       fMWrite                                 SP      -       R
1049
#008H T8  AB:000 DB:00          MREQ    WR      2       3       fMWrite         mw              SP              -       W
1050 8 gdevic
#009H T9  AB:0FF DB:--  3       1       fMWrite                                         -       P       PCl             >l              >       W
1051 3 gdevic
#010H T10 AB:0FF DB:01          MREQ    3       2       fMWrite                                 SP      -       R
1052
#011H T11 AB:0FF DB:01          MREQ    WR      3       3       fMWrite         INT     INT     WZ                      W                                                                                                                                                                                       NOT_PC! Value on the bus into ALU OP
1053
// INTR IM2 continues here...                                                                                                                                                                                                                                                                           Extension for IM2 interrupt mode
1054
#012H T12 AB:001 DB:--  4       1       fMRead                          I*                      W                       
1055
#013H T13 AB:001 DB:01          MREQ RD 4       2       fMRead                                  >       +       R                       >l      d                               >s0                     bus
1056
#014H T14 AB:001 DB:01          MREQ RD 4       3       fMRead          mr                                                      Z       
1057
#015H T15 AB:002 DB:--  5       1       fMRead                          I*                      W                       
1058
#016H T16 AB:002 DB:02          MREQ RD 5       2       fMRead                                          +       R
1059 8 gdevic
#017H T17 AB:002 DB:02          MREQ RD 5       3       fMRead                  Y       WZ                      W               W       
1060 3 gdevic
#end
1061
 
1062
// CB-Table opcodes
1063
 
1064
#if pla[49] : Every CB with IX/IY                       "4,3,5,+"
1065
#005H T1  AB:001 DB:--  M1      1       1       fMFetch
1066
#006H T2  AB:001 DB:CB  M1      MREQ RD 1       2       fMFetch
1067
#007H T3  AB:001 DB:--     RFSH 1       3       fMFetch                                                         AF              >                               >       >s0             bus     bus                             *       *       *       *       *       *                       CB
1068 8 gdevic
#008H T4  AB:001 DB:--     RFSH MREQ    1       4       fMFetch Y       mr
1069 3 gdevic
#009H T5  AB:002 DB:--  2       1       fMRead                          PC                      W
1070
#010H T6  AB:002 DB:01          MREQ RD 2       2       fMRead                                  PC      +       R
1071
#011H T7  AB:002 DB:01          MREQ RD 2       3       fMRead          mr
1072
#012H T8  AB:003 DB:--  3       1       fMRead                          PC                      W                                                                                                                                                                                       WZ=IX+d
1073
#013H T9  AB:003 DB:00          MREQ RD 3       2       fMRead                                  PC      +       R                                                                                                                                                                                       WZ=IX+d
1074
#014H T10 AB:003 DB:00          MREQ RD 3       3       fMRead                                                                                                                                                                                                                                          WZ=IX+d Loads the opcode byte in parallel
1075
#015H T11 AB:003 DB:--  3       4                                                                                                                                                                                                                                                       WZ=IX+d
1076
#016H T12 AB:003 DB:--  3       5                       mr                                                                                                                                                                                                                              WZ=IX+d
1077
#017H T13 AB:000 DB:--  4       1                                                                                                               R               >bs             bus     bus                                                                                             OpcodeToIR      Loads instruction register; starts the execute cycle
1078
// Loading a new instruction immediately changes PLA wires and continues into the new effective instructions' M4/T1 cycle
1079
#end
1080
 
1081
// Special Purposes PLA Entries
1082
 
1083
#if pla[3] : IX/IY                      4
1084
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
1085
#002H T2  AB:000 DB:DD  M1      MREQ RD 1       2       fMFetch                                                                                                                                                                                                                                         IX_IY
1086
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
1087 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                                                                                                                                                                                                       NO_INTS "At last M/T, inhibit interrupts"
1088 3 gdevic
#end
1089
 
1090
#if pla[44] : CB prefix                 4
1091
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
1092
#002H T2  AB:000 DB:CB  M1      MREQ RD 1       2       fMFetch                                                                                                                                                                                                                                         CB
1093
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
1094 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                                                                                                                                                                                                       NO_INTS "At last M/T, inhibit interrupts"
1095 3 gdevic
"#end Only set CB ff and clear ED, XX ff"
1096
 
1097
#if pla[51] : ED prefix                 4
1098
#001H T1  AB:000 DB:--  M1      1       1       fMFetch
1099
#002H T2  AB:000 DB:ED  M1      MREQ RD 1       2       fMFetch                                                                                                                                                                                                                                         ED
1100
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch
1101 8 gdevic
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch Y               Y                                                                                                                                                                                                                       NO_INTS "At last M/T, inhibit interrupts"
1102 3 gdevic
"#end Only set ED ff and clear CB, XX ff"
1103
 
1104
#if pla[76] : ALU CP
1105
#always                                                                                                                                                                                 CP                                              1
1106
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                                                                                                                                                 V                                               Update P/V once on a high nibble phase
1107
#end                                                                                                                                                                                                                                                                            Does not store the result!
1108
 
1109
#if pla[78] : ALU SUB
1110
#always                                                                                                                                                                                 SUB                                             1
1111
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <                                                                                                        *               V                                               Update P/V and store result to A
1112
#end
1113
 
1114
#if pla[79] : ALU SBC
1115
#always                                                                                                                                                                                 SBC                                             1
1116
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <                                                                                                        *               V                                               Update P/V and store result to A
1117
#end
1118
 
1119
#if pla[80] : ALU ADC
1120
#always                                                                                                                                                                                 ADC                                             0
1121
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <                                                                                                        *               V                                               Update P/V and store result to A
1122
#end
1123
 
1124
#if pla[84] : ALU ADD
1125
#always                                                                                                                                                                                 ADD                                             0
1126
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <                                                                                                        *               V                                               Update P/V and store result to A
1127
#end
1128
 
1129
#if pla[85] : ALU AND
1130
#always                                                                                                                                                                                 AND                                             0
1131
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <                                                                                                        *               P                                               Update P/V and store result to A
1132
#002H T2  AB:000 DB:A0  M1      MREQ RD 1       2       fMFetch                                                                                                                                                                                                                 0                                AND clears CF
1133
#end
1134
 
1135
#if pla[86] : ALU OR
1136
#always                                                                                                                                                                                 OR                                              0
1137
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <                                                                                                        *               P                                               Update P/V and store result to A
1138
#002H T2  AB:000 DB:B0  M1      MREQ RD 1       2       fMFetch                                                                                                                                                                                                                 0                                OR clears CF
1139
#end
1140
 
1141
#if pla[88] : ALU XOR
1142
#always                                                                                                                                                                                 XOR                                             0
1143
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                                                 A       <                                                                                                        *               P                                               Update P/V and store result to A
1144
#002H T2  AB:000 DB:A8  M1      MREQ RD 1       2       fMFetch                                                                                                                                                                                                                 0                                XOR clears CF
1145
#end
1146
 
1147
// State machine to compute (IX+d)
1148
#if ixy_d : Compute WZ=IX+d
1149
#001H T1 any M-cycle    ?       1                                                                                               d       <	R	alu	>s0              bus                                     *                                                                       "Reads ""d"" from the data latch"
1150 8 gdevic
#002H T2        ?       2                                                                       L               >l      d                       alu     >s0                     bus     L       ADD                             *
1151 3 gdevic
#003H T3        ?       3                                                                               Z       
1152
#004H T4        ?       4                                                                       H               >                               alu     >s0             0        bus     L       ADC                             *                               R               ?SF_NEG Stores result into WZ
1153
#005H T5        ?       5                                       WZ                      W               W       
1154
#end
1155
 
1156
// Default instruction fetch (M1) state machine
1157 8 gdevic
#if 1 :
1158
#001H T1  AB:000 DB:--  M1      1       1       fMFetch                                 PC      +       RL                                                                                                                                                                                              Fetch/execute overlap
1159 3 gdevic
#002H T2  AB:000 DB:CB  M1      MREQ RD 1       2       fMFetch                         IR                      W                                               R                                                                                                                                       "CLR_IX_IY, CLR_CB_ED, OpcodeToIR, OverrideIR"  Prepares for the next execution cycle
1160
#003H T3  AB:000 DB:--     RFSH 1       3       fMFetch                                 IR      +       RL                                                                                                                                                                                      Limit6  "Fetch opcode, evaluate flags"
1161
#004H T4  AB:000 DB:--     RFSH MREQ    1       4       fMFetch                                                                                                                                                                                                                                         EvalCond
1162
#end
1163 8 gdevic
 
1164
"// For all undecoded instructions, at M1/T4 advance a byte to the next opcode"
1165
#if ~validPLA : A catch-all case
1166
#001H   1       4                               Y
1167
#end
1168
 
1169
// The last cycle of an instruction is also the first cycle of the next one
1170
#if setM1 :
1171
#always                                                 PC                      W                                                                                                                                                                                               Fetch/execute overlap
1172
#end

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