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[/] [a-z80/] [trunk/] [cpu/] [control/] [exec_module.vh] - Blame information for rev 19

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Line No. Rev Author Line
1 6 gdevic 
// Automatically generated by genref.py
2 
 
3 
// Module: control/decode_state.v
4 8 gdevic 
output reg ctl_state_iy_set,
5 
output reg ctl_state_ixiy_clr,
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output reg ctl_state_ixiy_we,
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output reg ctl_state_halt_set,
8 
output reg ctl_state_tbl_ed_set,
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output reg ctl_state_tbl_cb_set,
10 
output reg ctl_state_alu,
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output reg ctl_repeat_we,
12 13 gdevic 
output reg ctl_state_tbl_we,
13 6 gdevic 
 
14 
// Module: control/interrupts.v
15 8 gdevic 
output reg ctl_iff1_iff2,
16 
output reg ctl_iffx_we,
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output reg ctl_iffx_bit,
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output reg ctl_im_we,
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output reg ctl_no_ints,
20 6 gdevic 
 
21 
// Module: control/ir.v
22 8 gdevic 
output reg ctl_ir_we,
23 6 gdevic 
 
24 
// Module: control/memory_ifc.v
25 8 gdevic 
output reg ctl_mRead,
26 
output reg ctl_mWrite,
27 
output reg ctl_iorw,
28 6 gdevic 
 
29 
// Module: alu/alu_control.v
30 8 gdevic 
output reg ctl_shift_en,
31 
output reg ctl_daa_oe,
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output reg ctl_alu_op_low,
33 
output reg ctl_cond_short,
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output reg ctl_alu_core_hf,
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output reg ctl_eval_cond,
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output reg ctl_66_oe,
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output reg [1:0] ctl_pf_sel,
38 6 gdevic 
 
39 
// Module: alu/alu_select.v
40 8 gdevic 
output reg ctl_alu_oe,
41 
output reg ctl_alu_shift_oe,
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output reg ctl_alu_op2_oe,
43 
output reg ctl_alu_res_oe,
44 
output reg ctl_alu_op1_oe,
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output reg ctl_alu_bs_oe,
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output reg ctl_alu_op1_sel_bus,
47 
output reg ctl_alu_op1_sel_low,
48 
output reg ctl_alu_op1_sel_zero,
49 
output reg ctl_alu_op2_sel_zero,
50 
output reg ctl_alu_op2_sel_bus,
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output reg ctl_alu_op2_sel_lq,
52 
output reg ctl_alu_sel_op2_neg,
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output reg ctl_alu_sel_op2_high,
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output reg ctl_alu_core_R,
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output reg ctl_alu_core_V,
56 
output reg ctl_alu_core_S,
57 6 gdevic 
 
58 
// Module: alu/alu_flags.v
59 8 gdevic 
output reg ctl_flags_oe,
60 
output reg ctl_flags_bus,
61 
output reg ctl_flags_alu,
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output reg ctl_flags_nf_set,
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output reg ctl_flags_cf_set,
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output reg ctl_flags_cf_cpl,
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output reg ctl_flags_cf_we,
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output reg ctl_flags_sz_we,
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output reg ctl_flags_xy_we,
68 
output reg ctl_flags_hf_we,
69 
output reg ctl_flags_pf_we,
70 
output reg ctl_flags_nf_we,
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output reg ctl_flags_cf2_we,
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output reg ctl_flags_hf_cpl,
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output reg ctl_flags_use_cf2,
74 
output reg ctl_flags_hf2_we,
75 
output reg ctl_flags_nf_clr,
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output reg ctl_alu_zero_16bit,
77 
output reg ctl_flags_cf2_sel_shift,
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output reg ctl_flags_cf2_sel_daa,
79 6 gdevic 
 
80 
// Module: registers/reg_file.v
81 8 gdevic 
output reg ctl_sw_4u,
82 
output reg ctl_reg_in_hi,
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output reg ctl_reg_in_lo,
84 
output reg ctl_reg_out_lo,
85 
output reg ctl_reg_out_hi,
86 6 gdevic 
 
87 
// Module: registers/reg_control.v
88 8 gdevic 
output reg ctl_reg_exx,
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output reg ctl_reg_ex_af,
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output reg ctl_reg_ex_de_hl,
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output reg ctl_reg_use_sp,
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output reg ctl_reg_sel_pc,
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output reg ctl_reg_sel_ir,
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output reg ctl_reg_sel_wz,
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output reg ctl_reg_gp_we,
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output reg ctl_reg_not_pc,
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output reg ctl_reg_sys_we_lo,
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output reg ctl_reg_sys_we_hi,
99 
output reg ctl_reg_sys_we,
100 
output reg ctl_sw_4d,
101 
output reg [1:0] ctl_reg_gp_hilo,
102 
output reg [1:0] ctl_reg_gp_sel,
103 
output reg [1:0] ctl_reg_sys_hilo,
104 6 gdevic 
 
105 
// Module: bus/address_latch.v
106 8 gdevic 
output reg ctl_inc_cy,
107 
output reg ctl_inc_dec,
108 
output reg ctl_al_we,
109 
output reg ctl_inc_limit6,
110 
output reg ctl_bus_inc_oe,
111 
output reg ctl_apin_mux,
112 
output reg ctl_apin_mux2,
113 6 gdevic 
 
114 
// Module: bus/bus_control.v
115 8 gdevic 
output reg ctl_bus_ff_oe,
116 
output reg ctl_bus_zero_oe,
117 6 gdevic 
 
118 8 gdevic 
// Module: bus/bus_switch.v
119 
output reg ctl_sw_1u,
120 
output reg ctl_sw_1d,
121 
output reg ctl_sw_2u,
122 
output reg ctl_sw_2d,
123 
output reg ctl_sw_mask543_en,
124 6 gdevic 
 
125 
// Module: bus/data_pins.v
126 8 gdevic 
output reg ctl_bus_db_we,
127 
output reg ctl_bus_db_oe,

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