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#!/usr/bin/env python3
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#
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# This script reads 'exec_matrix.vh' file and compiles it into an alternate format
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# that can be used with Xilinx toolchain.
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#
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# Xilinx synthesis tool is effectively not capable of processing that file.
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# Altera Quartus has no problems compiling it.
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#
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#-------------------------------------------------------------------------------
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# Copyright (C) 2016 Goran Devic
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#-------------------------------------------------------------------------------
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import os
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import io
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import copy
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import tokenize
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from io import BytesIO
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from tokenize import NAME, INDENT, DEDENT, ENCODING
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# Input file to process
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fname = "exec_matrix.vh"
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# Output file to contain compiled version of the input
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oname = "exec_matrix_compiled.vh"
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# Output file to contain a list of temporary wires used by the compiled Verilog file
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tname = "temp_wires.vh"
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# Define a list of control signals that are 2-bits wide
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ctls_wide = ['ctl_reg_gp_sel', 'ctl_reg_gp_hilo', 'ctl_reg_sys_hilo', 'ctl_pf_sel']
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# Help recognizing control signal names
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def is_ctl(name):
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return name.startswith('ctl_') or name=='validPLA' or name=='nextM' or name=='setM1' \
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or name=='fFetch' or name=='fMRead' or name=='fMWrite' or name=='fIORead' or name=='fIOWrite' \
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gdevic |
or name=='ixy_d' or name=='setIXIY' or name=='nonRep' or name=='pc_inc_hold'
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gdevic |
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def str2tok(s):
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t = io.BytesIO(bytes(s.encode()))
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return list(tokenize.tokenize(t.readline))[1:-1]
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def tok2str(tokens):
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line = [ tokens[n][m].string for n in range(len(tokens)) for m in range(len(tokens[n])) ]
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return ''.join(line)
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def get_rval(tokens, i):
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assert (tokens[i+1].string=='=' or tokens[i+1].string=='|=')
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paren = list(str2tok('()'))
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rval = paren[:1]
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while (tokens[i+2].string!=';'):
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rval.append(tokens[i+2])
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i += 1
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rval.extend(paren[1:2])
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return [rval]
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def decomment(s):
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i = s.find('//') # Remove trailing comments from a line
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if i>=0:
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return s[:i]
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i = s.find('/*') # Remove comments within a line
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j = s.find('*/')
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if i>=0 and j>=0:
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return decomment(s[:i] + s[j+2:])
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return s
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#--------------------------------------------------------------------------------
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# Generate a sequential-or form for all control wires
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#--------------------------------------------------------------------------------
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def sequential_or(f, t, tokens):
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incond = False # Inside an "if" condition state
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cond = [] # Condition nested lists
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ccond = [] # Currently scanned condition list
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ctls = {} # Dictionary of control wires and their equations
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ccwires = [] # List of wires at the current condition list level
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i = 0 # Current index into the tokens list
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while i < len(tokens):
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tok = tokens[i]
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(toknum, tokval, _, _, _) = tok
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if incond and not (toknum==NAME and tokval=='begin'):
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if toknum != DEDENT and toknum != INDENT:
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ccond.append(tok)
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if toknum==NAME:
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if tokval=='if':
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incond = True
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if tokval=='begin': # Push a condition list
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incond = False
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cond.append(copy.deepcopy(ccond))
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ccond.clear()
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ccwires.clear()
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if tokval=='end': # Pop a condition list
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cond.pop()
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if is_ctl(tokval) and not incond:
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rval = get_rval(tokens, i)
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linesub = tok2str(cond)
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rhs = tok2str(rval)
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line = "{0} = {0} | ".format(tokval)
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if tokval in ccwires: # Check for duplicate assignments
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hint = [ cond[n][m].string for n in range(len(cond)) for m in range(len(cond[n])) ]
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print ("WARNING: {0}: Multiple assignment of {1}".format(''.join(hint), tokval))
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ccwires.append(tokval) # Track this wire as assigned at this condition level
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if tokval in ctls_wide:
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tr = linesub.translate(str.maketrans(dict.fromkeys('~','n'))) # Make temporary name
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tmpname = "{0}_{1}_{2}".format(tokval, tr.translate(str.maketrans(dict.fromkeys('[]()&',None))), len(ccwires))
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t.write("reg {0};\n".format(tmpname))
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line = "{0} = {1};\n".format(tmpname, linesub) + line
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line += "({{{0},{0}}}){1}".format(tmpname, rhs)
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else:
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line += linesub + rhs
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line = line.replace(')(', ')&(')
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line = line.replace('&&', '&')
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line = line.replace('(1)&', '')
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line = line.replace('&(1)', '')
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i += len(rval[0])
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f.write ('{0};\n'.format(line))
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i += 1
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#--------------------------------------------------------------------------------
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tokens = []
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# Input file which we are processing
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with open(fname) as f:
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lines = f.readlines()
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for line in lines:
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src = decomment(line)
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src = bytes(src.encode())
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src = io.BytesIO(src)
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toklist = list(tokenize.tokenize(src.readline))
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tokens.extend(toklist)
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with open(oname, 'w') as f:
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with open(tname, 'w') as t:
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f.write("// Automatically generated by gencompile.py\n\n")
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t.write("// Automatically generated by gencompile.py\n\n")
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sequential_or(f, t, tokens)
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# Touch a file that includes 'exec_matrix_compiled.vh' to ensure it will recompile correctly
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os.utime("execute.v", None)
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